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10767ccb | 1 | /* |
1d6f9720 WD |
2 | * ueberarbeitet durch Christoph Seyfert |
3 | * | |
414eec35 | 4 | * (C) Copyright 2004-2005 DENX Software Engineering, |
10767ccb WD |
5 | * Wolfgang Grandegger <wg@denx.de> |
6 | * (C) Copyright 2003 | |
7 | * DAVE Srl | |
8 | * | |
9 | * http://www.dave-tech.it | |
10 | * http://www.wawnet.biz | |
11 | * mailto:info@wawnet.biz | |
12 | * | |
13 | * Credits: Stefan Roese, Wolfgang Denk | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | ||
31 | /* | |
32 | * board/config.h - configuration options, board specific | |
33 | */ | |
34 | ||
35 | #ifndef __CONFIG_H | |
36 | #define __CONFIG_H | |
37 | ||
38 | #define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */ | |
39 | #define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */ | |
40 | #define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */ | |
41 | #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL | |
42 | #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA | |
43 | #endif | |
44 | ||
1d6f9720 WD |
45 | /* Only one of the following two symbols must be defined (default is 25 MHz) |
46 | * CONFIG_PPCHAMELEON_CLK_25 | |
47 | * CONFIG_PPCHAMELEON_CLK_33 | |
48 | */ | |
49 | #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) | |
50 | #define CONFIG_PPCHAMELEON_CLK_25 | |
51 | #endif | |
52 | ||
53 | #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) | |
54 | #error "* Two external frequencies (SysClk) are defined! *" | |
55 | #endif | |
56 | ||
57 | #undef CONFIG_PPCHAMELEON_SMI712 | |
58 | ||
10767ccb WD |
59 | /* |
60 | * Debug stuff | |
61 | */ | |
62 | #undef __DEBUG_START_FROM_SRAM__ | |
63 | #define __DISABLE_MACHINE_EXCEPTION__ | |
64 | ||
65 | #ifdef __DEBUG_START_FROM_SRAM__ | |
6d0f6bcf | 66 | #define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4 |
10767ccb WD |
67 | #endif |
68 | ||
69 | /* | |
70 | * High Level Configuration Options | |
71 | * (easy to change) | |
72 | */ | |
73 | ||
74 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
75 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
76 | #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ | |
77 | ||
78 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ | |
79 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
80 | ||
1d6f9720 WD |
81 | #ifdef CONFIG_PPCHAMELEON_CLK_25 |
82 | # define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ | |
83 | #elif (defined (CONFIG_PPCHAMELEON_CLK_33)) | |
10767ccb | 84 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
1d6f9720 WD |
85 | #else |
86 | # error "* External frequency (SysClk) not defined! *" | |
87 | #endif | |
10767ccb | 88 | |
1d6f9720 | 89 | #define CONFIG_UART1_CONSOLE 1 /* Use second UART */ |
10767ccb WD |
90 | #define CONFIG_BAUDRATE 115200 |
91 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
92 | ||
1d6f9720 WD |
93 | #define CONFIG_VERSION_VARIABLE 1 /* add version variable */ |
94 | #define CONFIG_IDENT_STRING "1" | |
95 | ||
10767ccb WD |
96 | #undef CONFIG_BOOTARGS |
97 | ||
98 | /* Ethernet stuff */ | |
99 | #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ | |
1d6f9720 | 100 | #define CONFIG_ETHADDR 00:50:C2:1E:AF:FE |
e2ffd59b | 101 | #define CONFIG_HAS_ETH1 |
1d6f9720 | 102 | #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD |
10767ccb WD |
103 | |
104 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 105 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
10767ccb WD |
106 | |
107 | ||
108 | #undef CONFIG_EXT_PHY | |
1d6f9720 | 109 | #define CONFIG_NET_MULTI 1 |
10767ccb WD |
110 | |
111 | #define CONFIG_MII 1 /* MII PHY management */ | |
112 | #ifndef CONFIG_EXT_PHY | |
bf41886f | 113 | #define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ |
3c71f3e8 | 114 | #define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */ |
10767ccb WD |
115 | #else |
116 | #define CONFIG_PHY_ADDR 2 /* PHY address */ | |
117 | #endif | |
118 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ | |
119 | ||
414eec35 WD |
120 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
121 | ||
49cf7e8e | 122 | |
11799434 JL |
123 | /* |
124 | * BOOTP options | |
125 | */ | |
126 | #define CONFIG_BOOTP_BOOTFILESIZE | |
127 | #define CONFIG_BOOTP_BOOTPATH | |
128 | #define CONFIG_BOOTP_GATEWAY | |
129 | #define CONFIG_BOOTP_HOSTNAME | |
130 | ||
131 | ||
49cf7e8e JL |
132 | /* |
133 | * Command line configuration. | |
134 | */ | |
135 | #include <config_cmd_default.h> | |
136 | ||
137 | #define CONFIG_CMD_DHCP | |
138 | #define CONFIG_CMD_ELF | |
139 | #define CONFIG_CMD_EEPROM | |
140 | #define CONFIG_CMD_I2C | |
141 | #define CONFIG_CMD_IRQ | |
142 | #define CONFIG_CMD_JFFS2 | |
143 | #define CONFIG_CMD_MII | |
144 | #define CONFIG_CMD_NAND | |
145 | #define CONFIG_CMD_NFS | |
146 | #define CONFIG_CMD_SNTP | |
147 | ||
10767ccb WD |
148 | |
149 | #define CONFIG_MAC_PARTITION | |
150 | #define CONFIG_DOS_PARTITION | |
151 | ||
10767ccb WD |
152 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
153 | ||
154 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ | |
6d0f6bcf | 155 | #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ |
10767ccb WD |
156 | |
157 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
158 | ||
159 | /* | |
160 | * Miscellaneous configurable options | |
161 | */ | |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
163 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
10767ccb | 164 | |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
166 | #ifdef CONFIG_SYS_HUSH_PARSER | |
167 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
10767ccb WD |
168 | #endif |
169 | ||
49cf7e8e | 170 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 171 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
10767ccb | 172 | #else |
6d0f6bcf | 173 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
10767ccb | 174 | #endif |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
176 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
177 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
10767ccb | 178 | |
6d0f6bcf | 179 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
10767ccb | 180 | |
6d0f6bcf | 181 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
10767ccb | 182 | |
6d0f6bcf JCPV |
183 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
184 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
10767ccb | 185 | |
6d0f6bcf | 186 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 187 | #define CONFIG_SYS_BASE_BAUD 691200 |
10767ccb WD |
188 | |
189 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 190 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
10767ccb WD |
191 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
192 | 57600, 115200, 230400, 460800, 921600 } | |
193 | ||
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
195 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
10767ccb | 196 | |
6d0f6bcf | 197 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
10767ccb WD |
198 | |
199 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
200 | ||
201 | /*----------------------------------------------------------------------- | |
202 | * NAND-FLASH stuff | |
203 | *----------------------------------------------------------------------- | |
204 | */ | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_NAND0_BASE 0xFF400000 |
206 | #define CONFIG_SYS_NAND1_BASE 0xFF000000 | |
207 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE } | |
6db39708 | 208 | #define NAND_BIG_DELAY_US 25 |
10767ccb WD |
209 | |
210 | /* For CATcenter there is only NAND on the module */ | |
6d0f6bcf | 211 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
10767ccb WD |
212 | #define SECTORSIZE 512 |
213 | #define NAND_NO_RB | |
214 | ||
215 | #define ADDR_COLUMN 1 | |
216 | #define ADDR_PAGE 2 | |
217 | #define ADDR_COLUMN_PAGE 3 | |
218 | ||
219 | #define NAND_ChipID_UNKNOWN 0x00 | |
220 | #define NAND_MAX_FLOORS 1 | |
10767ccb | 221 | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
223 | #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
224 | #define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
225 | #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
10767ccb | 226 | |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ |
228 | #define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ | |
229 | #define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ | |
230 | #define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ | |
10767ccb WD |
231 | |
232 | ||
6db39708 | 233 | #define MACRO_NAND_DISABLE_CE(nandptr) do \ |
10767ccb | 234 | { \ |
6db39708 | 235 | switch((unsigned long)nandptr) \ |
10767ccb | 236 | { \ |
6d0f6bcf JCPV |
237 | case CONFIG_SYS_NAND0_BASE: \ |
238 | out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \ | |
10767ccb | 239 | break; \ |
6d0f6bcf JCPV |
240 | case CONFIG_SYS_NAND1_BASE: \ |
241 | out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \ | |
10767ccb WD |
242 | break; \ |
243 | } \ | |
244 | } while(0) | |
245 | ||
6db39708 | 246 | #define MACRO_NAND_ENABLE_CE(nandptr) do \ |
10767ccb | 247 | { \ |
6db39708 | 248 | switch((unsigned long)nandptr) \ |
10767ccb | 249 | { \ |
6d0f6bcf JCPV |
250 | case CONFIG_SYS_NAND0_BASE: \ |
251 | out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \ | |
10767ccb | 252 | break; \ |
6d0f6bcf JCPV |
253 | case CONFIG_SYS_NAND1_BASE: \ |
254 | out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \ | |
10767ccb WD |
255 | break; \ |
256 | } \ | |
257 | } while(0) | |
258 | ||
6db39708 | 259 | #define MACRO_NAND_CTL_CLRALE(nandptr) do \ |
10767ccb WD |
260 | { \ |
261 | switch((unsigned long)nandptr) \ | |
262 | { \ | |
6d0f6bcf JCPV |
263 | case CONFIG_SYS_NAND0_BASE: \ |
264 | out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \ | |
10767ccb | 265 | break; \ |
6d0f6bcf JCPV |
266 | case CONFIG_SYS_NAND1_BASE: \ |
267 | out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \ | |
10767ccb WD |
268 | break; \ |
269 | } \ | |
270 | } while(0) | |
271 | ||
6db39708 | 272 | #define MACRO_NAND_CTL_SETALE(nandptr) do \ |
10767ccb WD |
273 | { \ |
274 | switch((unsigned long)nandptr) \ | |
275 | { \ | |
6d0f6bcf JCPV |
276 | case CONFIG_SYS_NAND0_BASE: \ |
277 | out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \ | |
10767ccb | 278 | break; \ |
6d0f6bcf JCPV |
279 | case CONFIG_SYS_NAND1_BASE: \ |
280 | out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \ | |
10767ccb WD |
281 | break; \ |
282 | } \ | |
283 | } while(0) | |
284 | ||
6db39708 | 285 | #define MACRO_NAND_CTL_CLRCLE(nandptr) do \ |
10767ccb WD |
286 | { \ |
287 | switch((unsigned long)nandptr) \ | |
288 | { \ | |
6d0f6bcf JCPV |
289 | case CONFIG_SYS_NAND0_BASE: \ |
290 | out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \ | |
10767ccb | 291 | break; \ |
6d0f6bcf JCPV |
292 | case CONFIG_SYS_NAND1_BASE: \ |
293 | out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \ | |
10767ccb WD |
294 | break; \ |
295 | } \ | |
296 | } while(0) | |
297 | ||
6db39708 | 298 | #define MACRO_NAND_CTL_SETCLE(nandptr) do { \ |
10767ccb | 299 | switch((unsigned long)nandptr) { \ |
6d0f6bcf JCPV |
300 | case CONFIG_SYS_NAND0_BASE: \ |
301 | out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \ | |
10767ccb | 302 | break; \ |
6d0f6bcf JCPV |
303 | case CONFIG_SYS_NAND1_BASE: \ |
304 | out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \ | |
10767ccb WD |
305 | break; \ |
306 | } \ | |
307 | } while(0) | |
308 | ||
309 | #ifdef NAND_NO_RB | |
310 | /* constant delay (see also tR in the datasheet) */ | |
311 | #define NAND_WAIT_READY(nand) do { \ | |
312 | udelay(12); \ | |
313 | } while (0) | |
314 | #else | |
315 | /* use the R/B pin */ | |
316 | /* TBD */ | |
317 | #endif | |
318 | ||
319 | #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) | |
320 | #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) | |
321 | #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) | |
322 | #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) | |
323 | ||
324 | /*----------------------------------------------------------------------- | |
325 | * PCI stuff | |
326 | *----------------------------------------------------------------------- | |
327 | */ | |
328 | #if 0 /* No PCI on CATcenter */ | |
329 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
330 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
331 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
332 | ||
333 | #define CONFIG_PCI /* include pci support */ | |
334 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
335 | #undef CONFIG_PCI_PNP /* do pci plug-and-play */ | |
336 | /* resource configuration */ | |
337 | ||
338 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
339 | ||
6d0f6bcf JCPV |
340 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ |
341 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ | |
342 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
1d6f9720 | 343 | |
6d0f6bcf JCPV |
344 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ |
345 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
346 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
347 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
348 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
349 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
10767ccb WD |
350 | #endif /* No PCI */ |
351 | ||
352 | /*----------------------------------------------------------------------- | |
353 | * Start addresses for the final memory configuration | |
354 | * (Set up by the startup code) | |
6d0f6bcf | 355 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
10767ccb | 356 | */ |
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
358 | #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 | |
359 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
360 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ | |
361 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ | |
10767ccb WD |
362 | |
363 | /* | |
364 | * For booting Linux, the board info and command line data | |
365 | * have to be in the first 8 MB of memory, since this is | |
366 | * the maximum mapped by the Linux kernel during initialization. | |
367 | */ | |
6d0f6bcf | 368 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
10767ccb WD |
369 | /*----------------------------------------------------------------------- |
370 | * FLASH organization | |
371 | */ | |
6d0f6bcf JCPV |
372 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
373 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
10767ccb | 374 | |
6d0f6bcf JCPV |
375 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
376 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
10767ccb | 377 | |
6d0f6bcf JCPV |
378 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
379 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
380 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
10767ccb WD |
381 | /* |
382 | * The following defines are added for buggy IOP480 byte interface. | |
383 | * All other boards should use the standard values (CPCI405 etc.) | |
384 | */ | |
6d0f6bcf JCPV |
385 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
386 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
387 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
10767ccb | 388 | |
6d0f6bcf | 389 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
10767ccb | 390 | |
10767ccb WD |
391 | /*----------------------------------------------------------------------- |
392 | * Environment Variable setup | |
393 | */ | |
5a1aceb0 | 394 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
0e8d1586 JCPV |
395 | #define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ |
396 | #define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ | |
397 | #define CONFIG_ENV_ADDR_REDUND 0xFFFFA000 | |
398 | #define CONFIG_ENV_SIZE_REDUND 0x2000 | |
10767ccb | 399 | |
6d0f6bcf | 400 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
67c31036 | 401 | |
6d0f6bcf JCPV |
402 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ |
403 | #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ | |
10767ccb WD |
404 | |
405 | /*----------------------------------------------------------------------- | |
406 | * I2C EEPROM (CAT24WC16) for environment | |
407 | */ | |
408 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
6d0f6bcf JCPV |
409 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
410 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
10767ccb | 411 | |
6d0f6bcf JCPV |
412 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
413 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
10767ccb | 414 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
415 | /*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ |
416 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
10767ccb WD |
417 | /* 16 byte page write mode using*/ |
418 | /* last 4 bits of the address */ | |
6d0f6bcf | 419 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
10767ccb WD |
420 | |
421 | /*----------------------------------------------------------------------- | |
422 | * Cache Configuration | |
423 | */ | |
6d0f6bcf | 424 | #define CONFIG_SYS_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ |
10767ccb | 425 | /* have only 8kB, 16kB is save here */ |
6d0f6bcf | 426 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* ... */ |
49cf7e8e | 427 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 428 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
10767ccb WD |
429 | #endif |
430 | ||
431 | /* | |
432 | * Init Memory Controller: | |
433 | * | |
434 | * BR0/1 and OR0/1 (FLASH) | |
435 | */ | |
436 | ||
437 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ | |
438 | ||
439 | /*----------------------------------------------------------------------- | |
440 | * External Bus Controller (EBC) Setup | |
441 | */ | |
442 | ||
443 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
444 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
445 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
10767ccb WD |
446 | |
447 | /* Memory Bank 1 (External SRAM) initialization */ | |
448 | /* Since this must replace NOR Flash, we use the same settings for CS0 */ | |
6d0f6bcf JCPV |
449 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
450 | #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ | |
10767ccb WD |
451 | |
452 | /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */ | |
6d0f6bcf JCPV |
453 | #define CONFIG_SYS_EBC_PB2AP 0x92015480 |
454 | #define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */ | |
10767ccb WD |
455 | |
456 | /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */ | |
6d0f6bcf JCPV |
457 | #define CONFIG_SYS_EBC_PB3AP 0x92015480 |
458 | #define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ | |
10767ccb | 459 | |
1d6f9720 WD |
460 | #ifdef CONFIG_PPCHAMELEON_SMI712 |
461 | /* | |
462 | * Video console (graphic: SMI LynxEM) | |
463 | */ | |
464 | #define CONFIG_VIDEO | |
465 | #define CONFIG_CFB_CONSOLE | |
466 | #define CONFIG_VIDEO_SMI_LYNXEM | |
467 | #define CONFIG_VIDEO_LOGO | |
468 | /*#define CONFIG_VIDEO_BMP_LOGO*/ | |
469 | #define CONFIG_CONSOLE_EXTRA_INFO | |
470 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
471 | /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ | |
6d0f6bcf | 472 | #define CONFIG_SYS_ISA_IO 0xE8000000 |
7817cb20 | 473 | /* see also drivers/video/videomodes.c */ |
6d0f6bcf | 474 | #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303 |
10767ccb WD |
475 | #endif |
476 | ||
477 | /*----------------------------------------------------------------------- | |
478 | * FPGA stuff | |
479 | */ | |
480 | /* FPGA internal regs */ | |
6d0f6bcf JCPV |
481 | #define CONFIG_SYS_FPGA_MODE 0x00 |
482 | #define CONFIG_SYS_FPGA_STATUS 0x02 | |
483 | #define CONFIG_SYS_FPGA_TS 0x04 | |
484 | #define CONFIG_SYS_FPGA_TS_LOW 0x06 | |
485 | #define CONFIG_SYS_FPGA_TS_CAP0 0x10 | |
486 | #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 | |
487 | #define CONFIG_SYS_FPGA_TS_CAP1 0x14 | |
488 | #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 | |
489 | #define CONFIG_SYS_FPGA_TS_CAP2 0x18 | |
490 | #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a | |
491 | #define CONFIG_SYS_FPGA_TS_CAP3 0x1c | |
492 | #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e | |
10767ccb WD |
493 | |
494 | /* FPGA Mode Reg */ | |
6d0f6bcf JCPV |
495 | #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 |
496 | #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 | |
497 | #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 | |
498 | #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 | |
10767ccb WD |
499 | |
500 | /* FPGA Status Reg */ | |
6d0f6bcf JCPV |
501 | #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 |
502 | #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 | |
503 | #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 | |
504 | #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 | |
505 | #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 | |
10767ccb | 506 | |
6d0f6bcf JCPV |
507 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
508 | #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
10767ccb WD |
509 | |
510 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
511 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
512 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
513 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
514 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
515 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
10767ccb WD |
516 | |
517 | /*----------------------------------------------------------------------- | |
518 | * Definitions for initial stack pointer and data area (in data cache) | |
519 | */ | |
520 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 521 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
10767ccb WD |
522 | |
523 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
524 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
525 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
526 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
527 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ | |
10767ccb | 528 | |
6d0f6bcf JCPV |
529 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
530 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
531 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
10767ccb WD |
532 | |
533 | /*----------------------------------------------------------------------- | |
534 | * Definitions for GPIO setup (PPC405EP specific) | |
535 | * | |
536 | * GPIO0[0] - External Bus Controller BLAST output | |
537 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
538 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs | |
539 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
540 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
541 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
542 | * GPIO0[28-29] - UART1 data signal input/output | |
543 | * GPIO0[30] - EMAC0 input | |
544 | * GPIO0[31] - EMAC1 reject packet as output | |
545 | */ | |
6d0f6bcf JCPV |
546 | #define CONFIG_SYS_GPIO0_OSRH 0x40000550 |
547 | #define CONFIG_SYS_GPIO0_OSRL 0x00000110 | |
548 | #define CONFIG_SYS_GPIO0_ISR1H 0x00000000 | |
549 | /*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/ | |
550 | #define CONFIG_SYS_GPIO0_ISR1L 0x15555444 | |
551 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 | |
552 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 | |
553 | #define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 | |
10767ccb WD |
554 | |
555 | /* | |
556 | * Internal Definitions | |
557 | * | |
558 | * Boot Flags | |
559 | */ | |
560 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
561 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
562 | ||
563 | ||
564 | #define CONFIG_NO_SERIAL_EEPROM | |
565 | ||
566 | /*--------------------------------------------------------------------*/ | |
567 | ||
568 | #ifdef CONFIG_NO_SERIAL_EEPROM | |
569 | ||
570 | /* | |
571 | !----------------------------------------------------------------------- | |
572 | ! Defines for entry options. | |
573 | ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that | |
574 | ! are plugged in the board will be utilized as non-ECC DIMMs. | |
575 | !----------------------------------------------------------------------- | |
576 | */ | |
577 | #undef AUTO_MEMORY_CONFIG | |
578 | #define DIMM_READ_ADDR 0xAB | |
579 | #define DIMM_WRITE_ADDR 0xAA | |
580 | ||
10767ccb WD |
581 | #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ |
582 | #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ | |
583 | #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ | |
584 | #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ | |
585 | #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ | |
586 | #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ | |
587 | #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ | |
588 | #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ | |
589 | #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ | |
590 | #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ | |
591 | ||
592 | /* Defines for CPC0_PLLMR1 Register fields */ | |
593 | #define PLL_ACTIVE 0x80000000 | |
594 | #define CPC0_PLLMR1_SSCS 0x80000000 | |
595 | #define PLL_RESET 0x40000000 | |
596 | #define CPC0_PLLMR1_PLLR 0x40000000 | |
597 | /* Feedback multiplier */ | |
598 | #define PLL_FBKDIV 0x00F00000 | |
599 | #define CPC0_PLLMR1_FBDV 0x00F00000 | |
600 | #define PLL_FBKDIV_16 0x00000000 | |
601 | #define PLL_FBKDIV_1 0x00100000 | |
602 | #define PLL_FBKDIV_2 0x00200000 | |
603 | #define PLL_FBKDIV_3 0x00300000 | |
604 | #define PLL_FBKDIV_4 0x00400000 | |
605 | #define PLL_FBKDIV_5 0x00500000 | |
606 | #define PLL_FBKDIV_6 0x00600000 | |
607 | #define PLL_FBKDIV_7 0x00700000 | |
608 | #define PLL_FBKDIV_8 0x00800000 | |
609 | #define PLL_FBKDIV_9 0x00900000 | |
610 | #define PLL_FBKDIV_10 0x00A00000 | |
611 | #define PLL_FBKDIV_11 0x00B00000 | |
612 | #define PLL_FBKDIV_12 0x00C00000 | |
613 | #define PLL_FBKDIV_13 0x00D00000 | |
614 | #define PLL_FBKDIV_14 0x00E00000 | |
615 | #define PLL_FBKDIV_15 0x00F00000 | |
616 | /* Forward A divisor */ | |
617 | #define PLL_FWDDIVA 0x00070000 | |
618 | #define CPC0_PLLMR1_FWDVA 0x00070000 | |
619 | #define PLL_FWDDIVA_8 0x00000000 | |
620 | #define PLL_FWDDIVA_7 0x00010000 | |
621 | #define PLL_FWDDIVA_6 0x00020000 | |
622 | #define PLL_FWDDIVA_5 0x00030000 | |
623 | #define PLL_FWDDIVA_4 0x00040000 | |
624 | #define PLL_FWDDIVA_3 0x00050000 | |
625 | #define PLL_FWDDIVA_2 0x00060000 | |
626 | #define PLL_FWDDIVA_1 0x00070000 | |
627 | /* Forward B divisor */ | |
628 | #define PLL_FWDDIVB 0x00007000 | |
629 | #define CPC0_PLLMR1_FWDVB 0x00007000 | |
630 | #define PLL_FWDDIVB_8 0x00000000 | |
631 | #define PLL_FWDDIVB_7 0x00001000 | |
632 | #define PLL_FWDDIVB_6 0x00002000 | |
633 | #define PLL_FWDDIVB_5 0x00003000 | |
634 | #define PLL_FWDDIVB_4 0x00004000 | |
635 | #define PLL_FWDDIVB_3 0x00005000 | |
636 | #define PLL_FWDDIVB_2 0x00006000 | |
637 | #define PLL_FWDDIVB_1 0x00007000 | |
638 | /* PLL tune bits */ | |
639 | #define PLL_TUNE_MASK 0x000003FF | |
640 | #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ | |
641 | #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ | |
642 | #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ | |
643 | #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ | |
644 | #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ | |
645 | #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ | |
646 | #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ | |
647 | ||
648 | /* Defines for CPC0_PLLMR0 Register fields */ | |
649 | /* CPU divisor */ | |
650 | #define PLL_CPUDIV 0x00300000 | |
651 | #define CPC0_PLLMR0_CCDV 0x00300000 | |
652 | #define PLL_CPUDIV_1 0x00000000 | |
653 | #define PLL_CPUDIV_2 0x00100000 | |
654 | #define PLL_CPUDIV_3 0x00200000 | |
655 | #define PLL_CPUDIV_4 0x00300000 | |
656 | /* PLB divisor */ | |
657 | #define PLL_PLBDIV 0x00030000 | |
658 | #define CPC0_PLLMR0_CBDV 0x00030000 | |
659 | #define PLL_PLBDIV_1 0x00000000 | |
660 | #define PLL_PLBDIV_2 0x00010000 | |
661 | #define PLL_PLBDIV_3 0x00020000 | |
662 | #define PLL_PLBDIV_4 0x00030000 | |
663 | /* OPB divisor */ | |
664 | #define PLL_OPBDIV 0x00003000 | |
665 | #define CPC0_PLLMR0_OPDV 0x00003000 | |
666 | #define PLL_OPBDIV_1 0x00000000 | |
667 | #define PLL_OPBDIV_2 0x00001000 | |
668 | #define PLL_OPBDIV_3 0x00002000 | |
669 | #define PLL_OPBDIV_4 0x00003000 | |
670 | /* EBC divisor */ | |
671 | #define PLL_EXTBUSDIV 0x00000300 | |
672 | #define CPC0_PLLMR0_EPDV 0x00000300 | |
673 | #define PLL_EXTBUSDIV_2 0x00000000 | |
674 | #define PLL_EXTBUSDIV_3 0x00000100 | |
675 | #define PLL_EXTBUSDIV_4 0x00000200 | |
676 | #define PLL_EXTBUSDIV_5 0x00000300 | |
677 | /* MAL divisor */ | |
678 | #define PLL_MALDIV 0x00000030 | |
679 | #define CPC0_PLLMR0_MPDV 0x00000030 | |
680 | #define PLL_MALDIV_1 0x00000000 | |
681 | #define PLL_MALDIV_2 0x00000010 | |
682 | #define PLL_MALDIV_3 0x00000020 | |
683 | #define PLL_MALDIV_4 0x00000030 | |
684 | /* PCI divisor */ | |
685 | #define PLL_PCIDIV 0x00000003 | |
686 | #define CPC0_PLLMR0_PPFD 0x00000003 | |
687 | #define PLL_PCIDIV_1 0x00000000 | |
688 | #define PLL_PCIDIV_2 0x00000001 | |
689 | #define PLL_PCIDIV_3 0x00000002 | |
690 | #define PLL_PCIDIV_4 0x00000003 | |
691 | ||
1d6f9720 WD |
692 | #ifdef CONFIG_PPCHAMELEON_CLK_25 |
693 | /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ | |
694 | #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ | |
695 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ | |
696 | PLL_MALDIV_1 | PLL_PCIDIV_4) | |
697 | #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ | |
698 | PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \ | |
699 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
700 | ||
701 | #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ | |
702 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ | |
703 | PLL_MALDIV_1 | PLL_PCIDIV_4) | |
704 | #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ | |
705 | PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ | |
706 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
707 | ||
708 | #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ | |
709 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ | |
710 | PLL_MALDIV_1 | PLL_PCIDIV_4) | |
711 | #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ | |
712 | PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ | |
713 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
714 | ||
715 | #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ | |
716 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ | |
717 | PLL_MALDIV_1 | PLL_PCIDIV_2) | |
718 | #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ | |
719 | PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ | |
720 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) | |
721 | ||
722 | #elif (defined (CONFIG_PPCHAMELEON_CLK_33)) | |
723 | ||
10767ccb | 724 | /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ |
1d6f9720 WD |
725 | #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ |
726 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ | |
10767ccb | 727 | PLL_MALDIV_1 | PLL_PCIDIV_4) |
1d6f9720 WD |
728 | #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ |
729 | PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ | |
10767ccb | 730 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
1d6f9720 WD |
731 | |
732 | #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ | |
733 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ | |
10767ccb | 734 | PLL_MALDIV_1 | PLL_PCIDIV_4) |
1d6f9720 WD |
735 | #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ |
736 | PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ | |
10767ccb | 737 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
1d6f9720 WD |
738 | |
739 | #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ | |
740 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ | |
10767ccb | 741 | PLL_MALDIV_1 | PLL_PCIDIV_4) |
1d6f9720 WD |
742 | #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ |
743 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ | |
10767ccb | 744 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
1d6f9720 WD |
745 | |
746 | #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ | |
747 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ | |
10767ccb | 748 | PLL_MALDIV_1 | PLL_PCIDIV_2) |
1d6f9720 WD |
749 | #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ |
750 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ | |
10767ccb WD |
751 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) |
752 | ||
1d6f9720 WD |
753 | #else |
754 | #error "* External frequency (SysClk) not defined! *" | |
755 | #endif | |
756 | ||
10767ccb WD |
757 | #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) |
758 | /* Model HI */ | |
1d6f9720 WD |
759 | #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 |
760 | #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 | |
6d0f6bcf | 761 | #define CONFIG_SYS_OPB_FREQ 55555555 |
10767ccb WD |
762 | /* Model ME */ |
763 | #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) | |
1d6f9720 WD |
764 | #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 |
765 | #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 | |
6d0f6bcf | 766 | #define CONFIG_SYS_OPB_FREQ 66666666 |
10767ccb WD |
767 | #else |
768 | /* Model BA (default) */ | |
1d6f9720 WD |
769 | #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 |
770 | #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 | |
6d0f6bcf | 771 | #define CONFIG_SYS_OPB_FREQ 66666666 |
10767ccb WD |
772 | #endif |
773 | ||
774 | #endif /* CONFIG_NO_SERIAL_EEPROM */ | |
775 | ||
776 | #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ | |
10767ccb WD |
777 | #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ |
778 | ||
700a0c64 WD |
779 | /* |
780 | * JFFS2 partitions | |
781 | * | |
782 | */ | |
783 | /* No command line, one static partition */ | |
68d7d651 | 784 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
785 | #define CONFIG_JFFS2_DEV "nand" |
786 | #define CONFIG_JFFS2_PART_SIZE 0x00200000 | |
787 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
788 | ||
789 | /* mtdparts command line support | |
790 | * | |
791 | * Note: fake mtd_id used, no linux mtd map file | |
792 | */ | |
793 | /* | |
68d7d651 | 794 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
795 | #define MTDIDS_DEFAULT "nand0=catcenter" |
796 | #define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)" | |
797 | */ | |
798 | ||
10767ccb | 799 | #endif /* __CONFIG_H */ |