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c609719b | 1 | /* |
414eec35 | 2 | * (C) Copyright 2001-2005 |
c609719b WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * configuration options, board specific, for Siemens Card Controller Module | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | #undef CCM_80MHz /* define for 80 MHz CPU only */ | |
32 | ||
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | ||
38 | #define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */ | |
39 | #define CONFIG_CCM 1 /* on a Card Controller Module */ | |
40 | ||
41 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
42 | #undef CONFIG_8xx_CONS_SMC2 | |
43 | #undef CONFIG_8xx_CONS_NONE | |
44 | ||
45 | /* ENVIRONMENT */ | |
46 | ||
47 | #define CONFIG_BAUDRATE 19200 /* console baudrate in bps */ | |
48 | #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ | |
c609719b WD |
49 | |
50 | #define CONFIG_IPADDR 192.168.0.42 | |
51 | #define CONFIG_NETMASK 255.255.255.0 | |
52 | #define CONFIG_GATEWAYIP 0.0.0.0 | |
53 | #define CONFIG_SERVERIP 192.168.0.254 | |
54 | ||
55 | #define CONFIG_HOSTNAME CCM | |
56 | ||
57 | #define CONFIG_LOADADDR 40180000 | |
58 | ||
59 | #undef CONFIG_BOOTARGS | |
60 | ||
61 | #define CONFIG_BOOTCOMMAND "setenv bootargs " \ | |
fe126d8b WD |
62 | "mem=${mem} " \ |
63 | "root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ | |
8bde7f77 WD |
64 | "wt_8xx=timeout:3600; " \ |
65 | "bootm" | |
c609719b WD |
66 | |
67 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
68 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
69 | ||
70 | #define CONFIG_WATCHDOG 1 /* watchdog enabled */ | |
71 | ||
72 | #undef CONFIG_STATUS_LED /* Status LED disabled */ | |
73 | ||
74 | #define CONFIG_PRAM 512 /* reserve 512kB "protected RAM"*/ | |
75 | ||
76 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
77 | ||
78 | #define CONFIG_SPI /* enable SPI driver */ | |
79 | #define CONFIG_SPI_X /* 16 bit EEPROM addressing */ | |
80 | ||
81 | /* ---------------------------------------------------------------- | |
82 | * Offset to initial SPI buffers in DPRAM (used if the environment | |
83 | * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to | |
84 | * use at an early stage. It is used between the two initialization | |
85 | * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it | |
86 | * far enough from the start of the data area (as well as from the | |
87 | * stack pointer). | |
88 | * ---------------------------------------------------------------- */ | |
89 | #define CFG_SPI_INIT_OFFSET 0xB00 | |
90 | ||
91 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-byte page size */ | |
92 | ||
93 | ||
94 | #define CONFIG_MAC_PARTITION /* nod used yet */ | |
95 | #define CONFIG_DOS_PARTITION | |
96 | ||
5d2ebe1b JL |
97 | /* |
98 | * BOOTP options | |
99 | */ | |
100 | #define CONFIG_BOOTP_SUBNETMASK | |
101 | #define CONFIG_BOOTP_GATEWAY | |
102 | #define CONFIG_BOOTP_HOSTNAME | |
103 | #define CONFIG_BOOTP_BOOTPATH | |
104 | #define CONFIG_BOOTP_BOOTFILESIZE | |
c609719b | 105 | |
c609719b | 106 | |
49cf7e8e JL |
107 | /* |
108 | * Command line configuration. | |
109 | */ | |
110 | #include <config_cmd_default.h> | |
111 | ||
112 | #define CONFIG_CMD_BSP | |
113 | #define CONFIG_CMD_DHCP | |
114 | #define CONFIG_CMD_DATE | |
115 | #define CONFIG_CMD_EEPROM | |
116 | #define CONFIG_CMD_NFS | |
117 | #define CONFIG_CMD_SNTP | |
c609719b | 118 | |
c609719b WD |
119 | |
120 | /* | |
121 | * Miscellaneous configurable options | |
122 | */ | |
123 | #define CFG_LONGHELP /* undef to save memory */ | |
124 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
49cf7e8e | 125 | #if defined(CONFIG_CMD_KGDB) |
c609719b WD |
126 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
127 | #else | |
128 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
129 | #endif | |
130 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
131 | #define CFG_MAXARGS 16 /* max number of command args */ | |
132 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
133 | ||
134 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
135 | #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ | |
136 | ||
137 | #define CFG_LOAD_ADDR 0x00100000 /* default load address */ | |
138 | ||
139 | /* Ethernet hardware configuration done using port pins */ | |
53677ef1 | 140 | #define CFG_PA_ETH_RESET 0x0200 /* PA 6 */ |
c609719b WD |
141 | #define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */ |
142 | #define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ | |
143 | #define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */ | |
144 | #define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */ | |
145 | #define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */ | |
146 | ||
147 | /* Ethernet settings: | |
148 | * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex | |
149 | */ | |
150 | #define CFG_ETH_MDDIS_VALUE 0 | |
151 | #define CFG_ETH_CFG1_VALUE 1 | |
152 | #define CFG_ETH_CFG2_VALUE 1 | |
153 | #define CFG_ETH_CFG3_VALUE 1 | |
154 | ||
155 | /* PUMA configuration */ | |
156 | #define CFG_PC_PUMA_PROG 0x0200 /* PC 6 */ | |
157 | #define CFG_PC_PUMA_DONE 0x0008 /* PC 12 */ | |
158 | #define CFG_PC_PUMA_INIT 0x0004 /* PC 13 */ | |
159 | ||
160 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
161 | ||
162 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
163 | ||
164 | /* | |
165 | * Low Level Configuration Settings | |
166 | * (address mappings, register initial values, etc.) | |
167 | * You should know what you are doing if you make changes here. | |
168 | */ | |
169 | /*----------------------------------------------------------------------- | |
170 | * Internal Memory Mapped Register | |
171 | */ | |
172 | #define CFG_IMMR 0xF0000000 | |
173 | ||
174 | /*----------------------------------------------------------------------- | |
175 | * Definitions for initial stack pointer and data area (in DPRAM) | |
176 | */ | |
177 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
178 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
179 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
180 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
181 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
182 | ||
183 | /*----------------------------------------------------------------------- | |
184 | * Address accessed to reset the board - must not be mapped/assigned | |
185 | */ | |
186 | #define CFG_RESET_ADDRESS 0xFEFFFFFF | |
187 | ||
188 | /*----------------------------------------------------------------------- | |
189 | * Start addresses for the final memory configuration | |
190 | * (Set up by the startup code) | |
191 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
192 | */ | |
193 | #define CFG_SDRAM_BASE 0x00000000 | |
194 | #define CFG_FLASH_BASE 0x40000000 | |
195 | #if defined(DEBUG) | |
196 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
197 | #else | |
198 | #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ | |
199 | #endif | |
200 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
201 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
202 | ||
203 | /* | |
204 | * For booting Linux, the board info and command line data | |
205 | * have to be in the first 8 MB of memory, since this is | |
206 | * the maximum mapped by the Linux kernel during initialization. | |
207 | */ | |
208 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
209 | ||
210 | /*----------------------------------------------------------------------- | |
211 | * FLASH organization | |
212 | */ | |
213 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
214 | #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ | |
215 | ||
216 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
217 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
218 | ||
219 | #if 1 | |
220 | /* Start port with environment in flash; switch to SPI EEPROM later */ | |
5a1aceb0 | 221 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
222 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
223 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
6aff3115 WD |
224 | |
225 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
226 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
227 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
c609719b WD |
228 | #else |
229 | /* Final version: environment in EEPROM */ | |
bb1f8b4f | 230 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
0e8d1586 JCPV |
231 | #define CONFIG_ENV_OFFSET 2048 |
232 | #define CONFIG_ENV_SIZE 2048 | |
c609719b WD |
233 | #endif |
234 | ||
235 | /*----------------------------------------------------------------------- | |
236 | * Hardware Information Block | |
237 | */ | |
238 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
239 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
240 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
241 | ||
242 | /*----------------------------------------------------------------------- | |
243 | * Cache Configuration | |
244 | */ | |
245 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
246 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
247 | ||
248 | /*----------------------------------------------------------------------- | |
249 | * SYPCR - System Protection Control 11-9 | |
250 | * SYPCR can only be written once after reset! | |
251 | *----------------------------------------------------------------------- | |
252 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
253 | */ | |
254 | #if defined(CONFIG_WATCHDOG) | |
255 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
256 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
257 | #else | |
6aff3115 WD |
258 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
259 | SYPCR_SWP) | |
c609719b WD |
260 | #endif |
261 | ||
262 | /*----------------------------------------------------------------------- | |
263 | * SIUMCR - SIU Module Configuration 11-6 | |
264 | *----------------------------------------------------------------------- | |
265 | * we must activate GPL5 in the SIUMCR for CAN | |
266 | */ | |
267 | #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
268 | ||
269 | /*----------------------------------------------------------------------- | |
270 | * TBSCR - Time Base Status and Control 11-26 | |
271 | *----------------------------------------------------------------------- | |
272 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
273 | */ | |
274 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
275 | ||
276 | /*----------------------------------------------------------------------- | |
277 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
278 | *----------------------------------------------------------------------- | |
279 | */ | |
280 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
281 | ||
282 | /*----------------------------------------------------------------------- | |
283 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
284 | *----------------------------------------------------------------------- | |
285 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
286 | */ | |
287 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
288 | ||
289 | /*----------------------------------------------------------------------- | |
290 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
291 | *----------------------------------------------------------------------- | |
292 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
293 | * interrupt status bit | |
294 | * | |
295 | * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! | |
296 | */ | |
297 | #ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ | |
298 | #define CFG_PLPRCR \ | |
299 | ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) | |
300 | #else /* up to 50 MHz we use a 1:1 clock */ | |
301 | #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) | |
302 | #endif /* CCM_80MHz */ | |
303 | ||
304 | /*----------------------------------------------------------------------- | |
305 | * SCCR - System Clock and reset Control Register 15-27 | |
306 | *----------------------------------------------------------------------- | |
307 | * Set clock output, timebase and RTC source and divider, | |
308 | * power management and some other internal clocks | |
309 | */ | |
310 | #define SCCR_MASK SCCR_EBDF11 | |
311 | #ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ | |
312 | #define CFG_SCCR (/* SCCR_TBS | */ \ | |
313 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
314 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
315 | SCCR_DFALCD00) | |
316 | #else /* up to 50 MHz we use a 1:1 clock */ | |
317 | #define CFG_SCCR (SCCR_TBS | \ | |
318 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
319 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
320 | SCCR_DFALCD00) | |
321 | #endif /* CCM_80MHz */ | |
322 | ||
323 | /*----------------------------------------------------------------------- | |
324 | * | |
325 | * Interrupt Levels | |
326 | *----------------------------------------------------------------------- | |
327 | */ | |
328 | #define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ | |
329 | ||
330 | /*----------------------------------------------------------------------- | |
331 | * | |
332 | *----------------------------------------------------------------------- | |
333 | * | |
334 | */ | |
335 | #define CFG_DER 0 | |
336 | ||
337 | /* | |
338 | * Init Memory Controller: | |
339 | * | |
340 | * BR0/1 and OR0/1 (FLASH) | |
341 | */ | |
342 | ||
343 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
344 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
345 | ||
346 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
347 | * restrict access enough to keep SRAM working (if any) | |
348 | * but not too much to meddle with FLASH accesses | |
349 | */ | |
350 | #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
351 | #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
352 | ||
353 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
354 | #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ | |
355 | OR_SCY_5_CLK | OR_EHTR) | |
356 | ||
357 | #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) | |
358 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) | |
359 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
360 | ||
361 | #define CFG_OR1_REMAP CFG_OR0_REMAP | |
362 | #define CFG_OR1_PRELIM CFG_OR0_PRELIM | |
363 | #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
364 | ||
365 | /* | |
366 | * BR2 and OR2 (SDRAM) | |
367 | * | |
368 | */ | |
369 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
370 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
371 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
372 | ||
373 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
374 | #define CFG_OR_TIMING_SDRAM 0x00000A00 | |
375 | ||
376 | #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) | |
377 | #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
378 | ||
379 | /* | |
380 | * BR3 and OR3 (CAN Controller) | |
381 | */ | |
382 | #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ | |
383 | #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
384 | #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) | |
385 | #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ | |
386 | BR_PS_8 | BR_MS_UPMB | BR_V ) | |
387 | ||
388 | /* | |
389 | * BR4/OR4: PUMA Config | |
390 | * | |
391 | * Memory controller will be used in 2 modes: | |
392 | * | |
393 | * - "read" mode: | |
394 | * BR4: 0x10100801 OR4: 0xffff8520 | |
395 | * - "load" mode (chip select on UPM B): | |
396 | * BR4: 0x101004c1 OR4: 0xffff8600 | |
397 | * | |
398 | * Default initialization is in "read" mode | |
399 | */ | |
400 | #define PUMA_CONF_BASE 0x10100000 /* PUMA Config */ | |
401 | #define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */ | |
402 | #define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_2_CLK) | |
403 | #define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_2_CLK) | |
404 | ||
405 | #define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \ | |
406 | BR_PS_8 | BR_MS_UPMB | BR_V) | |
407 | #define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING) | |
408 | ||
409 | #define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) | |
410 | #define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING) | |
411 | ||
412 | #define CFG_BR4_PRELIM PUMA_CONF_BR_READ | |
413 | #define CFG_OR4_PRELIM PUMA_CONF_OR_READ | |
414 | ||
415 | /* | |
416 | * BR5/OR5: PUMA: SMA Bus 8 Bit | |
417 | * BR5: 0x10200401 OR5: 0xffe0010a | |
418 | */ | |
419 | #define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */ | |
420 | #define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */ | |
421 | #define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) | |
422 | ||
423 | #define CFG_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) | |
424 | #define CFG_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) | |
425 | ||
426 | /* | |
427 | * BR6/OR6: PUMA: SMA Bus 16 Bit | |
428 | * BR6: 0x10600801 OR6: 0xffe0010a | |
429 | */ | |
430 | #define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */ | |
431 | #define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */ | |
432 | #define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) | |
433 | ||
434 | #define CFG_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) | |
435 | #define CFG_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) | |
436 | ||
437 | /* | |
438 | * BR7/OR7: PUMA: external Flash | |
439 | * BR7: 0x10a00801 OR7: 0xfe00010a | |
440 | */ | |
441 | #define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */ | |
442 | #define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */ | |
443 | #define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) | |
444 | ||
445 | #define CFG_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) | |
446 | #define CFG_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA) | |
447 | ||
448 | ||
449 | /* | |
450 | * Memory Periodic Timer Prescaler | |
451 | */ | |
452 | ||
453 | /* periodic timer for refresh */ | |
454 | #define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ | |
455 | ||
456 | /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ | |
457 | #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ | |
458 | #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
459 | ||
460 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
461 | #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ | |
462 | #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
463 | ||
464 | /* | |
465 | * MAMR settings for SDRAM | |
466 | */ | |
467 | ||
468 | /* 8 column SDRAM */ | |
469 | #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
470 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
471 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
472 | /* 9 column SDRAM */ | |
473 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
474 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
475 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
476 | ||
477 | ||
478 | /* | |
479 | * Internal Definitions | |
480 | * | |
481 | * Boot Flags | |
482 | */ | |
483 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
484 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
485 | ||
486 | #endif /* __CONFIG_H */ |