[people/ms/u-boot.git] / include / configs / CMS700.h

/*
 * (C) Copyright 2005
 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * CMS700.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_VOM405		1	/* ...on a VOM405 board		*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC8000

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#undef  CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#undef  CONFIG_HAS_ETH1

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_BSP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DATE
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM


#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

#undef  CONFIG_PRAM			/* no "protected RAM"           */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/

#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD	    691200

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * RTC stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR	0x68

/*-----------------------------------------------------------------------
 * NAND-FLASH stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
#define NAND_BIG_DELAY_US	25

#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */

#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
#define CONFIG_SYS_NAND_QUIET          1

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)

#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
# define CONFIG_SYS_RAMBOOT		1
#else
# undef CONFIG_SYS_RAMBOOT
#endif

/*-----------------------------------------------------------------------
 * Environment Variable setup
 */
#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
				   /* total size of a CAT24WC16 is 2048 bytes */

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

#define CONFIG_SYS_EEPROM_WREN         1

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */
#define CONFIG_SYS_PLD_BASE            0xf0000000
#define CONFIG_SYS_NAND_BASE	        0xF4000000  /* NAND FLASH Base Address		*/

/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
#define CONFIG_SYS_EBC_PB0AP		0x92015480
#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
#define CONFIG_SYS_EBC_PB1AP		0x92015480
#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/*-----------------------------------------------------------------------
 * FPGA stuff
 */
#define CONFIG_SYS_XSVF_DEFAULT_ADDR	0xfffc0000

/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
#define CONFIG_SYS_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
#define CONFIG_SYS_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
#define CONFIG_SYS_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
#define CONFIG_SYS_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM	  1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/

#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup (PPC405EP specific)
 *
 * GPIO0[0]	- External Bus Controller BLAST output
 * GPIO0[1-9]	- Instruction trace outputs -> GPIO
 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 * GPIO0[24-27] - UART0 control signal inputs/outputs
 * GPIO0[28-29] - UART1 data signal input/output
 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 */
/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
#define CONFIG_SYS_GPIO0_OSRL		0x40000500  /*	0 ... 15 */
#define CONFIG_SYS_GPIO0_OSRH		0x00000110  /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_ISR1L		0x00000000  /*	0 ... 15 */
#define CONFIG_SYS_GPIO0_ISR1H		0x14000045  /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TSRL		0x00000000  /*	0 ... 15 */
#define CONFIG_SYS_GPIO0_TSRH		0x00000000  /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */

#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 8)    /* GPIO8 */
#define CONFIG_SYS_PLD_RESET		(0x80000000 >> 12)   /* GPIO12 */

/*
 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 * This value will be set if iic boot eprom is disabled.
 */
#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33

#endif	/* __CONFIG_H */
Commit	Line	Data
feaedfcf SR	1	/*
	2	* (C) Copyright 2005
	3	* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
feaedfcf SR	6	*/
	7
	8	/*
	9	* CMS700.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_405EP 1 /* This is a PPC405 CPU */
	21	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	22	#define CONFIG_VOM405 1 /* ...on a VOM405 board */
	23
2ae18241 WD	24	#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
2ae18241 WD	25
feaedfcf SR	26	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
	27	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
	28
	29	#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
	30
	31	#define CONFIG_BAUDRATE 9600
	32	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	33
	34	#undef CONFIG_BOOTARGS
	35	#undef CONFIG_BOOTCOMMAND
	36
	37	#define CONFIG_PREBOOT /* enable preboot variable */
	38
6d0f6bcf	39	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
feaedfcf	40
96e21f86	41	#define CONFIG_PPC4xx_EMAC
feaedfcf SR	42	#undef CONFIG_HAS_ETH1
	43
	44	#define CONFIG_MII 1 /* MII PHY management */
	45	#define CONFIG_PHY_ADDR 0 /* PHY address */
	46	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
	47	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
	48
5d2ebe1b JL	49	/*
	50	* BOOTP options
	51	*/
	52	#define CONFIG_BOOTP_SUBNETMASK
	53	#define CONFIG_BOOTP_GATEWAY
	54	#define CONFIG_BOOTP_HOSTNAME
	55	#define CONFIG_BOOTP_BOOTPATH
	56	#define CONFIG_BOOTP_DNS
	57	#define CONFIG_BOOTP_DNS2
	58	#define CONFIG_BOOTP_SEND_HOSTNAME
	59
feaedfcf	60
49cf7e8e JL	61	/*
	62	* Command line configuration.
	63	*/
	64	#include <config_cmd_default.h>
	65
	66	#define CONFIG_CMD_DHCP
	67	#define CONFIG_CMD_BSP
49cf7e8e JL	68	#define CONFIG_CMD_ELF
	69	#define CONFIG_CMD_NAND
	70	#define CONFIG_CMD_I2C
	71	#define CONFIG_CMD_DATE
	72	#define CONFIG_CMD_MII
	73	#define CONFIG_CMD_PING
	74	#define CONFIG_CMD_EEPROM
	75
feaedfcf SR	76
	77	#undef CONFIG_WATCHDOG /* watchdog disabled */
	78
	79	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	80
	81	#undef CONFIG_PRAM /* no "protected RAM" */
	82
	83	/*
	84	* Miscellaneous configurable options
	85	*/
6d0f6bcf	86	#define CONFIG_SYS_LONGHELP /* undef to save memory */
feaedfcf	87
6d0f6bcf	88	#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
feaedfcf	89
49cf7e8e	90	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	91	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
feaedfcf	92	#else
6d0f6bcf	93	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
feaedfcf	94	#endif
6d0f6bcf JCPV	95	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	96	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	97	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
feaedfcf	98
6d0f6bcf	99	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
feaedfcf	100
6d0f6bcf	101	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
feaedfcf	102
6d0f6bcf JCPV	103	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	104	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
feaedfcf	105
550650dd SR	106	#define CONFIG_CONS_INDEX 2 /* Use UART1 */
	107	#define CONFIG_SYS_NS16550
	108	#define CONFIG_SYS_NS16550_SERIAL
	109	#define CONFIG_SYS_NS16550_REG_SIZE 1
	110	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	111
6d0f6bcf	112	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf	113	#define CONFIG_SYS_BASE_BAUD 691200
feaedfcf SR	114
feaedfcf SR	115	/* The following table includes the supported baudrates */
6d0f6bcf	116	#define CONFIG_SYS_BAUDRATE_TABLE \
feaedfcf SR	117	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	118	57600, 115200, 230400, 460800, 921600 }
	119
6d0f6bcf JCPV	120	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	121	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
feaedfcf	122
feaedfcf SR	123	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	124
	125	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	126
6d0f6bcf	127	#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
feaedfcf SR	128
	129	/*-----------------------------------------------------------------------
	130	* RTC stuff
	131	*-----------------------------------------------------------------------
	132	*/
	133	#define CONFIG_RTC_DS1337
6d0f6bcf	134	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
feaedfcf SR	135
	136	/*-----------------------------------------------------------------------
	137	* NAND-FLASH stuff
	138	*-----------------------------------------------------------------------
	139	*/
6d0f6bcf	140	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
6d0f6bcf	141	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
bd84ee4c MF	142	#define NAND_BIG_DELAY_US 25
bd84ee4c MF	143
6d0f6bcf JCPV	144	#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
	145	#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
	146	#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
	147	#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
feaedfcf	148
6d0f6bcf JCPV	149	#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
6d0f6bcf JCPV	150	#define CONFIG_SYS_NAND_QUIET 1
feaedfcf	151
feaedfcf SR	152	/*
	153	* For booting Linux, the board info and command line data
	154	* have to be in the first 8 MB of memory, since this is
	155	* the maximum mapped by the Linux kernel during initialization.
	156	*/
6d0f6bcf	157	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
feaedfcf SR	158	/*-----------------------------------------------------------------------
	159	* FLASH organization
	160	*/
	161	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
	162
6d0f6bcf JCPV	163	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	164	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
feaedfcf	165
6d0f6bcf JCPV	166	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	167	#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
feaedfcf	168
6d0f6bcf JCPV	169	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	170	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	171	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
feaedfcf SR	172	/*
	173	* The following defines are added for buggy IOP480 byte interface.
	174	* All other boards should use the standard values (CPCI405 etc.)
	175	*/
6d0f6bcf JCPV	176	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	177	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	178	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
feaedfcf	179
6d0f6bcf	180	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
feaedfcf	181
feaedfcf SR	182	/*-----------------------------------------------------------------------
	183	* Start addresses for the final memory configuration
	184	* (Set up by the startup code)
6d0f6bcf	185	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
feaedfcf	186	*/
6d0f6bcf	187	#define CONFIG_SYS_SDRAM_BASE 0x00000000
7cc635fb	188	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
14d0a02a WD	189	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
14d0a02a WD	190	#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
7cc635fb	191	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
6d0f6bcf JCPV	192
	193	#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
	194	# define CONFIG_SYS_RAMBOOT 1
feaedfcf	195	#else
6d0f6bcf	196	# undef CONFIG_SYS_RAMBOOT
feaedfcf SR	197	#endif
	198
	199	/*-----------------------------------------------------------------------
	200	* Environment Variable setup
	201	*/
bb1f8b4f	202	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	203	#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	204	#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
feaedfcf SR	205	/* total size of a CAT24WC16 is 2048 bytes */
	206
	207	/*-----------------------------------------------------------------------
	208	* I2C EEPROM (CAT24WC16) for environment
	209	*/
880540de DE	210	#define CONFIG_SYS_I2C
	211	#define CONFIG_SYS_I2C_PPC4XX
	212	#define CONFIG_SYS_I2C_PPC4XX_CH0
	213	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
	214	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
feaedfcf	215
6d0f6bcf JCPV	216	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
6d0f6bcf JCPV	217	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
feaedfcf	218	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	219	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	220	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
feaedfcf SR	221	/* 16 byte page write mode using*/
feaedfcf SR	222	/* last 4 bits of the address */
6d0f6bcf	223	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
feaedfcf	224
6d0f6bcf	225	#define CONFIG_SYS_EEPROM_WREN 1
feaedfcf	226
feaedfcf SR	227	/*-----------------------------------------------------------------------
	228	* External Bus Controller (EBC) Setup
	229	*/
6d0f6bcf JCPV	230	#define CONFIG_SYS_PLD_BASE 0xf0000000
6d0f6bcf JCPV	231	#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
feaedfcf SR	232
feaedfcf SR	233	/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
6d0f6bcf JCPV	234	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	235	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
feaedfcf SR	236
feaedfcf SR	237	/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
6d0f6bcf JCPV	238	#define CONFIG_SYS_EBC_PB1AP 0x92015480
6d0f6bcf JCPV	239	#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
feaedfcf SR	240
feaedfcf SR	241	/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
6d0f6bcf JCPV	242	#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	243	#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
feaedfcf SR	244
	245	/*-----------------------------------------------------------------------
	246	* FPGA stuff
	247	*/
7cc635fb	248	#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
feaedfcf SR	249
feaedfcf SR	250	/* FPGA program pin configuration */
6d0f6bcf JCPV	251	#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
	252	#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
	253	#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
	254	#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
	255	#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
feaedfcf SR	256
	257	/*-----------------------------------------------------------------------
	258	* Definitions for initial stack pointer and data area (in data cache)
	259	*/
	260	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
6d0f6bcf	261	#define CONFIG_SYS_TEMP_STACK_OCM 1
feaedfcf SR	262
feaedfcf SR	263	/* On Chip Memory location */
6d0f6bcf JCPV	264	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	265	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	266	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
553f0982	267	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
feaedfcf	268
25ddd1fb	269	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	270	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
feaedfcf SR	271
	272	/*-----------------------------------------------------------------------
	273	* Definitions for GPIO setup (PPC405EP specific)
	274	*
	275	* GPIO0[0] - External Bus Controller BLAST output
	276	* GPIO0[1-9] - Instruction trace outputs -> GPIO
	277	* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
	278	* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
	279	* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
	280	* GPIO0[24-27] - UART0 control signal inputs/outputs
	281	* GPIO0[28-29] - UART1 data signal input/output
	282	* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
	283	*/
	284	/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
	285	/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
	286	/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
	287	/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
afabb498 SR	288	#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
	289	#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
	290	#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
	291	#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
	292	#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
	293	#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
6d0f6bcf JCPV	294	#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
	295
	296	#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
	297	#define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */
feaedfcf	298
feaedfcf SR	299	/*
	300	* Default speed selection (cpu_plb_opb_ebc) in mhz.
	301	* This value will be set if iic boot eprom is disabled.
	302	*/
feaedfcf SR	303	#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
feaedfcf SR	304	#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
feaedfcf SR	305
feaedfcf SR	306	#endif /* __CONFIG_H */