[people/ms/u-boot.git] / include / configs / CPC45.h

/*
 * (C) Copyright 2001-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

/*
 *
 * Configuration settings for the CPC45 board.
 *
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_CPC45		1

#define CONFIG_SYS_TEXT_BASE	0xFFF00000

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#define CONFIG_BOOTDELAY	5

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH

#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/

#if 1
#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
#endif

/* Print Buffer Size
 */
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */

#define CONFIG_SYS_SDRAM_BASE		0x00000000

#if defined(CONFIG_BOOT_ROM)
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#else
#define CONFIG_SYS_FLASH_BASE		0xFF800000
#endif

#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100

#define CONFIG_SYS_EUMB_ADDR		0xFCE00000

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/

/* Maximum amount of RAM.
 */
#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000


#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
#undef CONFIG_SYS_RAMBOOT
#else
#define CONFIG_SYS_RAMBOOT
#endif


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */

#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	1

#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
#define DUART_DCR		(CONFIG_SYS_EUMB_ADDR + 0x4511)

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * RTC configuration
 */
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR	0x51

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ	33000000
#define CONFIG_SYS_HZ			1000


/* Bit-field values for MCCR1.
 */
#define CONFIG_SYS_ROMNAL		0
#define CONFIG_SYS_ROMFAL		8

#define CONFIG_SYS_BANK0_ROW		0	/* SDRAM bank 7-0 row address */
#define CONFIG_SYS_BANK1_ROW		0
#define CONFIG_SYS_BANK2_ROW		0
#define CONFIG_SYS_BANK3_ROW		0
#define CONFIG_SYS_BANK4_ROW		0
#define CONFIG_SYS_BANK5_ROW		0
#define CONFIG_SYS_BANK6_ROW		0
#define CONFIG_SYS_BANK7_ROW		0

/* Bit-field values for MCCR2.
 */

#define CONFIG_SYS_REFINT		0x2ec

/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 */
#define CONFIG_SYS_BSTOPRE		160

/* Bit-field values for MCCR3.
 */
#define CONFIG_SYS_REFREC		2	/* Refresh to activate interval		*/
#define CONFIG_SYS_RDLAT		0	/* Data latancy from read command	*/

/* Bit-field values for MCCR4.
 */
#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* SDMODE CAS latancy			*/
#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length			*/
#define CONFIG_SYS_ACTORW		2
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
#define CONFIG_SYS_EXTROM		0
#define CONFIG_SYS_REGDIMM		0

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CONFIG_SYS_BANK0_START		0x00000000
#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE	1
#define CONFIG_SYS_BANK1_START		0x3ff00000
#define CONFIG_SYS_BANK1_END		0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE	0
#define CONFIG_SYS_BANK2_START		0x3ff00000
#define CONFIG_SYS_BANK2_END		0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE	0
#define CONFIG_SYS_BANK3_START		0x3ff00000
#define CONFIG_SYS_BANK3_END		0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE	0
#define CONFIG_SYS_BANK4_START		0x3ff00000
#define CONFIG_SYS_BANK4_END		0x3fffffff
#define CONFIG_SYS_BANK4_ENABLE	0
#define CONFIG_SYS_BANK5_START		0x3ff00000
#define CONFIG_SYS_BANK5_END		0x3fffffff
#define CONFIG_SYS_BANK5_ENABLE	0
#define CONFIG_SYS_BANK6_START		0x3ff00000
#define CONFIG_SYS_BANK6_END		0x3fffffff
#define CONFIG_SYS_BANK6_ENABLE	0
#define CONFIG_SYS_BANK7_START		0x3ff00000
#define CONFIG_SYS_BANK7_END		0x3fffffff
#define CONFIG_SYS_BANK7_ENABLE	0

#define CONFIG_SYS_ODCR		0xff
#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
#define INTEL_ID_28F160F3T	0x88F388F3	/*  16M = 1M x 16 top boot sector	*/
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

	/* Warining: environment is not EMBEDDED in the ppcboot code.
	 * It's stored in flash separately.
	 */
#define CONFIG_ENV_IS_IN_FLASH	    1

#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x7F8000)
#define CONFIG_ENV_SIZE		0x4000	/* Size of the Environment		*/
#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
#define CONFIG_ENV_SECT_SIZE	0x8000 /* Size of the Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*----------------------------------------------------------------------*/
/* CPC45 Memory Map							*/
/*----------------------------------------------------------------------*/
#define SRAM_BASE	0x80000000	/* SRAM base address		*/
#define SRAM_END	0x801FFFFF
#define ST16552_A_BASE	0x80200000	/* ST16552 channel A		*/
#define ST16552_B_BASE	0x80400000	/* ST16552 channel A		*/
#define BCSR_BASE	0x80600000	/* board control / status registers */
#define DISPLAY_BASE	0x80600040	/* DISPLAY base			*/
#define PCMCIA_MEM_BASE 0x83000000	/* PCMCIA memory window base	*/
#define PCMCIA_IO_BASE	0xFE000000	/* PCMCIA IO window base	*/

#define	CONFIG_SYS_SRAM_BASE	SRAM_BASE
#define	CONFIG_SYS_SRAM_SIZE	(SRAM_END - SRAM_BASE + 1)

/*---------------------------------------------------------------------*/
/* CPC45 Control/Status Registers				       */
/*---------------------------------------------------------------------*/
#define IRQ_ENA_1		*((volatile uchar*)(BCSR_BASE + 0x00))
#define IRQ_STAT_1		*((volatile uchar*)(BCSR_BASE + 0x01))
#define IRQ_ENA_2		*((volatile uchar*)(BCSR_BASE + 0x02))
#define IRQ_STAT_2		*((volatile uchar*)(BCSR_BASE + 0x03))
#define BOARD_CTRL		*((volatile uchar*)(BCSR_BASE + 0x04))
#define BOARD_STAT		*((volatile uchar*)(BCSR_BASE + 0x05))
#define WDG_START		*((volatile uchar*)(BCSR_BASE + 0x06))
#define WDG_PRESTOP		*((volatile uchar*)(BCSR_BASE + 0x06))
#define WDG_STOP		*((volatile uchar*)(BCSR_BASE + 0x06))
#define BOARD_REV		*((volatile uchar*)(BCSR_BASE + 0x07))

/* IRQ_ENA_1 bit definitions */
#define I_ENA_1_IERA	0x80		/* INTA enable			*/
#define I_ENA_1_IERB	0x40		/* INTB enable			*/
#define I_ENA_1_IERC	0x20		/* INTC enable			*/
#define I_ENA_1_IERD	0x10		/* INTD enable			*/

/* IRQ_STAT_1 bit definitions */
#define I_STAT_1_INTA	0x80		/* INTA status			*/
#define I_STAT_1_INTB	0x40		/* INTB status			*/
#define I_STAT_1_INTC	0x20		/* INTC status			*/
#define I_STAT_1_INTD	0x10		/* INTD status			*/

/* IRQ_ENA_2 bit definitions */
#define I_ENA_2_IEAB	0x80		/* ABORT IRQ enable		*/
#define I_ENA_2_IEK1	0x40		/* KEY1 IRQ enable		*/
#define I_ENA_2_IEK2	0x20		/* KEY2 IRQ enable		*/
#define I_ENA_2_IERT	0x10		/* RTC IRQ enable		*/
#define I_ENA_2_IESM	0x08		/* LM81 IRQ enable		*/
#define I_ENA_2_IEDG	0x04		/* DEGENERATING IRQ enable	*/
#define I_ENA_2_IES2	0x02		/* ST16552/B IRQ enable		*/
#define I_ENA_2_IES1	0x01		/* ST16552/A IRQ enable		*/

/* IRQ_STAT_2 bit definitions */
#define I_STAT_2_ABO	0x80		/* ABORT IRQ status		*/
#define I_STAT_2_KY1	0x40		/* KEY1 IRQ status		*/
#define I_STAT_2_KY2	0x20		/* KEY2 IRQ status		*/
#define I_STAT_2_RTC	0x10		/* RTC IRQ status		*/
#define I_STAT_2_SMN	0x08		/* LM81 IRQ status		*/
#define I_STAT_2_DEG	0x04		/* DEGENERATING IRQ status	*/
#define I_STAT_2_SIO2	0x02		/* ST16552/B IRQ status		*/
#define I_STAT_2_SIO1	0x01		/* ST16552/A IRQ status		*/

/* BOARD_CTRL bit definitions */
#define USER_LEDS		2			/* 2 user LEDs	*/

#if (USER_LEDS == 4)
#define B_CTRL_WRSE		0x80
#define B_CTRL_KRSE		0x40
#define B_CTRL_FWRE		0x20		/* Flash write enable		*/
#define B_CTRL_FWPT		0x10		/* Flash write protect		*/
#define B_CTRL_LED3		0x08		/* LED 3 control		*/
#define B_CTRL_LED2		0x04		/* LED 2 control		*/
#define B_CTRL_LED1		0x02		/* LED 1 control		*/
#define B_CTRL_LED0		0x01		/* LED 0 control		*/
#else
#define B_CTRL_WRSE		0x80
#define B_CTRL_KRSE		0x40
#define B_CTRL_FWRE_1		0x20		/* Flash write enable		*/
#define B_CTRL_FWPT_1		0x10		/* Flash write protect		*/
#define B_CTRL_LED1		0x08		/* LED 1 control		*/
#define B_CTRL_LED0		0x04		/* LED 0 control		*/
#define B_CTRL_FWRE_0		0x02		/* Flash write enable		*/
#define B_CTRL_FWPT_0		0x01		/* Flash write protect		*/
#endif

/* BOARD_STAT bit definitions */
#define B_STAT_WDGE		0x80
#define B_STAT_WDGS		0x40
#define B_STAT_WRST		0x20
#define B_STAT_KRST		0x10
#define B_STAT_CSW3		0x08		/* sitch bit 3 status		*/
#define B_STAT_CSW2		0x04		/* sitch bit 2 status		*/
#define B_STAT_CSW1		0x02		/* sitch bit 1 status		*/
#define B_STAT_CSW0		0x01		/* sitch bit 0 status		*/

/*---------------------------------------------------------------------*/
/* Display addresses						       */
/*---------------------------------------------------------------------*/
#define DISP_UDC_RAM	(DISPLAY_BASE + 0x08)	/* UDC RAM	       */
#define DISP_CHR_RAM	(DISPLAY_BASE + 0x18)	/* character Ram       */
#define DISP_FLASH	(DISPLAY_BASE + 0x20)	/* Flash Ram	       */

#define DISP_UDC_ADR	*((volatile uchar*)(DISPLAY_BASE + 0x00))	/* UDC Address Reg.    */
#define DISP_CWORD	*((volatile uchar*)(DISPLAY_BASE + 0x10))	/* Control Word Reg.   */

#define DISP_DIG0	*((volatile uchar*)(DISP_CHR_RAM + 0x00))	/* Digit 0 address     */
#define DISP_DIG1	*((volatile uchar*)(DISP_CHR_RAM + 0x01))	/* Digit 0 address     */
#define DISP_DIG2	*((volatile uchar*)(DISP_CHR_RAM + 0x02))	/* Digit 0 address     */
#define DISP_DIG3	*((volatile uchar*)(DISP_CHR_RAM + 0x03))	/* Digit 0 address     */
#define DISP_DIG4	*((volatile uchar*)(DISP_CHR_RAM + 0x04))	/* Digit 0 address     */
#define DISP_DIG5	*((volatile uchar*)(DISP_CHR_RAM + 0x05))	/* Digit 0 address     */
#define DISP_DIG6	*((volatile uchar*)(DISP_CHR_RAM + 0x06))	/* Digit 0 address     */
#define DISP_DIG7	*((volatile uchar*)(DISP_CHR_RAM + 0x07))	/* Digit 0 address     */


/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI			/* include pci support			*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_SYS_EARLY_PCI_INIT
#undef	CONFIG_PCI_PNP
#undef	CONFIG_PCI_SCAN_SHOW


#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/

#define PCI_ENET0_IOADDR	0x82000000
#define PCI_ENET0_MEMADDR	0x82000000
#define PCI_PLX9030_IOADDR	0x82100000
#define PCI_PLX9030_MEMADDR	0x82100000

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 */

#define CONFIG_I82365

#define CONFIG_SYS_PCMCIA_MEM_ADDR	PCMCIA_MEM_BASE
#define CONFIG_SYS_PCMCIA_MEM_SIZE	0x1000

#define CONFIG_PCMCIA_SLOT_A

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for IDE not supported	*/
#define	CONFIG_IDE_LED			/* LED   for IDE is  supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

#define CONFIG_SYS_ATA_DATA_OFFSET	CONFIG_SYS_PCMCIA_MEM_SIZE

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)

#define CONFIG_DOS_PARTITION

#endif	/* __CONFIG_H */
Commit	Line	Data
3bac3513	1	/*
414eec35	2	* (C) Copyright 2001-2005
3bac3513 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
3bac3513 WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
3bac3513 WD	6	*/
	7
	8	/*
	9	*
	10	* Configuration settings for the CPC45 board.
	11	*
	12	*/
	13
	14	/* ------------------------------------------------------------------------- */
	15
	16	/*
	17	* board/config.h - configuration options, board specific
	18	*/
	19
	20	#ifndef __CONFIG_H
	21	#define __CONFIG_H
	22
	23	/*
	24	* High Level Configuration Options
	25	* (easy to change)
	26	*/
	27
	28	#define CONFIG_MPC824X 1
	29	#define CONFIG_MPC8245 1
	30	#define CONFIG_CPC45 1
	31
2ae18241	32	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
3bac3513 WD	33
	34	#define CONFIG_CONS_INDEX 1
	35	#define CONFIG_BAUDRATE 9600
3bac3513	36
32bf3d14	37	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
3bac3513 WD	38
	39	#define CONFIG_BOOTDELAY 5
	40
5d2ebe1b JL	41	/*
	42	* BOOTP options
	43	*/
	44	#define CONFIG_BOOTP_SUBNETMASK
	45	#define CONFIG_BOOTP_GATEWAY
	46	#define CONFIG_BOOTP_HOSTNAME
	47	#define CONFIG_BOOTP_BOOTPATH
	48
	49	#define CONFIG_BOOTP_BOOTFILESIZE
3bac3513	50
49cf7e8e JL	51
	52	/*
	53	* Command line configuration.
3bac3513	54	*/
49cf7e8e JL	55	#include <config_cmd_default.h>
	56
	57	#define CONFIG_CMD_BEDBUG
	58	#define CONFIG_CMD_DATE
	59	#define CONFIG_CMD_DHCP
	60	#define CONFIG_CMD_EEPROM
	61	#define CONFIG_CMD_EXT2
	62	#define CONFIG_CMD_FAT
	63	#define CONFIG_CMD_FLASH
	64	#define CONFIG_CMD_I2C
	65	#define CONFIG_CMD_IDE
	66	#define CONFIG_CMD_NFS
	67	#define CONFIG_CMD_PCI
	68	#define CONFIG_CMD_PING
	69	#define CONFIG_CMD_SDRAM
	70	#define CONFIG_CMD_SNTP
3bac3513 WD	71
	72
	73	/*
	74	* Miscellaneous configurable options
	75	*/
6d0f6bcf JCPV	76	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	77	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	78	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
3bac3513 WD	79
3bac3513 WD	80	#if 1
6d0f6bcf	81	#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
3bac3513	82	#endif
3bac3513 WD	83
	84	/* Print Buffer Size
	85	*/
6d0f6bcf	86	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
3bac3513	87
6d0f6bcf JCPV	88	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	89	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	90	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
3bac3513 WD	91
	92	/*-----------------------------------------------------------------------
	93	* Start addresses for the final memory configuration
	94	* (Set up by the startup code)
6d0f6bcf	95	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
3bac3513 WD	96	*/
3bac3513 WD	97
6d0f6bcf	98	#define CONFIG_SYS_SDRAM_BASE 0x00000000
3bac3513 WD	99
3bac3513 WD	100	#if defined(CONFIG_BOOT_ROM)
6d0f6bcf	101	#define CONFIG_SYS_FLASH_BASE 0xFF000000
3bac3513	102	#else
6d0f6bcf	103	#define CONFIG_SYS_FLASH_BASE 0xFF800000
3bac3513 WD	104	#endif
3bac3513 WD	105
6d0f6bcf	106	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
3bac3513	107
6d0f6bcf	108	#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
3bac3513	109
14d0a02a	110	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
3bac3513	111
6d0f6bcf JCPV	112	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6d0f6bcf JCPV	113	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
3bac3513	114
6d0f6bcf JCPV	115	#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
6d0f6bcf JCPV	116	#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
3bac3513	117
49822e23 WD	118	/* Maximum amount of RAM.
49822e23 WD	119	*/
6d0f6bcf	120	#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
3bac3513 WD	121
3bac3513 WD	122
6d0f6bcf JCPV	123	#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	124	#undef CONFIG_SYS_RAMBOOT
3bac3513	125	#else
6d0f6bcf	126	#define CONFIG_SYS_RAMBOOT
3bac3513 WD	127	#endif
	128
	129
	130	/*-----------------------------------------------------------------------
	131	* Definitions for initial stack pointer and data area
	132	*/
	133
6d0f6bcf	134	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982	135	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	136	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
3bac3513 WD	137
	138	/*
	139	* NS16550 Configuration
	140	*/
6d0f6bcf JCPV	141	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	142	#define CONFIG_SYS_NS16550_SERIAL
3bac3513	143
6d0f6bcf	144	#define CONFIG_SYS_NS16550_REG_SIZE 1
3bac3513	145
6d0f6bcf	146	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
3bac3513	147
6d0f6bcf JCPV	148	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
	149	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
	150	#define DUART_DCR (CONFIG_SYS_EUMB_ADDR + 0x4511)
49822e23 WD	151
	152	/*
	153	* I2C configuration
	154	*/
	155	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	156
6d0f6bcf JCPV	157	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	158	#define CONFIG_SYS_I2C_SLAVE 0x7F
49822e23 WD	159
	160	/*
	161	* RTC configuration
	162	*/
	163	#define CONFIG_RTC_PCF8563
6d0f6bcf	164	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
49822e23 WD	165
	166	/*
	167	* EEPROM configuration
	168	*/
6d0f6bcf JCPV	169	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
	170	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	171	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	172	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
	173	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
3bac3513 WD	174
	175	/*
	176	* Low Level Configuration Settings
	177	* (address mappings, register initial values, etc.)
	178	* You should know what you are doing if you make changes here.
	179	* For the detail description refer to the MPC8240 user's manual.
	180	*/
	181
49822e23	182	#define CONFIG_SYS_CLK_FREQ 33000000
6d0f6bcf	183	#define CONFIG_SYS_HZ 1000
53cf9435	184
3bac3513	185
49822e23 WD	186	/* Bit-field values for MCCR1.
49822e23 WD	187	*/
6d0f6bcf JCPV	188	#define CONFIG_SYS_ROMNAL 0
	189	#define CONFIG_SYS_ROMFAL 8
	190
	191	#define CONFIG_SYS_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
	192	#define CONFIG_SYS_BANK1_ROW 0
	193	#define CONFIG_SYS_BANK2_ROW 0
	194	#define CONFIG_SYS_BANK3_ROW 0
	195	#define CONFIG_SYS_BANK4_ROW 0
	196	#define CONFIG_SYS_BANK5_ROW 0
	197	#define CONFIG_SYS_BANK6_ROW 0
	198	#define CONFIG_SYS_BANK7_ROW 0
49822e23 WD	199
	200	/* Bit-field values for MCCR2.
	201	*/
3bac3513	202
6d0f6bcf	203	#define CONFIG_SYS_REFINT 0x2ec
3bac3513	204
49822e23 WD	205	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
49822e23 WD	206	*/
6d0f6bcf	207	#define CONFIG_SYS_BSTOPRE 160
3bac3513	208
49822e23 WD	209	/* Bit-field values for MCCR3.
49822e23 WD	210	*/
6d0f6bcf JCPV	211	#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
6d0f6bcf JCPV	212	#define CONFIG_SYS_RDLAT 0 /* Data latancy from read command */
3bac3513	213
49822e23 WD	214	/* Bit-field values for MCCR4.
49822e23 WD	215	*/
6d0f6bcf JCPV	216	#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
	217	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
	218	#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
	219	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
	220	#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
	221	#define CONFIG_SYS_ACTORW 2
	222	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
	223	#define CONFIG_SYS_EXTROM 0
	224	#define CONFIG_SYS_REGDIMM 0
3bac3513 WD	225
	226	/* Memory bank settings.
	227	* Only bits 20-29 are actually used from these vales to set the
	228	* start/end addresses. The upper two bits will always be 0, and the lower
	229	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
	230	* address. Refer to the MPC8240 book.
	231	*/
	232
6d0f6bcf JCPV	233	#define CONFIG_SYS_BANK0_START 0x00000000
	234	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	235	#define CONFIG_SYS_BANK0_ENABLE 1
	236	#define CONFIG_SYS_BANK1_START 0x3ff00000
	237	#define CONFIG_SYS_BANK1_END 0x3fffffff
	238	#define CONFIG_SYS_BANK1_ENABLE 0
	239	#define CONFIG_SYS_BANK2_START 0x3ff00000
	240	#define CONFIG_SYS_BANK2_END 0x3fffffff
	241	#define CONFIG_SYS_BANK2_ENABLE 0
	242	#define CONFIG_SYS_BANK3_START 0x3ff00000
	243	#define CONFIG_SYS_BANK3_END 0x3fffffff
	244	#define CONFIG_SYS_BANK3_ENABLE 0
	245	#define CONFIG_SYS_BANK4_START 0x3ff00000
	246	#define CONFIG_SYS_BANK4_END 0x3fffffff
	247	#define CONFIG_SYS_BANK4_ENABLE 0
	248	#define CONFIG_SYS_BANK5_START 0x3ff00000
	249	#define CONFIG_SYS_BANK5_END 0x3fffffff
	250	#define CONFIG_SYS_BANK5_ENABLE 0
	251	#define CONFIG_SYS_BANK6_START 0x3ff00000
	252	#define CONFIG_SYS_BANK6_END 0x3fffffff
	253	#define CONFIG_SYS_BANK6_ENABLE 0
	254	#define CONFIG_SYS_BANK7_START 0x3ff00000
	255	#define CONFIG_SYS_BANK7_END 0x3fffffff
	256	#define CONFIG_SYS_BANK7_ENABLE 0
	257
	258	#define CONFIG_SYS_ODCR 0xff
	259	#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
49822e23 WD	260	/* currently accessed page in memory */
49822e23 WD	261	/* see 8240 book for details */
3bac3513	262
6d0f6bcf JCPV	263	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	264	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
3bac3513	265
6d0f6bcf JCPV	266	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	267	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
3bac3513	268
6d0f6bcf JCPV	269	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	270	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
3bac3513	271
6d0f6bcf JCPV	272	#define CONFIG_SYS_IBAT3L (0xFC000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	273	#define CONFIG_SYS_IBAT3U (0xFC000000 \| BATU_BL_64M \| BATU_VS \| BATU_VP)
3bac3513	274
6d0f6bcf JCPV	275	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	276	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	277	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	278	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	279	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	280	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	281	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	282	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
3bac3513 WD	283
	284	/*
	285	* For booting Linux, the board info and command line data
	286	* have to be in the first 8 MB of memory, since this is
	287	* the maximum mapped by the Linux kernel during initialization.
	288	*/
6d0f6bcf	289	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
3bac3513 WD	290
	291	/*-----------------------------------------------------------------------
	292	* FLASH organization
	293	*/
6d0f6bcf JCPV	294	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
6d0f6bcf JCPV	295	#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
3bac3513	296	#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */
6d0f6bcf JCPV	297	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	298	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
3bac3513 WD	299
	300	/* Warining: environment is not EMBEDDED in the ppcboot code.
	301	* It's stored in flash separately.
	302	*/
5a1aceb0	303	#define CONFIG_ENV_IS_IN_FLASH 1
3bac3513	304
6d0f6bcf	305	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x7F8000)
0e8d1586 JCPV	306	#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
	307	#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
	308	#define CONFIG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
3bac3513 WD	309
	310	/*-----------------------------------------------------------------------
	311	* Cache Configuration
	312	*/
6d0f6bcf	313	#define CONFIG_SYS_CACHELINE_SIZE 32
49cf7e8e	314	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	315	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
3bac3513 WD	316	#endif
3bac3513 WD	317
49822e23 WD	318	/----------------------------------------------------------------------/
	319	/* CPC45 Memory Map */
	320	/----------------------------------------------------------------------/
	321	#define SRAM_BASE 0x80000000 /* SRAM base address */
36116650	322	#define SRAM_END 0x801FFFFF
49822e23 WD	323	#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
	324	#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
	325	#define BCSR_BASE 0x80600000 /* board control / status registers */
	326	#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
e2ffd59b	327	#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */
49822e23	328	#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
3bac3513	329
36116650 WD	330	#define CONFIG_SYS_SRAM_BASE SRAM_BASE
36116650 WD	331	#define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1)
3bac3513 WD	332
3bac3513 WD	333	/---------------------------------------------------------------------/
49822e23	334	/* CPC45 Control/Status Registers */
3bac3513	335	/---------------------------------------------------------------------/
49822e23 WD	336	#define IRQ_ENA_1 ((volatile uchar)(BCSR_BASE + 0x00))
	337	#define IRQ_STAT_1 ((volatile uchar)(BCSR_BASE + 0x01))
	338	#define IRQ_ENA_2 ((volatile uchar)(BCSR_BASE + 0x02))
	339	#define IRQ_STAT_2 ((volatile uchar)(BCSR_BASE + 0x03))
	340	#define BOARD_CTRL ((volatile uchar)(BCSR_BASE + 0x04))
	341	#define BOARD_STAT ((volatile uchar)(BCSR_BASE + 0x05))
	342	#define WDG_START ((volatile uchar)(BCSR_BASE + 0x06))
	343	#define WDG_PRESTOP ((volatile uchar)(BCSR_BASE + 0x06))
	344	#define WDG_STOP ((volatile uchar)(BCSR_BASE + 0x06))
	345	#define BOARD_REV ((volatile uchar)(BCSR_BASE + 0x07))
3bac3513 WD	346
3bac3513 WD	347	/* IRQ_ENA_1 bit definitions */
49822e23 WD	348	#define I_ENA_1_IERA 0x80 /* INTA enable */
	349	#define I_ENA_1_IERB 0x40 /* INTB enable */
	350	#define I_ENA_1_IERC 0x20 /* INTC enable */
	351	#define I_ENA_1_IERD 0x10 /* INTD enable */
3bac3513 WD	352
3bac3513 WD	353	/* IRQ_STAT_1 bit definitions */
49822e23 WD	354	#define I_STAT_1_INTA 0x80 /* INTA status */
	355	#define I_STAT_1_INTB 0x40 /* INTB status */
	356	#define I_STAT_1_INTC 0x20 /* INTC status */
	357	#define I_STAT_1_INTD 0x10 /* INTD status */
3bac3513 WD	358
3bac3513 WD	359	/* IRQ_ENA_2 bit definitions */
49822e23 WD	360	#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
	361	#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
	362	#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
	363	#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
	364	#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
	365	#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
	366	#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
	367	#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
3bac3513 WD	368
3bac3513 WD	369	/* IRQ_STAT_2 bit definitions */
49822e23 WD	370	#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
	371	#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
	372	#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
	373	#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
	374	#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
	375	#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
	376	#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
	377	#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
3bac3513 WD	378
3bac3513 WD	379	/* BOARD_CTRL bit definitions */
49822e23	380	#define USER_LEDS 2 /* 2 user LEDs */
3bac3513 WD	381
3bac3513 WD	382	#if (USER_LEDS == 4)
49822e23 WD	383	#define B_CTRL_WRSE 0x80
	384	#define B_CTRL_KRSE 0x40
	385	#define B_CTRL_FWRE 0x20 /* Flash write enable */
	386	#define B_CTRL_FWPT 0x10 /* Flash write protect */
	387	#define B_CTRL_LED3 0x08 /* LED 3 control */
	388	#define B_CTRL_LED2 0x04 /* LED 2 control */
	389	#define B_CTRL_LED1 0x02 /* LED 1 control */
	390	#define B_CTRL_LED0 0x01 /* LED 0 control */
3bac3513	391	#else
49822e23 WD	392	#define B_CTRL_WRSE 0x80
	393	#define B_CTRL_KRSE 0x40
	394	#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
	395	#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
	396	#define B_CTRL_LED1 0x08 /* LED 1 control */
	397	#define B_CTRL_LED0 0x04 /* LED 0 control */
	398	#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
	399	#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
3bac3513 WD	400	#endif
	401
	402	/* BOARD_STAT bit definitions */
49822e23 WD	403	#define B_STAT_WDGE 0x80
	404	#define B_STAT_WDGS 0x40
	405	#define B_STAT_WRST 0x20
	406	#define B_STAT_KRST 0x10
	407	#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
	408	#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
	409	#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
	410	#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
3bac3513 WD	411
3bac3513 WD	412	/---------------------------------------------------------------------/
49822e23	413	/* Display addresses */
3bac3513	414	/---------------------------------------------------------------------/
49822e23 WD	415	#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
	416	#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
	417	#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
3bac3513	418
49822e23 WD	419	#define DISP_UDC_ADR ((volatile uchar)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
49822e23 WD	420	#define DISP_CWORD ((volatile uchar)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
3bac3513	421
49822e23 WD	422	#define DISP_DIG0 ((volatile uchar)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
	423	#define DISP_DIG1 ((volatile uchar)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
	424	#define DISP_DIG2 ((volatile uchar)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
	425	#define DISP_DIG3 ((volatile uchar)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
	426	#define DISP_DIG4 ((volatile uchar)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
	427	#define DISP_DIG5 ((volatile uchar)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
	428	#define DISP_DIG6 ((volatile uchar)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
	429	#define DISP_DIG7 ((volatile uchar)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
3bac3513 WD	430
	431
	432	/*-----------------------------------------------------------------------
	433	* PCI stuff
	434	*-----------------------------------------------------------------------
	435	*/
	436	#define CONFIG_PCI /* include pci support */
842033e6	437	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
76221a6c	438	#define CONFIG_SYS_EARLY_PCI_INIT
49822e23 WD	439	#undef CONFIG_PCI_PNP
49822e23 WD	440	#undef CONFIG_PCI_SCAN_SHOW
3bac3513	441
3bac3513 WD	442
3bac3513 WD	443	#define CONFIG_EEPRO100
6d0f6bcf	444	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
3bac3513	445
49822e23	446	#define PCI_ENET0_IOADDR 0x82000000
3bac3513	447	#define PCI_ENET0_MEMADDR 0x82000000
49822e23 WD	448	#define PCI_PLX9030_IOADDR 0x82100000
49822e23 WD	449	#define PCI_PLX9030_MEMADDR 0x82100000
e2ffd59b WD	450
	451	/*-----------------------------------------------------------------------
	452	* PCMCIA stuff
	453	*-----------------------------------------------------------------------
	454	*/
	455
	456	#define CONFIG_I82365
	457
6d0f6bcf JCPV	458	#define CONFIG_SYS_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE
6d0f6bcf JCPV	459	#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
e2ffd59b WD	460
	461	#define CONFIG_PCMCIA_SLOT_A
	462
	463	/*-----------------------------------------------------------------------
	464	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	465	*-----------------------------------------------------------------------
	466	*/
	467
8d1165e1	468	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
e2ffd59b WD	469	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	470
	471	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	472	#undef CONFIG_IDE_RESET /* reset for IDE not supported */
	473	#define CONFIG_IDE_LED /* LED for IDE is supported */
	474
6d0f6bcf JCPV	475	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	476	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
e2ffd59b	477
6d0f6bcf	478	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
e2ffd59b	479
6d0f6bcf	480	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
e2ffd59b	481
6d0f6bcf	482	#define CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_PCMCIA_MEM_SIZE
e2ffd59b WD	483
e2ffd59b WD	484	/* Offset for normal register accesses */
6d0f6bcf	485	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
e2ffd59b WD	486
e2ffd59b WD	487	/* Offset for alternate registers */
6d0f6bcf	488	#define CONFIG_SYS_ATA_ALT_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)
e2ffd59b WD	489
	490	#define CONFIG_DOS_PARTITION
	491
3bac3513	492	#endif /* __CONFIG_H */