[people/ms/u-boot.git] / include / configs / CPC45.h

/*
 * (C) Copyright 2001-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 *
 * Configuration settings for the CPC45 board.
 *
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_CPC45		1


#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"

#define CONFIG_BOOTDELAY	5

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_BEDBUG	| \
				CFG_CMD_DATE	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_EEPROM	| \
				CFG_CMD_EXT2	| \
				CFG_CMD_FAT	| \
				CFG_CMD_FLASH	| \
				CFG_CMD_I2C	| \
				CFG_CMD_IDE	| \
				CFG_CMD_NFS	| \
				CFG_CMD_PCI	| \
				CFG_CMD_PING	| \
				CFG_CMD_SDRAM	| \
				CFG_CMD_SNTP	)

/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
 */
#include <cmd_confdefs.h>


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/

#if 1
#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
#endif
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

/* Print Buffer Size
 */
#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)

#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */

#define CFG_SDRAM_BASE		0x00000000

#if defined(CONFIG_BOOT_ROM)
#define CFG_FLASH_BASE		0xFF000000
#else
#define CFG_FLASH_BASE		0xFF800000
#endif

#define CFG_RESET_ADDRESS	0xFFF00100

#define CFG_EUMB_ADDR		0xFCE00000

#define CFG_MONITOR_BASE	TEXT_BASE

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

#define CFG_MEMTEST_START	0x00004000	/* memtest works on		*/
#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/

/* Maximum amount of RAM.
 */
#define CFG_MAX_RAM_SIZE	0x10000000


#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#undef CFG_RAMBOOT
#else
#define CFG_RAMBOOT
#endif


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */

/* Size in bytes reserved for initial data
 */
#define CFG_GBL_DATA_SIZE	128

#define CFG_INIT_RAM_ADDR	0x40000000
#define CFG_INIT_RAM_END	0x1000
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

/*
 * NS16550 Configuration
 */
#define CFG_NS16550
#define CFG_NS16550_SERIAL

#define CFG_NS16550_REG_SIZE	1

#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
#define DUART_DCR		(CFG_EUMB_ADDR + 0x4511)

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */

#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * RTC configuration
 */
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR	0x51

/*
 * EEPROM configuration
 */
#define CFG_I2C_EEPROM_ADDR		0x58
#define CFG_I2C_EEPROM_ADDR_LEN		1
#define CFG_EEPROM_PAGE_WRITE_BITS	4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ	33000000
#define CFG_HZ			1000


/* Bit-field values for MCCR1.
 */
#define CFG_ROMNAL		0
#define CFG_ROMFAL		8

#define CFG_BANK0_ROW		0	/* SDRAM bank 7-0 row address */
#define CFG_BANK1_ROW		0
#define CFG_BANK2_ROW		0
#define CFG_BANK3_ROW		0
#define CFG_BANK4_ROW		0
#define CFG_BANK5_ROW		0
#define CFG_BANK6_ROW		0
#define CFG_BANK7_ROW		0

/* Bit-field values for MCCR2.
 */

#define CFG_REFINT		0x2ec

/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 */
#define CFG_BSTOPRE		160

/* Bit-field values for MCCR3.
 */
#define CFG_REFREC		2	/* Refresh to activate interval		*/
#define CFG_RDLAT		0	/* Data latancy from read command	*/

/* Bit-field values for MCCR4.
 */
#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
#define CFG_SDMODE_CAS_LAT	2	/* SDMODE CAS latancy			*/
#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length			*/
#define CFG_ACTORW		2
#define CFG_REGISTERD_TYPE_BUFFER 1
#define CFG_EXTROM		0
#define CFG_REGDIMM		0

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CFG_BANK0_START		0x00000000
#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
#define CFG_BANK0_ENABLE	1
#define CFG_BANK1_START		0x3ff00000
#define CFG_BANK1_END		0x3fffffff
#define CFG_BANK1_ENABLE	0
#define CFG_BANK2_START		0x3ff00000
#define CFG_BANK2_END		0x3fffffff
#define CFG_BANK2_ENABLE	0
#define CFG_BANK3_START		0x3ff00000
#define CFG_BANK3_END		0x3fffffff
#define CFG_BANK3_ENABLE	0
#define CFG_BANK4_START		0x3ff00000
#define CFG_BANK4_END		0x3fffffff
#define CFG_BANK4_ENABLE	0
#define CFG_BANK5_START		0x3ff00000
#define CFG_BANK5_END		0x3fffffff
#define CFG_BANK5_ENABLE	0
#define CFG_BANK6_START		0x3ff00000
#define CFG_BANK6_END		0x3fffffff
#define CFG_BANK6_ENABLE	0
#define CFG_BANK7_START		0x3ff00000
#define CFG_BANK7_END		0x3fffffff
#define CFG_BANK7_ENABLE	0

#define CFG_ODCR		0xff
#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)

#define CFG_DBAT0L  CFG_IBAT0L
#define CFG_DBAT0U  CFG_IBAT0U
#define CFG_DBAT1L  CFG_IBAT1L
#define CFG_DBAT1U  CFG_IBAT1U
#define CFG_DBAT2L  CFG_IBAT2L
#define CFG_DBAT2U  CFG_IBAT2U
#define CFG_DBAT3L  CFG_IBAT3L
#define CFG_DBAT3U  CFG_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
#define CFG_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
#define INTEL_ID_28F160F3T	0x88F388F3	/*  16M = 1M x 16 top boot sector	*/
#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

	/* Warining: environment is not EMBEDDED in the ppcboot code.
	 * It's stored in flash separately.
	 */
#define CFG_ENV_IS_IN_FLASH	    1

#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x7F8000)
#define CFG_ENV_SIZE		0x4000	/* Size of the Environment		*/
#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
#define CFG_ENV_SECT_SIZE	0x8000 /* Size of the Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/


#define SRAM_BASE		0x80000000	/* SRAM base address	*/
#define SRAM_END		0x801FFFFF

/*----------------------------------------------------------------------*/
/* CPC45 Memory Map							*/
/*----------------------------------------------------------------------*/
#define SRAM_BASE	0x80000000	/* SRAM base address		*/
#define ST16552_A_BASE	0x80200000	/* ST16552 channel A		*/
#define ST16552_B_BASE	0x80400000	/* ST16552 channel A		*/
#define BCSR_BASE	0x80600000	/* board control / status registers */
#define DISPLAY_BASE	0x80600040	/* DISPLAY base			*/
#define PCMCIA_MEM_BASE 0x83000000	/* PCMCIA memory window base	*/
#define PCMCIA_IO_BASE	0xFE000000	/* PCMCIA IO window base	*/


/*---------------------------------------------------------------------*/
/* CPC45 Control/Status Registers				       */
/*---------------------------------------------------------------------*/
#define IRQ_ENA_1		*((volatile uchar*)(BCSR_BASE + 0x00))
#define IRQ_STAT_1		*((volatile uchar*)(BCSR_BASE + 0x01))
#define IRQ_ENA_2		*((volatile uchar*)(BCSR_BASE + 0x02))
#define IRQ_STAT_2		*((volatile uchar*)(BCSR_BASE + 0x03))
#define BOARD_CTRL		*((volatile uchar*)(BCSR_BASE + 0x04))
#define BOARD_STAT		*((volatile uchar*)(BCSR_BASE + 0x05))
#define WDG_START		*((volatile uchar*)(BCSR_BASE + 0x06))
#define WDG_PRESTOP		*((volatile uchar*)(BCSR_BASE + 0x06))
#define WDG_STOP		*((volatile uchar*)(BCSR_BASE + 0x06))
#define BOARD_REV		*((volatile uchar*)(BCSR_BASE + 0x07))

/* IRQ_ENA_1 bit definitions */
#define I_ENA_1_IERA	0x80		/* INTA enable			*/
#define I_ENA_1_IERB	0x40		/* INTB enable			*/
#define I_ENA_1_IERC	0x20		/* INTC enable			*/
#define I_ENA_1_IERD	0x10		/* INTD enable			*/

/* IRQ_STAT_1 bit definitions */
#define I_STAT_1_INTA	0x80		/* INTA status			*/
#define I_STAT_1_INTB	0x40		/* INTB status			*/
#define I_STAT_1_INTC	0x20		/* INTC status			*/
#define I_STAT_1_INTD	0x10		/* INTD status			*/

/* IRQ_ENA_2 bit definitions */
#define I_ENA_2_IEAB	0x80		/* ABORT IRQ enable		*/
#define I_ENA_2_IEK1	0x40		/* KEY1 IRQ enable		*/
#define I_ENA_2_IEK2	0x20		/* KEY2 IRQ enable		*/
#define I_ENA_2_IERT	0x10		/* RTC IRQ enable		*/
#define I_ENA_2_IESM	0x08		/* LM81 IRQ enable		*/
#define I_ENA_2_IEDG	0x04		/* DEGENERATING IRQ enable	*/
#define I_ENA_2_IES2	0x02		/* ST16552/B IRQ enable		*/
#define I_ENA_2_IES1	0x01		/* ST16552/A IRQ enable		*/

/* IRQ_STAT_2 bit definitions */
#define I_STAT_2_ABO	0x80		/* ABORT IRQ status		*/
#define I_STAT_2_KY1	0x40		/* KEY1 IRQ status		*/
#define I_STAT_2_KY2	0x20		/* KEY2 IRQ status		*/
#define I_STAT_2_RTC	0x10		/* RTC IRQ status		*/
#define I_STAT_2_SMN	0x08		/* LM81 IRQ status		*/
#define I_STAT_2_DEG	0x04		/* DEGENERATING IRQ status	*/
#define I_STAT_2_SIO2	0x02		/* ST16552/B IRQ status		*/
#define I_STAT_2_SIO1	0x01		/* ST16552/A IRQ status		*/

/* BOARD_CTRL bit definitions */
#define USER_LEDS		2			/* 2 user LEDs	*/

#if (USER_LEDS == 4)
#define B_CTRL_WRSE		0x80
#define B_CTRL_KRSE		0x40
#define B_CTRL_FWRE		0x20		/* Flash write enable		*/
#define B_CTRL_FWPT		0x10		/* Flash write protect		*/
#define B_CTRL_LED3		0x08		/* LED 3 control		*/
#define B_CTRL_LED2		0x04		/* LED 2 control		*/
#define B_CTRL_LED1		0x02		/* LED 1 control		*/
#define B_CTRL_LED0		0x01		/* LED 0 control		*/
#else
#define B_CTRL_WRSE		0x80
#define B_CTRL_KRSE		0x40
#define B_CTRL_FWRE_1		0x20		/* Flash write enable		*/
#define B_CTRL_FWPT_1		0x10		/* Flash write protect		*/
#define B_CTRL_LED1		0x08		/* LED 1 control		*/
#define B_CTRL_LED0		0x04		/* LED 0 control		*/
#define B_CTRL_FWRE_0		0x02		/* Flash write enable		*/
#define B_CTRL_FWPT_0		0x01		/* Flash write protect		*/
#endif

/* BOARD_STAT bit definitions */
#define B_STAT_WDGE		0x80
#define B_STAT_WDGS		0x40
#define B_STAT_WRST		0x20
#define B_STAT_KRST		0x10
#define B_STAT_CSW3		0x08		/* sitch bit 3 status		*/
#define B_STAT_CSW2		0x04		/* sitch bit 2 status		*/
#define B_STAT_CSW1		0x02		/* sitch bit 1 status		*/
#define B_STAT_CSW0		0x01		/* sitch bit 0 status		*/

/*---------------------------------------------------------------------*/
/* Display addresses						       */
/*---------------------------------------------------------------------*/
#define DISP_UDC_RAM	(DISPLAY_BASE + 0x08)	/* UDC RAM	       */
#define DISP_CHR_RAM	(DISPLAY_BASE + 0x18)	/* character Ram       */
#define DISP_FLASH	(DISPLAY_BASE + 0x20)	/* Flash Ram	       */

#define DISP_UDC_ADR	*((volatile uchar*)(DISPLAY_BASE + 0x00))	/* UDC Address Reg.    */
#define DISP_CWORD	*((volatile uchar*)(DISPLAY_BASE + 0x10))	/* Control Word Reg.   */

#define DISP_DIG0	*((volatile uchar*)(DISP_CHR_RAM + 0x00))	/* Digit 0 address     */
#define DISP_DIG1	*((volatile uchar*)(DISP_CHR_RAM + 0x01))	/* Digit 0 address     */
#define DISP_DIG2	*((volatile uchar*)(DISP_CHR_RAM + 0x02))	/* Digit 0 address     */
#define DISP_DIG3	*((volatile uchar*)(DISP_CHR_RAM + 0x03))	/* Digit 0 address     */
#define DISP_DIG4	*((volatile uchar*)(DISP_CHR_RAM + 0x04))	/* Digit 0 address     */
#define DISP_DIG5	*((volatile uchar*)(DISP_CHR_RAM + 0x05))	/* Digit 0 address     */
#define DISP_DIG6	*((volatile uchar*)(DISP_CHR_RAM + 0x06))	/* Digit 0 address     */
#define DISP_DIG7	*((volatile uchar*)(DISP_CHR_RAM + 0x07))	/* Digit 0 address     */


/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI			/* include pci support			*/
#undef	CONFIG_PCI_PNP
#undef	CONFIG_PCI_SCAN_SHOW

#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/

#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/

#define PCI_ENET0_IOADDR	0x82000000
#define PCI_ENET0_MEMADDR	0x82000000
#define PCI_PLX9030_IOADDR	0x82100000
#define PCI_PLX9030_MEMADDR	0x82100000

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 */

#define CONFIG_I82365

#define CFG_PCMCIA_MEM_ADDR	PCMCIA_MEM_BASE
#define CFG_PCMCIA_MEM_SIZE	0x1000

#define CONFIG_PCMCIA_SLOT_A

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for IDE not supported	*/
#define	CONFIG_IDE_LED			/* LED   for IDE is  supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

#define CFG_ATA_DATA_OFFSET	CFG_PCMCIA_MEM_SIZE

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x400)

#define CONFIG_DOS_PARTITION

#endif	/* __CONFIG_H */
Commit	Line	Data
3bac3513	1	/*
414eec35	2	* (C) Copyright 2001-2005
3bac3513 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	*
	26	* Configuration settings for the CPC45 board.
	27	*
	28	*/
	29
	30	/* ------------------------------------------------------------------------- */
	31
	32	/*
	33	* board/config.h - configuration options, board specific
	34	*/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*
	40	* High Level Configuration Options
	41	* (easy to change)
	42	*/
	43
	44	#define CONFIG_MPC824X 1
	45	#define CONFIG_MPC8245 1
	46	#define CONFIG_CPC45 1
	47
	48
	49	#define CONFIG_CONS_INDEX 1
	50	#define CONFIG_BAUDRATE 9600
	51	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	52
3bac3513 WD	53	#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
	54
	55	#define CONFIG_BOOTDELAY 5
	56
	57	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE)
	58
	59	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
49822e23 WD	60	CFG_CMD_BEDBUG \| \
49822e23 WD	61	CFG_CMD_DATE \| \
3bac3513	62	CFG_CMD_DHCP \| \
49822e23	63	CFG_CMD_EEPROM \| \
436be29c	64	CFG_CMD_EXT2 \| \
e2ffd59b WD	65	CFG_CMD_FAT \| \
e2ffd59b WD	66	CFG_CMD_FLASH \| \
49822e23	67	CFG_CMD_I2C \| \
e2ffd59b	68	CFG_CMD_IDE \| \
436be29c	69	CFG_CMD_NFS \| \
3bac3513	70	CFG_CMD_PCI \| \
436be29c	71	CFG_CMD_PING \| \
414eec35 WD	72	CFG_CMD_SDRAM \| \
414eec35 WD	73	CFG_CMD_SNTP )
3bac3513 WD	74
	75	/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
	76	*/
	77	#include <cmd_confdefs.h>
	78
	79
	80	/*
	81	* Miscellaneous configurable options
	82	*/
	83	#define CFG_LONGHELP /* undef to save memory */
	84	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	85	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	86
	87	#if 1
49822e23	88	#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
3bac3513 WD	89	#endif
3bac3513 WD	90	#ifdef CFG_HUSH_PARSER
49822e23	91	#define CFG_PROMPT_HUSH_PS2 "> "
3bac3513 WD	92	#endif
	93
	94	/* Print Buffer Size
	95	*/
	96	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
	97
49822e23	98	#define CFG_MAXARGS 16 /* max number of command args */
3bac3513 WD	99	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	100	#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
	101
	102	/*-----------------------------------------------------------------------
	103	* Start addresses for the final memory configuration
	104	* (Set up by the startup code)
	105	* Please note that CFG_SDRAM_BASE _must_ start at 0
	106	*/
	107
49822e23	108	#define CFG_SDRAM_BASE 0x00000000
3bac3513 WD	109
3bac3513 WD	110	#if defined(CONFIG_BOOT_ROM)
49822e23	111	#define CFG_FLASH_BASE 0xFF000000
3bac3513	112	#else
49822e23	113	#define CFG_FLASH_BASE 0xFF800000
3bac3513 WD	114	#endif
3bac3513 WD	115
49822e23	116	#define CFG_RESET_ADDRESS 0xFFF00100
3bac3513	117
49822e23	118	#define CFG_EUMB_ADDR 0xFCE00000
3bac3513	119
49822e23	120	#define CFG_MONITOR_BASE TEXT_BASE
3bac3513	121
49822e23 WD	122	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
49822e23 WD	123	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
3bac3513	124
49822e23 WD	125	#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
49822e23 WD	126	#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
3bac3513	127
49822e23 WD	128	/* Maximum amount of RAM.
	129	*/
	130	#define CFG_MAX_RAM_SIZE 0x10000000
3bac3513 WD	131
	132
	133	#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
	134	#undef CFG_RAMBOOT
	135	#else
	136	#define CFG_RAMBOOT
	137	#endif
	138
	139
	140	/*-----------------------------------------------------------------------
	141	* Definitions for initial stack pointer and data area
	142	*/
	143
49822e23 WD	144	/* Size in bytes reserved for initial data
	145	*/
	146	#define CFG_GBL_DATA_SIZE 128
3bac3513	147
49822e23 WD	148	#define CFG_INIT_RAM_ADDR 0x40000000
	149	#define CFG_INIT_RAM_END 0x1000
	150	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
3bac3513 WD	151
	152	/*
	153	* NS16550 Configuration
	154	*/
53cf9435	155	#define CFG_NS16550
3bac3513 WD	156	#define CFG_NS16550_SERIAL
	157
	158	#define CFG_NS16550_REG_SIZE 1
	159
	160	#define CFG_NS16550_CLK get_bus_freq(0)
	161
	162	#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
	163	#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
49822e23 WD	164	#define DUART_DCR (CFG_EUMB_ADDR + 0x4511)
	165
	166	/*
	167	* I2C configuration
	168	*/
	169	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	170
	171	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	172	#define CFG_I2C_SLAVE 0x7F
	173
	174	/*
	175	* RTC configuration
	176	*/
	177	#define CONFIG_RTC_PCF8563
	178	#define CFG_I2C_RTC_ADDR 0x51
	179
	180	/*
	181	* EEPROM configuration
	182	*/
	183	#define CFG_I2C_EEPROM_ADDR 0x58
	184	#define CFG_I2C_EEPROM_ADDR_LEN 1
	185	#define CFG_EEPROM_PAGE_WRITE_BITS 4
	186	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
	187	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
3bac3513 WD	188
	189	/*
	190	* Low Level Configuration Settings
	191	* (address mappings, register initial values, etc.)
	192	* You should know what you are doing if you make changes here.
	193	* For the detail description refer to the MPC8240 user's manual.
	194	*/
	195
49822e23 WD	196	#define CONFIG_SYS_CLK_FREQ 33000000
49822e23 WD	197	#define CFG_HZ 1000
53cf9435	198
3bac3513	199
49822e23 WD	200	/* Bit-field values for MCCR1.
	201	*/
	202	#define CFG_ROMNAL 0
	203	#define CFG_ROMFAL 8
	204
	205	#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
	206	#define CFG_BANK1_ROW 0
	207	#define CFG_BANK2_ROW 0
	208	#define CFG_BANK3_ROW 0
	209	#define CFG_BANK4_ROW 0
	210	#define CFG_BANK5_ROW 0
	211	#define CFG_BANK6_ROW 0
	212	#define CFG_BANK7_ROW 0
	213
	214	/* Bit-field values for MCCR2.
	215	*/
3bac3513	216
49822e23	217	#define CFG_REFINT 0x2ec
3bac3513	218
49822e23 WD	219	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	220	*/
	221	#define CFG_BSTOPRE 160
3bac3513	222
49822e23 WD	223	/* Bit-field values for MCCR3.
	224	*/
	225	#define CFG_REFREC 2 /* Refresh to activate interval */
	226	#define CFG_RDLAT 0 /* Data latancy from read command */
3bac3513	227
49822e23 WD	228	/* Bit-field values for MCCR4.
	229	*/
	230	#define CFG_PRETOACT 2 /* Precharge to activate interval */
	231	#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
	232	#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
	233	#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
	234	#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
	235	#define CFG_ACTORW 2
3bac3513	236	#define CFG_REGISTERD_TYPE_BUFFER 1
49822e23 WD	237	#define CFG_EXTROM 0
49822e23 WD	238	#define CFG_REGDIMM 0
3bac3513 WD	239
	240	/* Memory bank settings.
	241	* Only bits 20-29 are actually used from these vales to set the
	242	* start/end addresses. The upper two bits will always be 0, and the lower
	243	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
	244	* address. Refer to the MPC8240 book.
	245	*/
	246
49822e23 WD	247	#define CFG_BANK0_START 0x00000000
	248	#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
	249	#define CFG_BANK0_ENABLE 1
	250	#define CFG_BANK1_START 0x3ff00000
	251	#define CFG_BANK1_END 0x3fffffff
	252	#define CFG_BANK1_ENABLE 0
	253	#define CFG_BANK2_START 0x3ff00000
	254	#define CFG_BANK2_END 0x3fffffff
	255	#define CFG_BANK2_ENABLE 0
	256	#define CFG_BANK3_START 0x3ff00000
	257	#define CFG_BANK3_END 0x3fffffff
	258	#define CFG_BANK3_ENABLE 0
	259	#define CFG_BANK4_START 0x3ff00000
	260	#define CFG_BANK4_END 0x3fffffff
	261	#define CFG_BANK4_ENABLE 0
	262	#define CFG_BANK5_START 0x3ff00000
	263	#define CFG_BANK5_END 0x3fffffff
	264	#define CFG_BANK5_ENABLE 0
	265	#define CFG_BANK6_START 0x3ff00000
	266	#define CFG_BANK6_END 0x3fffffff
	267	#define CFG_BANK6_ENABLE 0
	268	#define CFG_BANK7_START 0x3ff00000
	269	#define CFG_BANK7_END 0x3fffffff
	270	#define CFG_BANK7_ENABLE 0
	271
	272	#define CFG_ODCR 0xff
	273	#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
	274	/* currently accessed page in memory */
	275	/* see 8240 book for details */
3bac3513 WD	276
	277	#define CFG_IBAT0L (CFG_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	278	#define CFG_IBAT0U (CFG_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	279
	280	#define CFG_IBAT1L (CFG_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	281	#define CFG_IBAT1U (CFG_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	282
	283	#define CFG_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	284	#define CFG_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	285
	286	#define CFG_IBAT3L (0xFC000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	287	#define CFG_IBAT3U (0xFC000000 \| BATU_BL_64M \| BATU_VS \| BATU_VP)
	288
	289	#define CFG_DBAT0L CFG_IBAT0L
	290	#define CFG_DBAT0U CFG_IBAT0U
	291	#define CFG_DBAT1L CFG_IBAT1L
	292	#define CFG_DBAT1U CFG_IBAT1U
	293	#define CFG_DBAT2L CFG_IBAT2L
	294	#define CFG_DBAT2U CFG_IBAT2U
	295	#define CFG_DBAT3L CFG_IBAT3L
	296	#define CFG_DBAT3U CFG_IBAT3U
	297
	298	/*
	299	* For booting Linux, the board info and command line data
	300	* have to be in the first 8 MB of memory, since this is
	301	* the maximum mapped by the Linux kernel during initialization.
	302	*/
49822e23	303	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
3bac3513 WD	304
	305	/*-----------------------------------------------------------------------
	306	* FLASH organization
	307	*/
	308	#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
	309	#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
	310	#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */
	311	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	312	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	313
	314	/* Warining: environment is not EMBEDDED in the ppcboot code.
	315	* It's stored in flash separately.
	316	*/
	317	#define CFG_ENV_IS_IN_FLASH 1
	318
49822e23	319	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7F8000)
3bac3513 WD	320	#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
	321	#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
	322	#define CFG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
	323
	324	/*-----------------------------------------------------------------------
	325	* Cache Configuration
	326	*/
	327	#define CFG_CACHELINE_SIZE 32
	328	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	329	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	330	#endif
	331
	332	/*
	333	* Internal Definitions
	334	*
	335	* Boot Flags
	336	*/
	337	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	338	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	339
	340
49822e23 WD	341	#define SRAM_BASE 0x80000000 /* SRAM base address */
49822e23 WD	342	#define SRAM_END 0x801FFFFF
3bac3513	343
49822e23 WD	344	/----------------------------------------------------------------------/
	345	/* CPC45 Memory Map */
	346	/----------------------------------------------------------------------/
	347	#define SRAM_BASE 0x80000000 /* SRAM base address */
	348	#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
	349	#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
	350	#define BCSR_BASE 0x80600000 /* board control / status registers */
	351	#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
e2ffd59b	352	#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */
49822e23	353	#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
3bac3513 WD	354
	355
	356	/---------------------------------------------------------------------/
49822e23	357	/* CPC45 Control/Status Registers */
3bac3513	358	/---------------------------------------------------------------------/
49822e23 WD	359	#define IRQ_ENA_1 ((volatile uchar)(BCSR_BASE + 0x00))
	360	#define IRQ_STAT_1 ((volatile uchar)(BCSR_BASE + 0x01))
	361	#define IRQ_ENA_2 ((volatile uchar)(BCSR_BASE + 0x02))
	362	#define IRQ_STAT_2 ((volatile uchar)(BCSR_BASE + 0x03))
	363	#define BOARD_CTRL ((volatile uchar)(BCSR_BASE + 0x04))
	364	#define BOARD_STAT ((volatile uchar)(BCSR_BASE + 0x05))
	365	#define WDG_START ((volatile uchar)(BCSR_BASE + 0x06))
	366	#define WDG_PRESTOP ((volatile uchar)(BCSR_BASE + 0x06))
	367	#define WDG_STOP ((volatile uchar)(BCSR_BASE + 0x06))
	368	#define BOARD_REV ((volatile uchar)(BCSR_BASE + 0x07))
3bac3513 WD	369
3bac3513 WD	370	/* IRQ_ENA_1 bit definitions */
49822e23 WD	371	#define I_ENA_1_IERA 0x80 /* INTA enable */
	372	#define I_ENA_1_IERB 0x40 /* INTB enable */
	373	#define I_ENA_1_IERC 0x20 /* INTC enable */
	374	#define I_ENA_1_IERD 0x10 /* INTD enable */
3bac3513 WD	375
3bac3513 WD	376	/* IRQ_STAT_1 bit definitions */
49822e23 WD	377	#define I_STAT_1_INTA 0x80 /* INTA status */
	378	#define I_STAT_1_INTB 0x40 /* INTB status */
	379	#define I_STAT_1_INTC 0x20 /* INTC status */
	380	#define I_STAT_1_INTD 0x10 /* INTD status */
3bac3513 WD	381
3bac3513 WD	382	/* IRQ_ENA_2 bit definitions */
49822e23 WD	383	#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
	384	#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
	385	#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
	386	#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
	387	#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
	388	#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
	389	#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
	390	#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
3bac3513 WD	391
3bac3513 WD	392	/* IRQ_STAT_2 bit definitions */
49822e23 WD	393	#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
	394	#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
	395	#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
	396	#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
	397	#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
	398	#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
	399	#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
	400	#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
3bac3513 WD	401
3bac3513 WD	402	/* BOARD_CTRL bit definitions */
49822e23	403	#define USER_LEDS 2 /* 2 user LEDs */
3bac3513 WD	404
3bac3513 WD	405	#if (USER_LEDS == 4)
49822e23 WD	406	#define B_CTRL_WRSE 0x80
	407	#define B_CTRL_KRSE 0x40
	408	#define B_CTRL_FWRE 0x20 /* Flash write enable */
	409	#define B_CTRL_FWPT 0x10 /* Flash write protect */
	410	#define B_CTRL_LED3 0x08 /* LED 3 control */
	411	#define B_CTRL_LED2 0x04 /* LED 2 control */
	412	#define B_CTRL_LED1 0x02 /* LED 1 control */
	413	#define B_CTRL_LED0 0x01 /* LED 0 control */
3bac3513	414	#else
49822e23 WD	415	#define B_CTRL_WRSE 0x80
	416	#define B_CTRL_KRSE 0x40
	417	#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
	418	#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
	419	#define B_CTRL_LED1 0x08 /* LED 1 control */
	420	#define B_CTRL_LED0 0x04 /* LED 0 control */
	421	#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
	422	#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
3bac3513 WD	423	#endif
	424
	425	/* BOARD_STAT bit definitions */
49822e23 WD	426	#define B_STAT_WDGE 0x80
	427	#define B_STAT_WDGS 0x40
	428	#define B_STAT_WRST 0x20
	429	#define B_STAT_KRST 0x10
	430	#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
	431	#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
	432	#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
	433	#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
3bac3513 WD	434
3bac3513 WD	435	/---------------------------------------------------------------------/
49822e23	436	/* Display addresses */
3bac3513	437	/---------------------------------------------------------------------/
49822e23 WD	438	#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
	439	#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
	440	#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
3bac3513	441
49822e23 WD	442	#define DISP_UDC_ADR ((volatile uchar)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
49822e23 WD	443	#define DISP_CWORD ((volatile uchar)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
3bac3513	444
49822e23 WD	445	#define DISP_DIG0 ((volatile uchar)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
	446	#define DISP_DIG1 ((volatile uchar)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
	447	#define DISP_DIG2 ((volatile uchar)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
	448	#define DISP_DIG3 ((volatile uchar)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
	449	#define DISP_DIG4 ((volatile uchar)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
	450	#define DISP_DIG5 ((volatile uchar)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
	451	#define DISP_DIG6 ((volatile uchar)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
	452	#define DISP_DIG7 ((volatile uchar)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
3bac3513 WD	453
	454
	455	/*-----------------------------------------------------------------------
	456	* PCI stuff
	457	*-----------------------------------------------------------------------
	458	*/
	459	#define CONFIG_PCI /* include pci support */
49822e23 WD	460	#undef CONFIG_PCI_PNP
49822e23 WD	461	#undef CONFIG_PCI_SCAN_SHOW
3bac3513	462
49822e23	463	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
3bac3513 WD	464
3bac3513 WD	465	#define CONFIG_EEPRO100
49822e23	466	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
3bac3513	467
49822e23	468	#define PCI_ENET0_IOADDR 0x82000000
3bac3513	469	#define PCI_ENET0_MEMADDR 0x82000000
49822e23 WD	470	#define PCI_PLX9030_IOADDR 0x82100000
49822e23 WD	471	#define PCI_PLX9030_MEMADDR 0x82100000
e2ffd59b WD	472
	473	/*-----------------------------------------------------------------------
	474	* PCMCIA stuff
	475	*-----------------------------------------------------------------------
	476	*/
	477
	478	#define CONFIG_I82365
	479
	480	#define CFG_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE
	481	#define CFG_PCMCIA_MEM_SIZE 0x1000
	482
	483	#define CONFIG_PCMCIA_SLOT_A
	484
	485	/*-----------------------------------------------------------------------
	486	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	487	*-----------------------------------------------------------------------
	488	*/
	489
	490	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	491
	492	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	493	#undef CONFIG_IDE_RESET /* reset for IDE not supported */
	494	#define CONFIG_IDE_LED /* LED for IDE is supported */
	495
	496	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	497	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	498
	499	#define CFG_ATA_IDE0_OFFSET 0x0000
e2ffd59b WD	500
	501	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
	502
	503	#define CFG_ATA_DATA_OFFSET CFG_PCMCIA_MEM_SIZE
	504
	505	/* Offset for normal register accesses */
1a344f29	506	#define CFG_ATA_REG_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
e2ffd59b WD	507
	508	/* Offset for alternate registers */
	509	#define CFG_ATA_ALT_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x400)
	510
	511	#define CONFIG_DOS_PARTITION
	512
3bac3513	513	#endif /* __CONFIG_H */