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7644f16f SR |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
7644f16f SR |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
21 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
22 | ||
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
24 | ||
7644f16f SR |
25 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
26 | ||
27 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ | |
28 | ||
29 | #define CONFIG_BAUDRATE 9600 | |
30 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
31 | ||
32 | #undef CONFIG_BOOTARGS | |
33 | #undef CONFIG_BOOTCOMMAND | |
34 | ||
35 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
36 | ||
37 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 38 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
7644f16f SR |
39 | |
40 | #define CONFIG_MII 1 /* MII PHY management */ | |
41 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
42 | ||
11799434 JL |
43 | /* |
44 | * BOOTP options | |
45 | */ | |
46 | #define CONFIG_BOOTP_BOOTFILESIZE | |
47 | #define CONFIG_BOOTP_BOOTPATH | |
48 | #define CONFIG_BOOTP_GATEWAY | |
49 | #define CONFIG_BOOTP_HOSTNAME | |
50 | ||
51 | ||
49cf7e8e JL |
52 | /* |
53 | * Command line configuration. | |
54 | */ | |
55 | #include <config_cmd_default.h> | |
56 | ||
57 | #define CONFIG_CMD_PCI | |
58 | #define CONFIG_CMD_IRQ | |
59 | #define CONFIG_CMD_ELF | |
60 | #define CONFIG_CMD_I2C | |
61 | #define CONFIG_CMD_BSP | |
62 | #define CONFIG_CMD_EEPROM | |
63 | ||
64 | #undef CONFIG_CMD_NET | |
ee8028b7 | 65 | #undef CONFIG_CMD_NFS |
7644f16f SR |
66 | |
67 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
68 | ||
69 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
70 | ||
71 | /* | |
72 | * Miscellaneous configurable options | |
73 | */ | |
6d0f6bcf | 74 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
7644f16f | 75 | |
6d0f6bcf | 76 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
7644f16f | 77 | |
49cf7e8e | 78 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 79 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
7644f16f | 80 | #else |
6d0f6bcf | 81 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
7644f16f | 82 | #endif |
6d0f6bcf JCPV |
83 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
84 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
85 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
7644f16f | 86 | |
6d0f6bcf | 87 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
7644f16f | 88 | |
6d0f6bcf | 89 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
7644f16f SR |
90 | |
91 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ | |
92 | ||
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
94 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
7644f16f | 95 | |
550650dd SR |
96 | #define CONFIG_CONS_INDEX 2 /* Use UART1 */ |
97 | #define CONFIG_SYS_NS16550 | |
98 | #define CONFIG_SYS_NS16550_SERIAL | |
99 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
100 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
101 | ||
6d0f6bcf | 102 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 103 | #define CONFIG_SYS_BASE_BAUD 691200 |
7644f16f SR |
104 | |
105 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 106 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
7644f16f SR |
107 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
108 | 57600, 115200, 230400, 460800, 921600 } | |
109 | ||
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
111 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
7644f16f | 112 | |
7644f16f SR |
113 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
114 | ||
115 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
116 | ||
117 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
118 | ||
6d0f6bcf | 119 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
7644f16f SR |
120 | |
121 | /*----------------------------------------------------------------------- | |
122 | * PCI stuff | |
123 | *----------------------------------------------------------------------- | |
124 | */ | |
125 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
126 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
127 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
128 | ||
129 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 130 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
7644f16f SR |
131 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
132 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
133 | /* resource configuration */ | |
134 | ||
135 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
136 | ||
137 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
138 | ||
139 | #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ | |
140 | ||
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
142 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */ | |
143 | #define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ | |
2076d0a1 | 144 | |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ |
146 | #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ | |
147 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
148 | #define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */ | |
149 | #define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */ | |
150 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ | |
7644f16f SR |
151 | |
152 | /*----------------------------------------------------------------------- | |
153 | * Start addresses for the final memory configuration | |
154 | * (Set up by the startup code) | |
6d0f6bcf | 155 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
7644f16f | 156 | */ |
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
158 | #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 | |
159 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
160 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ | |
161 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
7644f16f SR |
162 | |
163 | /* | |
164 | * For booting Linux, the board info and command line data | |
165 | * have to be in the first 8 MB of memory, since this is | |
166 | * the maximum mapped by the Linux kernel during initialization. | |
167 | */ | |
6d0f6bcf | 168 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
7644f16f SR |
169 | /*----------------------------------------------------------------------- |
170 | * FLASH organization | |
171 | */ | |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
173 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
7644f16f | 174 | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
176 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
7644f16f | 177 | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
179 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
180 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
7644f16f | 181 | |
6d0f6bcf JCPV |
182 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
183 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
184 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
7644f16f | 185 | |
6d0f6bcf | 186 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
7644f16f | 187 | |
bb1f8b4f | 188 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
189 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
190 | #define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ | |
7644f16f SR |
191 | |
192 | /*----------------------------------------------------------------------- | |
193 | * I2C EEPROM (CAT24WC16) for environment | |
194 | */ | |
880540de DE |
195 | #define CONFIG_SYS_I2C |
196 | #define CONFIG_SYS_I2C_PPC4XX | |
197 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
198 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
199 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
7644f16f | 200 | |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
202 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
7644f16f | 203 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
205 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
7644f16f SR |
206 | /* 16 byte page write mode using*/ |
207 | /* last 4 bits of the address */ | |
6d0f6bcf | 208 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
7644f16f | 209 | |
6d0f6bcf | 210 | #define CONFIG_SYS_EEPROM_WREN 1 |
7644f16f | 211 | |
7644f16f SR |
212 | /* |
213 | * Init Memory Controller: | |
214 | * | |
215 | * BR0/1 and OR0/1 (FLASH) | |
216 | */ | |
217 | #define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ | |
218 | #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ | |
219 | ||
220 | /*----------------------------------------------------------------------- | |
221 | * External Bus Controller (EBC) Setup | |
222 | */ | |
223 | ||
224 | /* Memory Bank 0 (Flash Bank 0) initialization */ | |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
226 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
7644f16f SR |
227 | |
228 | /* Memory Bank 2 (PB0) initialization */ | |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ |
230 | #define CONFIG_SYS_EBC_PB2CR 0xEF018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
7644f16f SR |
231 | |
232 | /* Memory Bank 3 (PB1) initialization */ | |
6d0f6bcf JCPV |
233 | #define CONFIG_SYS_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ |
234 | #define CONFIG_SYS_EBC_PB3CR 0xEF118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ | |
7644f16f SR |
235 | |
236 | /*----------------------------------------------------------------------- | |
237 | * Definitions for initial stack pointer and data area (in data cache) | |
238 | */ | |
6d0f6bcf | 239 | #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ |
7644f16f | 240 | |
6d0f6bcf | 241 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ |
553f0982 | 242 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
25ddd1fb | 243 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 244 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
7644f16f SR |
245 | |
246 | /*----------------------------------------------------------------------- | |
247 | * GPIO definitions | |
248 | */ | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */ |
250 | #define CONFIG_SYS_SELF_RST (0x80000000 >> 14) /* GPIO14 */ | |
251 | #define CONFIG_SYS_PB_LED (0x80000000 >> 16) /* GPIO16 */ | |
252 | #define CONFIG_SYS_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */ | |
7644f16f | 253 | |
7644f16f | 254 | #endif /* __CONFIG_H */ |