[thirdparty/u-boot.git] / include / configs / CPCI405.h

/*
 * (C) Copyright 2001
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	 1	/* call misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#undef	CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */

#undef  CONFIG_HAS_ETH1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MII
#define CONFIG_CMD_EEPROM


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_SUPPORT_VFAT

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD	    691200

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_LOOPW            1       /* enable loopw command         */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
					/* resource configuration       */

#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */

#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/

#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */

#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/

#if 1 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
#define CONFIG_ENV_ADDR		\
	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/

#else /* Use EEPROM for environment variables */

#define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
				   /* total size of a CAT24WC08 is 1024 bytes */
#endif

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC08) for environment
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		0x92015480
#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1) initialization					*/
#define CONFIG_SYS_EBC_PB1AP		0x92015480
#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization			*/
#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (CompactFlash IDE) initialization				*/
#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 4 (NVRAM) initialization						*/
#define CONFIG_SYS_EBC_PB4AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 5 (Quart) initialization						*/
#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/

/*-----------------------------------------------------------------------
 * FPGA stuff
 */

/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
#define CONFIG_SYS_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
#define CONFIG_SYS_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
#if 1 /* test-only */
#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */

#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
#else
#define CONFIG_SYS_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
#endif
#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1	21	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c609719b WD	22	#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
c609719b WD	23
2ae18241 WD	24	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	25
c837dcb1	26	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
3a8f28d0	27	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
c609719b	28
c837dcb1	29	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
c609719b WD	30
	31	#define CONFIG_BAUDRATE 9600
	32	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	33
c609719b	34	#undef CONFIG_BOOTARGS
a20b27a3 SR	35	#undef CONFIG_BOOTCOMMAND
	36
	37	#define CONFIG_PREBOOT /* enable preboot variable */
c609719b WD	38
c609719b WD	39	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	40	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
c609719b	41
96e21f86	42	#define CONFIG_PPC4xx_EMAC
c609719b	43	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	44	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	45	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
6f35c531 MF	46	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
6f35c531 MF	47
6f35c531	48	#undef CONFIG_HAS_ETH1
c609719b	49
5d2ebe1b JL	50	/*
	51	* BOOTP options
	52	*/
	53	#define CONFIG_BOOTP_SUBNETMASK
	54	#define CONFIG_BOOTP_GATEWAY
	55	#define CONFIG_BOOTP_HOSTNAME
	56	#define CONFIG_BOOTP_BOOTPATH
	57	#define CONFIG_BOOTP_DNS
	58	#define CONFIG_BOOTP_DNS2
	59	#define CONFIG_BOOTP_SEND_HOSTNAME
	60
9919f13c	61
49cf7e8e JL	62	/*
	63	* Command line configuration.
	64	*/
	65	#include <config_cmd_default.h>
	66
	67	#define CONFIG_CMD_DHCP
	68	#define CONFIG_CMD_PCI
	69	#define CONFIG_CMD_IRQ
	70	#define CONFIG_CMD_IDE
	71	#define CONFIG_CMD_FAT
	72	#define CONFIG_CMD_ELF
	73	#define CONFIG_CMD_MII
	74	#define CONFIG_CMD_EEPROM
	75
c609719b WD	76
	77	#define CONFIG_MAC_PARTITION
	78	#define CONFIG_DOS_PARTITION
	79
a20b27a3 SR	80	#define CONFIG_SUPPORT_VFAT
a20b27a3 SR	81
c837dcb1	82	#undef CONFIG_WATCHDOG /* watchdog disabled */
c609719b	83
c837dcb1	84	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c609719b WD	85
	86	/*
	87	* Miscellaneous configurable options
	88	*/
6d0f6bcf JCPV	89	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	90	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
c609719b	91
6d0f6bcf	92	#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
c609719b	93
49cf7e8e	94	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	95	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	96	#else
6d0f6bcf	97	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b	98	#endif
6d0f6bcf JCPV	99	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	100	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	101	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c609719b	102
6d0f6bcf	103	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
c609719b	104
6d0f6bcf	105	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c609719b	106
6d0f6bcf JCPV	107	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	108	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
c609719b	109
550650dd SR	110	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	111	#define CONFIG_SYS_NS16550
	112	#define CONFIG_SYS_NS16550_SERIAL
	113	#define CONFIG_SYS_NS16550_REG_SIZE 1
	114	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	115
6d0f6bcf	116	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf	117	#define CONFIG_SYS_BASE_BAUD 691200
c609719b WD	118
c609719b WD	119	/* The following table includes the supported baudrates */
6d0f6bcf	120	#define CONFIG_SYS_BAUDRATE_TABLE \
8bde7f77 WD	121	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	122	57600, 115200, 230400, 460800, 921600 }
c609719b	123
6d0f6bcf JCPV	124	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	125	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
c609719b	126
6d0f6bcf	127	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b	128
a20b27a3 SR	129	#define CONFIG_LOOPW 1 /* enable loopw command */
a20b27a3 SR	130
c609719b WD	131	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	132
	133	/*-----------------------------------------------------------------------
	134	* PCI stuff
	135	*-----------------------------------------------------------------------
	136	*/
a20b27a3 SR	137	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	138	#define PCI_HOST_FORCE 1 /* configure as pci host */
	139	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	140
	141	#define CONFIG_PCI /* include pci support */
842033e6	142	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
a20b27a3 SR	143	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	144	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	145	/* resource configuration */
	146
	147	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	148
	149	#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
	150
	151	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
	152
6d0f6bcf JCPV	153	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	154	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	155	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
	156	#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	157	#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
	158	#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) \| 1) /* memsize, enable hard-wired to 1 */
	159	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	160	#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
	161	#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
468ebf19	162	#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
c609719b	163
82379b55 MF	164	#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
82379b55 MF	165
c609719b WD	166	/*-----------------------------------------------------------------------
	167	* IDE/ATA stuff
	168	*-----------------------------------------------------------------------
	169	*/
c837dcb1 WD	170	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	171	#undef CONFIG_IDE_LED /* no led for ide supported */
	172	#undef CONFIG_IDE_RESET /* no reset for ide supported */
c609719b	173
6d0f6bcf JCPV	174	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
6d0f6bcf JCPV	175	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS1) / max. 1 drives per IDE bus */
c609719b	176
6d0f6bcf JCPV	177	#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
6d0f6bcf JCPV	178	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
c609719b	179
6d0f6bcf JCPV	180	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
	181	#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
	182	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
c609719b WD	183
	184	/*-----------------------------------------------------------------------
	185	* Start addresses for the final memory configuration
	186	* (Set up by the startup code)
6d0f6bcf	187	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	188	*/
6d0f6bcf	189	#define CONFIG_SYS_SDRAM_BASE 0x00000000
14d0a02a WD	190	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
	191	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	192	#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
6d0f6bcf	193	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
c609719b WD	194
	195	/*
	196	* For booting Linux, the board info and command line data
	197	* have to be in the first 8 MB of memory, since this is
	198	* the maximum mapped by the Linux kernel during initialization.
	199	*/
6d0f6bcf	200	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	201	/*-----------------------------------------------------------------------
	202	* FLASH organization
	203	*/
6d0f6bcf JCPV	204	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	205	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
c609719b	206
6d0f6bcf JCPV	207	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	208	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b	209
6d0f6bcf JCPV	210	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	211	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	212	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c609719b WD	213	/*
	214	* The following defines are added for buggy IOP480 byte interface.
	215	* All other boards should use the standard values (CPCI405 etc.)
	216	*/
6d0f6bcf JCPV	217	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	218	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	219	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
c609719b	220
6d0f6bcf	221	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c609719b	222
6d0f6bcf JCPV	223	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
	224	#define CONFIG_SYS_NVRAM_SIZE (321024) / NVRAM size */
	225	#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
a20b27a3	226
c609719b WD	227	#if 1 /* Use NVRAM for environment variables */
	228	/*-----------------------------------------------------------------------
	229	* NVRAM organization
	230	*/
9314cee6	231	#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
0e8d1586 JCPV	232	#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
0e8d1586 JCPV	233	#define CONFIG_ENV_ADDR \
6d0f6bcf	234	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
c609719b WD	235
	236	#else /* Use EEPROM for environment variables */
	237
bb1f8b4f	238	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	239	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	240	#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
8bde7f77	241	/* total size of a CAT24WC08 is 1024 bytes */
c609719b WD	242	#endif
	243
	244	/*-----------------------------------------------------------------------
	245	* I2C EEPROM (CAT24WC08) for environment
	246	*/
880540de DE	247	#define CONFIG_SYS_I2C
	248	#define CONFIG_SYS_I2C_PPC4XX
	249	#define CONFIG_SYS_I2C_PPC4XX_CH0
	250	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	251	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
c609719b	252
6d0f6bcf JCPV	253	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
6d0f6bcf JCPV	254	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1	255	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	256	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	257	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
c609719b	258	/* 16 byte page write mode using*/
c837dcb1	259	/* last 4 bits of the address */
6d0f6bcf	260	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
c609719b	261
c609719b WD	262	/*
	263	* Init Memory Controller:
	264	*
	265	* BR0/1 and OR0/1 (FLASH)
	266	*/
	267
	268	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
	269	#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
	270
	271	/*-----------------------------------------------------------------------
	272	* External Bus Controller (EBC) Setup
	273	*/
	274
c837dcb1	275	/* Memory Bank 0 (Flash Bank 0) initialization */
6d0f6bcf JCPV	276	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	277	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c609719b	278
c837dcb1	279	/* Memory Bank 1 (Flash Bank 1) initialization */
6d0f6bcf JCPV	280	#define CONFIG_SYS_EBC_PB1AP 0x92015480
6d0f6bcf JCPV	281	#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
c609719b	282
c837dcb1	283	/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */
6d0f6bcf JCPV	284	#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	285	#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
c609719b	286
c837dcb1	287	/* Memory Bank 3 (CompactFlash IDE) initialization */
6d0f6bcf JCPV	288	#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	289	#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
c609719b	290
c837dcb1	291	/* Memory Bank 4 (NVRAM) initialization */
6d0f6bcf JCPV	292	#define CONFIG_SYS_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
6d0f6bcf JCPV	293	#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
c609719b	294
c837dcb1	295	/* Memory Bank 5 (Quart) initialization */
6d0f6bcf JCPV	296	#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
6d0f6bcf JCPV	297	#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
c609719b WD	298
	299	/*-----------------------------------------------------------------------
	300	* FPGA stuff
	301	*/
	302
	303	/* FPGA program pin configuration */
6d0f6bcf JCPV	304	#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	305	#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	306	#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	307	#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
	308	#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
c609719b WD	309
	310	/*-----------------------------------------------------------------------
	311	* Definitions for initial stack pointer and data area (in data cache)
	312	*/
	313	#if 1 /* test-only */
6d0f6bcf	314	#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
c609719b	315
6d0f6bcf	316	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
c609719b	317	#else
6d0f6bcf	318	#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
c609719b	319	#endif
553f0982	320	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
25ddd1fb	321	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	322	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b	323
c609719b	324	#endif /* __CONFIG_H */