[people/ms/u-boot.git] / include / configs / CPCI405AB.h

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
#define CONFIG_CPCI405AB	1	/* ...and special AB version	*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#undef	CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#undef	CONFIG_LOADS_ECHO		/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */

#define CONFIG_NET_MULTI	1
#undef  CONFIG_HAS_ETH1

#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_SUPPORT_VFAT

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
#define CFG_BASE_BAUD	    691200

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/

#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A	*/
#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/

#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	0xF0100000
#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFC0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

/*
 * JFFS2 partitions
 */
/* No command line, one static partition */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */

/* Use first bank for JFFS2, second bank contains U-Boot.
 *
 * Note: fake mtd_id's used, no linux mtd map file.
 */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=cpci405ab-0"
#define MTDPARTS_DEFAULT	"mtdparts=cpci405ab-0:-(jffs2)"
*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC32) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
#define CFG_I2C_MULTI_EEPROMS   1       /* more than one eeprom used!   */
#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
					/* 32 byte page write mode using*/
					/* last 5 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/* Use EEPROM for environment variables */

#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
				   /* total size of a CAT24WC32 is 4096 bytes */

#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CFG_EBC_PB0AP		0x92015480
#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1) initialization					*/
#define CFG_EBC_PB1AP		0x92015480
#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (CAN0, 1) initialization					*/
#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
#define CFG_LED_ADDR		0xF0000380

/* Memory Bank 3 (CompactFlash IDE) initialization				*/
#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 4 (NVRAM/RTC) initialization					*/
/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 5 (optional Quart) initialization				*/
#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 6 (FPGA internal) initialization					*/
#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
#define CFG_FPGA_BASE_ADDR	0xF0400000

/*-----------------------------------------------------------------------
 * FPGA stuff
 */
/* FPGA internal regs */
#define CFG_FPGA_MODE		0x00
#define CFG_FPGA_STATUS		0x02
#define CFG_FPGA_TS		0x04
#define CFG_FPGA_TS_LOW		0x06
#define CFG_FPGA_TS_CAP0	0x10
#define CFG_FPGA_TS_CAP0_LOW	0x12
#define CFG_FPGA_TS_CAP1	0x14
#define CFG_FPGA_TS_CAP1_LOW	0x16
#define CFG_FPGA_TS_CAP2	0x18
#define CFG_FPGA_TS_CAP2_LOW	0x1a
#define CFG_FPGA_TS_CAP3	0x1c
#define CFG_FPGA_TS_CAP3_LOW	0x1e

/* FPGA Mode Reg */
#define CFG_FPGA_MODE_CF_RESET	    0x0001
#define CFG_FPGA_MODE_DUART_RESET   0x0002
#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
#define CFG_FPGA_MODE_1WIRE_DIR     0x0100     /* dir=1 -> output */
#define CFG_FPGA_MODE_SIM_OK_DIR    0x0200
#define CFG_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
#define CFG_FPGA_MODE_1WIRE         0x1000
#define CFG_FPGA_MODE_SIM_OK        0x2000     /* wired-or net from all devices */
#define CFG_FPGA_MODE_TESTRIG_FAIL  0x4000

/* FPGA Status Reg */
#define CFG_FPGA_STATUS_DIP0    0x0001
#define CFG_FPGA_STATUS_DIP1    0x0002
#define CFG_FPGA_STATUS_DIP2    0x0004
#define CFG_FPGA_STATUS_FLASH   0x0008
#define CFG_FPGA_STATUS_1WIRE   0x1000
#define CFG_FPGA_STATUS_SIM_OK  0x2000

#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S30 */

/* FPGA program pin configuration */
#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */

#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
d4629c8c SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
d4629c8c	38	#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
c837dcb1 WD	39	#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
c837dcb1 WD	40	#define CONFIG_CPCI405AB 1 /* ...and special AB version */
d4629c8c	41
c837dcb1	42	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
d4629c8c	43
a20b27a3	44	#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
d4629c8c SR	45
	46	#define CONFIG_BAUDRATE 9600
	47	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	48
d4629c8c	49	#undef CONFIG_BOOTARGS
a20b27a3 SR	50	#undef CONFIG_BOOTCOMMAND
	51
	52	#define CONFIG_PREBOOT /* enable preboot variable */
d4629c8c	53
c837dcb1	54	#undef CONFIG_LOADS_ECHO /* echo on for serial download */
d4629c8c SR	55	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	56
	57	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	58	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	59	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
6f35c531 MF	60	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
	61
	62	#define CONFIG_NET_MULTI 1
	63	#undef CONFIG_HAS_ETH1
d4629c8c SR	64
	65	#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
	66
5d2ebe1b JL	67	/*
	68	* BOOTP options
	69	*/
	70	#define CONFIG_BOOTP_SUBNETMASK
	71	#define CONFIG_BOOTP_GATEWAY
	72	#define CONFIG_BOOTP_HOSTNAME
	73	#define CONFIG_BOOTP_BOOTPATH
	74	#define CONFIG_BOOTP_DNS
	75	#define CONFIG_BOOTP_DNS2
	76	#define CONFIG_BOOTP_SEND_HOSTNAME
	77
d4629c8c	78
49cf7e8e JL	79	/*
	80	* Command line configuration.
	81	*/
	82	#include <config_cmd_default.h>
	83
	84	#define CONFIG_CMD_DHCP
	85	#define CONFIG_CMD_PCI
	86	#define CONFIG_CMD_IRQ
	87	#define CONFIG_CMD_IDE
	88	#define CONFIG_CMD_FAT
	89	#define CONFIG_CMD_ELF
	90	#define CONFIG_CMD_DATE
	91	#define CONFIG_CMD_JFFS2
	92	#define CONFIG_CMD_I2C
	93	#define CONFIG_CMD_MII
	94	#define CONFIG_CMD_PING
	95	#define CONFIG_CMD_EEPROM
	96
d4629c8c SR	97
	98	#define CONFIG_MAC_PARTITION
	99	#define CONFIG_DOS_PARTITION
	100
a20b27a3 SR	101	#define CONFIG_SUPPORT_VFAT
a20b27a3 SR	102
c837dcb1	103	#undef CONFIG_WATCHDOG /* watchdog disabled */
d4629c8c	104
c837dcb1	105	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
d4629c8c SR	106
	107	/*
	108	* Miscellaneous configurable options
	109	*/
	110	#define CFG_LONGHELP /* undef to save memory */
	111	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	112
	113	#undef CFG_HUSH_PARSER /* use "hush" command parser */
	114	#ifdef CFG_HUSH_PARSER
c837dcb1	115	#define CFG_PROMPT_HUSH_PS2 "> "
d4629c8c SR	116	#endif
d4629c8c SR	117
49cf7e8e	118	#if defined(CONFIG_CMD_KGDB)
c837dcb1	119	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
d4629c8c	120	#else
c837dcb1	121	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
d4629c8c SR	122	#endif
	123	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	124	#define CFG_MAXARGS 16 /* max number of command args */
	125	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	126
c837dcb1	127	#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
d4629c8c	128
c837dcb1	129	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
d4629c8c SR	130
	131	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	132	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	133
c837dcb1 WD	134	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	135	#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	136	#define CFG_BASE_BAUD 691200
d4629c8c SR	137
d4629c8c SR	138	/* The following table includes the supported baudrates */
c837dcb1	139	#define CFG_BAUDRATE_TABLE \
8bde7f77 WD	140	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	141	57600, 115200, 230400, 460800, 921600 }
d4629c8c SR	142
	143	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	144	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	145
c837dcb1	146	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
d4629c8c SR	147
	148	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	149
c837dcb1	150	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
d4629c8c	151
c837dcb1	152	#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
53cf9435	153
d4629c8c SR	154	/*-----------------------------------------------------------------------
	155	* PCI stuff
	156	*-----------------------------------------------------------------------
	157	*/
c837dcb1 WD	158	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	159	#define PCI_HOST_FORCE 1 /* configure as pci host */
	160	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	161
	162	#define CONFIG_PCI /* include pci support */
	163	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	164	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	165	/* resource configuration */
	166
	167	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	168
a20b27a3 SR	169	#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
a20b27a3 SR	170
c837dcb1 WD	171	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
	172
	173	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	174	#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	175	#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
	176	#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
2076d0a1 SR	177	#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
2076d0a1 SR	178	#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) \| 1) /* memsize, enable hard-wired to 1 */
c837dcb1 WD	179	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	180	#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	181	#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	182	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
d4629c8c SR	183
	184	/*-----------------------------------------------------------------------
	185	* IDE/ATA stuff
	186	*-----------------------------------------------------------------------
	187	*/
c837dcb1 WD	188	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
c837dcb1 WD	189	#undef CONFIG_IDE_LED /* no led for ide supported */
d4629c8c SR	190	#define CONFIG_IDE_RESET 1 /* reset for ide supported */
d4629c8c SR	191
c837dcb1 WD	192	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
c837dcb1 WD	193	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 1 drives per IDE bus */
d4629c8c	194
c837dcb1 WD	195	#define CFG_ATA_BASE_ADDR 0xF0100000
c837dcb1 WD	196	#define CFG_ATA_IDE0_OFFSET 0x0000
d4629c8c SR	197
d4629c8c SR	198	#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
c837dcb1	199	#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
d4629c8c SR	200	#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
	201
	202	/*-----------------------------------------------------------------------
	203	* Start addresses for the final memory configuration
	204	* (Set up by the startup code)
	205	* Please note that CFG_SDRAM_BASE _must_ start at 0
	206	*/
	207	#define CFG_SDRAM_BASE 0x00000000
	208	#define CFG_FLASH_BASE 0xFFFC0000
	209	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	210	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
53cf9435	211	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
d4629c8c SR	212
	213	/*
	214	* For booting Linux, the board info and command line data
	215	* have to be in the first 8 MB of memory, since this is
	216	* the maximum mapped by the Linux kernel during initialization.
	217	*/
	218	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	219	/*-----------------------------------------------------------------------
	220	* FLASH organization
	221	*/
	222	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	223	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	224
	225	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	226	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	227
c837dcb1 WD	228	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	229	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	230	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
d4629c8c SR	231	/*
	232	* The following defines are added for buggy IOP480 byte interface.
	233	* All other boards should use the standard values (CPCI405 etc.)
	234	*/
c837dcb1 WD	235	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	236	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	237	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
d4629c8c	238
c837dcb1	239	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
d4629c8c	240
700a0c64 WD	241	/*
	242	* JFFS2 partitions
	243	*/
	244	/* No command line, one static partition */
	245	#undef CONFIG_JFFS2_CMDLINE
	246	#define CONFIG_JFFS2_DEV "nor0"
	247	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	248	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	249
	250	/* mtdparts command line support */
	251
	252	/* Use first bank for JFFS2, second bank contains U-Boot.
	253	*
	254	* Note: fake mtd_id's used, no linux mtd map file.
	255	*/
	256	/*
	257	#define CONFIG_JFFS2_CMDLINE
	258	#define MTDIDS_DEFAULT "nor0=cpci405ab-0"
	259	#define MTDPARTS_DEFAULT "mtdparts=cpci405ab-0:-(jffs2)"
	260	*/
d4629c8c	261
d4629c8c	262	/*-----------------------------------------------------------------------
2853d29b	263	* I2C EEPROM (CAT24WC32) for environment
d4629c8c	264	*/
2853d29b	265	#define CONFIG_HARD_I2C /* I2c with hardware support */
a20b27a3	266	#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
2853d29b	267	#define CFG_I2C_SLAVE 0x7F
d4629c8c	268
2853d29b	269	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
c837dcb1 WD	270	#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
c837dcb1 WD	271	/* mask of address bits that overflow into the "EEPROM chip address" */
2853d29b	272	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
a20b27a3	273	#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom used! */
2853d29b SR	274	#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
2853d29b SR	275	/* 32 byte page write mode using*/
c837dcb1	276	/* last 5 bits of the address */
2853d29b SR	277	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	278	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	279
	280	/* Use EEPROM for environment variables */
d4629c8c	281
c837dcb1 WD	282	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	283	#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
	284	#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
2853d29b	285	/* total size of a CAT24WC32 is 4096 bytes */
d4629c8c SR	286
	287	#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
	288	#define CFG_NVRAM_SIZE (321024) / NVRAM size */
a20b27a3	289	#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
d4629c8c	290
d4629c8c SR	291	/*
	292	* Init Memory Controller:
	293	*
	294	* BR0/1 and OR0/1 (FLASH)
	295	*/
	296
	297	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
	298	#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
	299
	300	/*-----------------------------------------------------------------------
	301	* External Bus Controller (EBC) Setup
	302	*/
	303
c837dcb1 WD	304	/* Memory Bank 0 (Flash Bank 0) initialization */
	305	#define CFG_EBC_PB0AP 0x92015480
	306	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
d4629c8c	307
c837dcb1 WD	308	/* Memory Bank 1 (Flash Bank 1) initialization */
	309	#define CFG_EBC_PB1AP 0x92015480
	310	#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
d4629c8c	311
c837dcb1 WD	312	/* Memory Bank 2 (CAN0, 1) initialization */
	313	#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	314	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
	315	#define CFG_LED_ADDR 0xF0000380
d4629c8c	316
c837dcb1 WD	317	/* Memory Bank 3 (CompactFlash IDE) initialization */
	318	#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	319	#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
d4629c8c	320
c837dcb1 WD	321	/* Memory Bank 4 (NVRAM/RTC) initialization */
	322	/#define CFG_EBC_PB4AP 0x01805280 / TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
	323	#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
	324	#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
d4629c8c	325
c837dcb1 WD	326	/* Memory Bank 5 (optional Quart) initialization */
	327	#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
	328	#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
d4629c8c	329
c837dcb1 WD	330	/* Memory Bank 6 (FPGA internal) initialization */
	331	#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	332	#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
	333	#define CFG_FPGA_BASE_ADDR 0xF0400000
d4629c8c SR	334
	335	/*-----------------------------------------------------------------------
	336	* FPGA stuff
	337	*/
	338	/* FPGA internal regs */
c837dcb1 WD	339	#define CFG_FPGA_MODE 0x00
	340	#define CFG_FPGA_STATUS 0x02
	341	#define CFG_FPGA_TS 0x04
	342	#define CFG_FPGA_TS_LOW 0x06
	343	#define CFG_FPGA_TS_CAP0 0x10
	344	#define CFG_FPGA_TS_CAP0_LOW 0x12
	345	#define CFG_FPGA_TS_CAP1 0x14
	346	#define CFG_FPGA_TS_CAP1_LOW 0x16
	347	#define CFG_FPGA_TS_CAP2 0x18
	348	#define CFG_FPGA_TS_CAP2_LOW 0x1a
	349	#define CFG_FPGA_TS_CAP3 0x1c
	350	#define CFG_FPGA_TS_CAP3_LOW 0x1e
d4629c8c SR	351
d4629c8c SR	352	/* FPGA Mode Reg */
c837dcb1	353	#define CFG_FPGA_MODE_CF_RESET 0x0001
d4629c8c SR	354	#define CFG_FPGA_MODE_DUART_RESET 0x0002
d4629c8c SR	355	#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
a20b27a3 SR	356	#define CFG_FPGA_MODE_1WIRE_DIR 0x0100 /* dir=1 -> output */
	357	#define CFG_FPGA_MODE_SIM_OK_DIR 0x0200
	358	#define CFG_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
	359	#define CFG_FPGA_MODE_1WIRE 0x1000
	360	#define CFG_FPGA_MODE_SIM_OK 0x2000 /* wired-or net from all devices */
	361	#define CFG_FPGA_MODE_TESTRIG_FAIL 0x4000
d4629c8c SR	362
d4629c8c SR	363	/* FPGA Status Reg */
a20b27a3 SR	364	#define CFG_FPGA_STATUS_DIP0 0x0001
	365	#define CFG_FPGA_STATUS_DIP1 0x0002
	366	#define CFG_FPGA_STATUS_DIP2 0x0004
	367	#define CFG_FPGA_STATUS_FLASH 0x0008
	368	#define CFG_FPGA_STATUS_1WIRE 0x1000
	369	#define CFG_FPGA_STATUS_SIM_OK 0x2000
d4629c8c	370
c837dcb1 WD	371	#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
c837dcb1 WD	372	#define CFG_FPGA_MAX_SIZE 1281024 / 128kByte is enough for XC2S30 */
d4629c8c SR	373
d4629c8c SR	374	/* FPGA program pin configuration */
c837dcb1 WD	375	#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	376	#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	377	#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	378	#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
	379	#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
d4629c8c SR	380
	381	/*-----------------------------------------------------------------------
	382	* Definitions for initial stack pointer and data area (in data cache)
	383	*/
c837dcb1	384	#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
d4629c8c	385
c837dcb1 WD	386	#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
c837dcb1 WD	387	#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
d4629c8c SR	388	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
d4629c8c SR	389	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c837dcb1	390	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
d4629c8c SR	391
	392
	393	/*
	394	* Internal Definitions
	395	*
	396	* Boot Flags
	397	*/
	398	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	399	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	400
	401	#endif /* __CONFIG_H */