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Commit | Line | Data |
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d4629c8c SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
c837dcb1 | 37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
d4629c8c | 38 | #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ |
c837dcb1 WD |
39 | #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ |
40 | #define CONFIG_CPCI405AB 1 /* ...and special AB version */ | |
d4629c8c | 41 | |
2ae18241 WD |
42 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
43 | ||
c837dcb1 | 44 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
3a8f28d0 | 45 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
d4629c8c | 46 | |
a20b27a3 | 47 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
d4629c8c SR |
48 | |
49 | #define CONFIG_BAUDRATE 9600 | |
50 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
51 | ||
d4629c8c | 52 | #undef CONFIG_BOOTARGS |
a20b27a3 SR |
53 | #undef CONFIG_BOOTCOMMAND |
54 | ||
55 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
d4629c8c | 56 | |
c837dcb1 | 57 | #undef CONFIG_LOADS_ECHO /* echo on for serial download */ |
6d0f6bcf | 58 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
d4629c8c | 59 | |
96e21f86 | 60 | #define CONFIG_PPC4xx_EMAC |
d4629c8c | 61 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 62 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 63 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
6f35c531 MF |
64 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
65 | ||
6f35c531 | 66 | #undef CONFIG_HAS_ETH1 |
d4629c8c SR |
67 | |
68 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ | |
69 | ||
5d2ebe1b JL |
70 | /* |
71 | * BOOTP options | |
72 | */ | |
73 | #define CONFIG_BOOTP_SUBNETMASK | |
74 | #define CONFIG_BOOTP_GATEWAY | |
75 | #define CONFIG_BOOTP_HOSTNAME | |
76 | #define CONFIG_BOOTP_BOOTPATH | |
77 | #define CONFIG_BOOTP_DNS | |
78 | #define CONFIG_BOOTP_DNS2 | |
79 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
80 | ||
d4629c8c | 81 | |
49cf7e8e JL |
82 | /* |
83 | * Command line configuration. | |
84 | */ | |
85 | #include <config_cmd_default.h> | |
86 | ||
87 | #define CONFIG_CMD_DHCP | |
88 | #define CONFIG_CMD_PCI | |
89 | #define CONFIG_CMD_IRQ | |
90 | #define CONFIG_CMD_IDE | |
91 | #define CONFIG_CMD_FAT | |
92 | #define CONFIG_CMD_ELF | |
93 | #define CONFIG_CMD_DATE | |
49cf7e8e JL |
94 | #define CONFIG_CMD_I2C |
95 | #define CONFIG_CMD_MII | |
96 | #define CONFIG_CMD_PING | |
3ba605d4 | 97 | #define CONFIG_CMD_BSP |
49cf7e8e JL |
98 | #define CONFIG_CMD_EEPROM |
99 | ||
d4629c8c SR |
100 | |
101 | #define CONFIG_MAC_PARTITION | |
102 | #define CONFIG_DOS_PARTITION | |
103 | ||
a20b27a3 SR |
104 | #define CONFIG_SUPPORT_VFAT |
105 | ||
c837dcb1 | 106 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
d4629c8c | 107 | |
c837dcb1 | 108 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
d4629c8c SR |
109 | |
110 | /* | |
111 | * Miscellaneous configurable options | |
112 | */ | |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
114 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
d4629c8c | 115 | |
6d0f6bcf | 116 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
d4629c8c | 117 | |
49cf7e8e | 118 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 119 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
d4629c8c | 120 | #else |
6d0f6bcf | 121 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d4629c8c | 122 | #endif |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
124 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
125 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
d4629c8c | 126 | |
6d0f6bcf | 127 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
d4629c8c | 128 | |
6d0f6bcf | 129 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
d4629c8c | 130 | |
6d0f6bcf JCPV |
131 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
132 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
d4629c8c | 133 | |
550650dd SR |
134 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
135 | #define CONFIG_SYS_NS16550 | |
136 | #define CONFIG_SYS_NS16550_SERIAL | |
137 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
138 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
139 | ||
6d0f6bcf | 140 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 141 | #define CONFIG_SYS_BASE_BAUD 691200 |
d4629c8c SR |
142 | |
143 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 144 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8bde7f77 WD |
145 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
146 | 57600, 115200, 230400, 460800, 921600 } | |
d4629c8c | 147 | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
149 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
d4629c8c | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
d4629c8c | 152 | |
ac53ee83 MF |
153 | #define CONFIG_CMDLINE_EDITING /* add command line history */ |
154 | ||
d4629c8c SR |
155 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
156 | ||
c837dcb1 | 157 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
d4629c8c | 158 | |
75511b47 MF |
159 | #define CONFIG_AUTOBOOT_KEYED 1 |
160 | #define CONFIG_AUTOBOOT_PROMPT \ | |
161 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay | |
162 | #undef CONFIG_AUTOBOOT_DELAY_STR | |
163 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
164 | ||
6d0f6bcf | 165 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
53cf9435 | 166 | |
d4629c8c SR |
167 | /*----------------------------------------------------------------------- |
168 | * PCI stuff | |
169 | *----------------------------------------------------------------------- | |
170 | */ | |
c837dcb1 WD |
171 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
172 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
173 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
174 | ||
175 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 176 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
c837dcb1 WD |
177 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
178 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
179 | /* resource configuration */ | |
180 | ||
181 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
182 | ||
a20b27a3 SR |
183 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ |
184 | ||
c837dcb1 WD |
185 | #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ |
186 | ||
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
188 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
189 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ | |
190 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
191 | #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ | |
192 | #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ | |
193 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
194 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
195 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
468ebf19 | 196 | #define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */ |
d4629c8c | 197 | |
82379b55 MF |
198 | #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ |
199 | ||
d4629c8c SR |
200 | /*----------------------------------------------------------------------- |
201 | * IDE/ATA stuff | |
202 | *----------------------------------------------------------------------- | |
203 | */ | |
c837dcb1 WD |
204 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
205 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
d4629c8c SR |
206 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
207 | ||
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
209 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ | |
d4629c8c | 210 | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
212 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
d4629c8c | 213 | |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
215 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
216 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
d4629c8c SR |
217 | |
218 | /*----------------------------------------------------------------------- | |
219 | * Start addresses for the final memory configuration | |
220 | * (Set up by the startup code) | |
6d0f6bcf | 221 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
d4629c8c | 222 | */ |
6d0f6bcf JCPV |
223 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
224 | #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 | |
225 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
226 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ | |
227 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ | |
d4629c8c | 228 | |
3ba605d4 MF |
229 | #define CONFIG_PRAM 0 /* use pram variable to overwrite */ |
230 | ||
d4629c8c SR |
231 | /* |
232 | * For booting Linux, the board info and command line data | |
233 | * have to be in the first 8 MB of memory, since this is | |
234 | * the maximum mapped by the Linux kernel during initialization. | |
235 | */ | |
6d0f6bcf | 236 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
ac53ee83 MF |
237 | |
238 | #define CONFIG_OF_LIBFDT | |
239 | #define CONFIG_OF_BOARD_SETUP | |
240 | ||
d4629c8c SR |
241 | /*----------------------------------------------------------------------- |
242 | * FLASH organization | |
243 | */ | |
6d0f6bcf JCPV |
244 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
245 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
d4629c8c | 246 | |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
248 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
d4629c8c | 249 | |
6d0f6bcf JCPV |
250 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
251 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
252 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
d4629c8c SR |
253 | /* |
254 | * The following defines are added for buggy IOP480 byte interface. | |
255 | * All other boards should use the standard values (CPCI405 etc.) | |
256 | */ | |
6d0f6bcf JCPV |
257 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
258 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
259 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
d4629c8c | 260 | |
6d0f6bcf | 261 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
d4629c8c | 262 | |
d4629c8c | 263 | /*----------------------------------------------------------------------- |
2853d29b | 264 | * I2C EEPROM (CAT24WC32) for environment |
d4629c8c | 265 | */ |
2853d29b | 266 | #define CONFIG_HARD_I2C /* I2c with hardware support */ |
d0b0dcaa | 267 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
6d0f6bcf JCPV |
268 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
269 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
d4629c8c | 270 | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ |
272 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
c837dcb1 | 273 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 |
275 | #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom used! */ | |
276 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ | |
2853d29b | 277 | /* 32 byte page write mode using*/ |
c837dcb1 | 278 | /* last 5 bits of the address */ |
6d0f6bcf | 279 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
2853d29b SR |
280 | |
281 | /* Use EEPROM for environment variables */ | |
d4629c8c | 282 | |
bb1f8b4f | 283 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
284 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
285 | #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ | |
2853d29b | 286 | /* total size of a CAT24WC32 is 4096 bytes */ |
d4629c8c | 287 | |
6d0f6bcf JCPV |
288 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ |
289 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
290 | #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ | |
d4629c8c | 291 | |
d4629c8c SR |
292 | /* |
293 | * Init Memory Controller: | |
294 | * | |
295 | * BR0/1 and OR0/1 (FLASH) | |
296 | */ | |
297 | ||
298 | #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ | |
299 | #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ | |
300 | ||
301 | /*----------------------------------------------------------------------- | |
302 | * External Bus Controller (EBC) Setup | |
303 | */ | |
304 | ||
c837dcb1 | 305 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
6d0f6bcf JCPV |
306 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
307 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
d4629c8c | 308 | |
c837dcb1 | 309 | /* Memory Bank 1 (Flash Bank 1) initialization */ |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
311 | #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ | |
d4629c8c | 312 | |
c837dcb1 | 313 | /* Memory Bank 2 (CAN0, 1) initialization */ |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
315 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
316 | #define CONFIG_SYS_LED_ADDR 0xF0000380 | |
d4629c8c | 317 | |
c837dcb1 | 318 | /* Memory Bank 3 (CompactFlash IDE) initialization */ |
6d0f6bcf JCPV |
319 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
320 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
d4629c8c | 321 | |
c837dcb1 | 322 | /* Memory Bank 4 (NVRAM/RTC) initialization */ |
6d0f6bcf JCPV |
323 | /*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ |
324 | #define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ | |
325 | #define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ | |
d4629c8c | 326 | |
c837dcb1 | 327 | /* Memory Bank 5 (optional Quart) initialization */ |
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ |
329 | #define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ | |
d4629c8c | 330 | |
c837dcb1 | 331 | /* Memory Bank 6 (FPGA internal) initialization */ |
6d0f6bcf JCPV |
332 | #define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
333 | #define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
334 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 | |
d4629c8c SR |
335 | |
336 | /*----------------------------------------------------------------------- | |
337 | * FPGA stuff | |
338 | */ | |
339 | /* FPGA internal regs */ | |
6d0f6bcf JCPV |
340 | #define CONFIG_SYS_FPGA_MODE 0x00 |
341 | #define CONFIG_SYS_FPGA_STATUS 0x02 | |
342 | #define CONFIG_SYS_FPGA_TS 0x04 | |
343 | #define CONFIG_SYS_FPGA_TS_LOW 0x06 | |
344 | #define CONFIG_SYS_FPGA_TS_CAP0 0x10 | |
345 | #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 | |
346 | #define CONFIG_SYS_FPGA_TS_CAP1 0x14 | |
347 | #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 | |
348 | #define CONFIG_SYS_FPGA_TS_CAP2 0x18 | |
349 | #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a | |
350 | #define CONFIG_SYS_FPGA_TS_CAP3 0x1c | |
351 | #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e | |
d4629c8c SR |
352 | |
353 | /* FPGA Mode Reg */ | |
6d0f6bcf JCPV |
354 | #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 |
355 | #define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002 | |
356 | #define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ | |
357 | #define CONFIG_SYS_FPGA_MODE_1WIRE_DIR 0x0100 /* dir=1 -> output */ | |
358 | #define CONFIG_SYS_FPGA_MODE_SIM_OK_DIR 0x0200 | |
359 | #define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400 | |
360 | #define CONFIG_SYS_FPGA_MODE_1WIRE 0x1000 | |
361 | #define CONFIG_SYS_FPGA_MODE_SIM_OK 0x2000 /* wired-or net from all devices */ | |
362 | #define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL 0x4000 | |
d4629c8c SR |
363 | |
364 | /* FPGA Status Reg */ | |
6d0f6bcf JCPV |
365 | #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 |
366 | #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 | |
367 | #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 | |
368 | #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 | |
369 | #define CONFIG_SYS_FPGA_STATUS_1WIRE 0x1000 | |
370 | #define CONFIG_SYS_FPGA_STATUS_SIM_OK 0x2000 | |
d4629c8c | 371 | |
6d0f6bcf JCPV |
372 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
373 | #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S30 */ | |
d4629c8c SR |
374 | |
375 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
376 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
377 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
378 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
379 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
380 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
d4629c8c SR |
381 | |
382 | /*----------------------------------------------------------------------- | |
383 | * Definitions for initial stack pointer and data area (in data cache) | |
384 | */ | |
6d0f6bcf | 385 | #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ |
d4629c8c | 386 | |
6d0f6bcf | 387 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ |
553f0982 | 388 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
25ddd1fb | 389 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 390 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
d4629c8c | 391 | |
d4629c8c | 392 | #endif /* __CONFIG_H */ |