[u-boot.git] / include / configs / CPCI405AB.h

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
#define CONFIG_CPCI405_VER2     1       /* ...version 2                 */
#define CONFIG_CPCI405AB        1       /* ...and special AB version    */

#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */

#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#if 0
#define CONFIG_PREBOOT                                                          \
	"crc32 f0207004 ffc 0;"                                                 \
	"if cmp 0 f0207000 1;"                                                  \
	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
	"else;echo Old CRC is bad;fi"
#endif

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* default boot command	*/

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define	CONFIG_PHY_ADDR		0	/* PHY address			*/

#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */

#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT)

#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_PCI	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_IDE	| \
				CFG_CMD_ELF	| \
				CFG_CMD_DATE	| \
				CFG_CMD_JFFS2	| \
				CFG_CMD_I2C	| \
				CFG_CMD_MII	| \
				CFG_CMD_PING	| \
				CFG_CMD_EEPROM  )

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */

#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
#define CFG_BASE_BAUD       691200

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE      \
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */

#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
					/* resource configuration       */

#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */

#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/

#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define	CFG_ATA_BASE_ADDR	0xF0100000
#define	CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFC0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */

#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */

#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */

#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#define CFG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
#define CFG_ENV_ADDR		\
	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))	/* Env	*/

#else /* Use EEPROM for environment variables */

#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars*/
				   /* total size of a CAT24WC08 is 1024 bytes */
#endif

#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
#define CFG_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC08) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"    */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last	4 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
					/* have only 8kB, 16kB is save here     */
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization                                  */
#define CFG_EBC_PB0AP           0x92015480
#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1) initialization                                  */
#define CFG_EBC_PB1AP           0x92015480
#define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (CAN0, 1) initialization                                       */
#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
#define CFG_LED_ADDR            0xF0000380

/* Memory Bank 3 (CompactFlash IDE) initialization                              */
#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 4 (NVRAM/RTC) initialization                                     */
/*#define CFG_EBC_PB4AP           0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1     */
#define CFG_EBC_PB4AP           0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1     */
#define CFG_EBC_PB4CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */

/* Memory Bank 5 (optional Quart) initialization                                */
#define CFG_EBC_PB5AP           0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
#define CFG_EBC_PB5CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */

/* Memory Bank 6 (FPGA internal) initialization                                 */
#define CFG_EBC_PB6AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB6CR           0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
#define CFG_FPGA_BASE_ADDR      0xF0400000

/*-----------------------------------------------------------------------
 * FPGA stuff
 */
/* FPGA internal regs */
#define CFG_FPGA_MODE           0x00
#define CFG_FPGA_STATUS         0x02
#define CFG_FPGA_TS             0x04
#define CFG_FPGA_TS_LOW         0x06
#define CFG_FPGA_TS_CAP0        0x10
#define CFG_FPGA_TS_CAP0_LOW    0x12
#define CFG_FPGA_TS_CAP1        0x14
#define CFG_FPGA_TS_CAP1_LOW    0x16
#define CFG_FPGA_TS_CAP2        0x18
#define CFG_FPGA_TS_CAP2_LOW    0x1a
#define CFG_FPGA_TS_CAP3        0x1c
#define CFG_FPGA_TS_CAP3_LOW    0x1e

/* FPGA Mode Reg */
#define CFG_FPGA_MODE_CF_RESET      0x0001
#define CFG_FPGA_MODE_DUART_RESET   0x0002
#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
#define CFG_FPGA_MODE_TS_CLEAR      0x2000

/* FPGA Status Reg */
#define CFG_FPGA_STATUS_DIP0    0x0001
#define CFG_FPGA_STATUS_DIP1    0x0002
#define CFG_FPGA_STATUS_DIP2    0x0004
#define CFG_FPGA_STATUS_FLASH   0x0008
#define CFG_FPGA_STATUS_TS_IRQ  0x1000

#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S30 */

/* FPGA program pin configuration */
#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
#define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */

#define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
d4629c8c SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	38	#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
	39	#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
	40	#define CONFIG_CPCI405AB 1 /* ...and special AB version */
	41
	42	#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
	43
	44	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	45
	46	#define CONFIG_BAUDRATE 9600
	47	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	48
	49	#if 0
	50	#define CONFIG_PREBOOT \
8bde7f77 WD	51	"crc32 f0207004 ffc 0;" \
	52	"if cmp 0 f0207000 1;" \
	53	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \
	54	"else;echo Old CRC is bad;fi"
d4629c8c SR	55	#endif
	56
	57	#undef CONFIG_BOOTARGS
53cf9435	58	#define CONFIG_BOOTCOMMAND "bootm 100000" /* default boot command */
d4629c8c SR	59
	60	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	61	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	62
	63	#define CONFIG_MII 1 /* MII PHY management */
	64	#define CONFIG_PHY_ADDR 0 /* PHY address */
	65
	66	#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
	67
d4629c8c	68	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT)
d4629c8c SR	69
	70	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
	71	CFG_CMD_DHCP \| \
	72	CFG_CMD_PCI \| \
	73	CFG_CMD_IRQ \| \
	74	CFG_CMD_IDE \| \
	75	CFG_CMD_ELF \| \
	76	CFG_CMD_DATE \| \
	77	CFG_CMD_JFFS2 \| \
	78	CFG_CMD_I2C \| \
	79	CFG_CMD_MII \| \
a0e135b4	80	CFG_CMD_PING \| \
d4629c8c SR	81	CFG_CMD_EEPROM )
	82
	83	#define CONFIG_MAC_PARTITION
	84	#define CONFIG_DOS_PARTITION
	85
	86	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	87	#include <cmd_confdefs.h>
	88
	89	#undef CONFIG_WATCHDOG /* watchdog disabled */
	90
	91	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	92
	93	/*
	94	* Miscellaneous configurable options
	95	*/
	96	#define CFG_LONGHELP /* undef to save memory */
	97	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	98
	99	#undef CFG_HUSH_PARSER /* use "hush" command parser */
	100	#ifdef CFG_HUSH_PARSER
	101	#define CFG_PROMPT_HUSH_PS2 "> "
	102	#endif
	103
	104	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	105	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	106	#else
	107	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	108	#endif
	109	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	110	#define CFG_MAXARGS 16 /* max number of command args */
	111	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	112
	113	#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
	114
	115	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
	116
	117	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	118	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	119
	120	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	121	#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	122	#define CFG_BASE_BAUD 691200
	123
	124	/* The following table includes the supported baudrates */
	125	#define CFG_BAUDRATE_TABLE \
8bde7f77 WD	126	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	127	57600, 115200, 230400, 460800, 921600 }
d4629c8c SR	128
	129	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	130	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	131
	132	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	133
	134	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	135
	136	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	137
53cf9435 SR	138	#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
53cf9435 SR	139
d4629c8c SR	140	/*-----------------------------------------------------------------------
	141	* PCI stuff
	142	*-----------------------------------------------------------------------
	143	*/
	144	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	145	#define PCI_HOST_FORCE 1 /* configure as pci host */
	146	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	147
	148	#define CONFIG_PCI /* include pci support */
	149	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	150	#define CONFIG_PCI_PNP /* do pci plug-and-play */
8bde7f77	151	/* resource configuration */
d4629c8c SR	152
	153	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	154
	155	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
	156
	157	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	158	#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	159	#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
	160	#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	161	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	162	#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
	163	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	164	#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	165	#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	166	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
	167
	168	/*-----------------------------------------------------------------------
	169	* IDE/ATA stuff
	170	*-----------------------------------------------------------------------
	171	*/
	172	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	173	#undef CONFIG_IDE_LED /* no led for ide supported */
	174	#define CONFIG_IDE_RESET 1 /* reset for ide supported */
	175
	176	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
	177	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 1 drives per IDE bus */
	178
	179	#define CFG_ATA_BASE_ADDR 0xF0100000
	180	#define CFG_ATA_IDE0_OFFSET 0x0000
	181
	182	#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
	183	#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
	184	#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
	185
	186	/*-----------------------------------------------------------------------
	187	* Start addresses for the final memory configuration
	188	* (Set up by the startup code)
	189	* Please note that CFG_SDRAM_BASE _must_ start at 0
	190	*/
	191	#define CFG_SDRAM_BASE 0x00000000
	192	#define CFG_FLASH_BASE 0xFFFC0000
	193	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	194	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
53cf9435	195	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
d4629c8c SR	196
	197	/*
	198	* For booting Linux, the board info and command line data
	199	* have to be in the first 8 MB of memory, since this is
	200	* the maximum mapped by the Linux kernel during initialization.
	201	*/
	202	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	203	/*-----------------------------------------------------------------------
	204	* FLASH organization
	205	*/
	206	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	207	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	208
	209	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	210	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	211
	212	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	213	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	214	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
	215	/*
	216	* The following defines are added for buggy IOP480 byte interface.
	217	* All other boards should use the standard values (CPCI405 etc.)
	218	*/
	219	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	220	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	221	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
	222
	223	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	224
	225	#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
	226	#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
	227
	228	#if 0 /* Use NVRAM for environment variables */
	229	/*-----------------------------------------------------------------------
	230	* NVRAM organization
	231	*/
	232	#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
	233	#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
	234	#define CFG_ENV_ADDR \
	235	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */
	236
	237	#else /* Use EEPROM for environment variables */
	238
	239	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	240	#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
	241	#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/
8bde7f77	242	/* total size of a CAT24WC08 is 1024 bytes */
d4629c8c SR	243	#endif
	244
	245	#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
	246	#define CFG_NVRAM_SIZE (321024) / NVRAM size */
	247	#define CFG_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
	248
	249	/*-----------------------------------------------------------------------
	250	* I2C EEPROM (CAT24WC08) for environment
	251	*/
	252	#define CONFIG_HARD_I2C /* I2c with hardware support */
	253	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	254	#define CFG_I2C_SLAVE 0x7F
	255
	256	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
	257	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	258	/* mask of address bits that overflow into the "EEPROM chip address" */
	259	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	260	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	261	/* 16 byte page write mode using*/
	262	/* last 4 bits of the address */
	263	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	264	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	265
	266	/*-----------------------------------------------------------------------
	267	* Cache Configuration
	268	*/
	269	#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
8bde7f77	270	/* have only 8kB, 16kB is save here */
d4629c8c SR	271	#define CFG_CACHELINE_SIZE 32 /* ... */
	272	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	273	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	274	#endif
	275
	276	/*
	277	* Init Memory Controller:
	278	*
	279	* BR0/1 and OR0/1 (FLASH)
	280	*/
	281
	282	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
	283	#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
	284
	285	/*-----------------------------------------------------------------------
	286	* External Bus Controller (EBC) Setup
	287	*/
	288
	289	/* Memory Bank 0 (Flash Bank 0) initialization */
	290	#define CFG_EBC_PB0AP 0x92015480
	291	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
	292
	293	/* Memory Bank 1 (Flash Bank 1) initialization */
	294	#define CFG_EBC_PB1AP 0x92015480
	295	#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
	296
	297	/* Memory Bank 2 (CAN0, 1) initialization */
	298	#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	299	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
	300	#define CFG_LED_ADDR 0xF0000380
	301
	302	/* Memory Bank 3 (CompactFlash IDE) initialization */
	303	#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	304	#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
	305
	306	/* Memory Bank 4 (NVRAM/RTC) initialization */
	307	/#define CFG_EBC_PB4AP 0x01805280 / TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
	308	#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
	309	#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
	310
	311	/* Memory Bank 5 (optional Quart) initialization */
	312	#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
	313	#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
	314
	315	/* Memory Bank 6 (FPGA internal) initialization */
	316	#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	317	#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
	318	#define CFG_FPGA_BASE_ADDR 0xF0400000
	319
	320	/*-----------------------------------------------------------------------
	321	* FPGA stuff
	322	*/
	323	/* FPGA internal regs */
	324	#define CFG_FPGA_MODE 0x00
	325	#define CFG_FPGA_STATUS 0x02
	326	#define CFG_FPGA_TS 0x04
	327	#define CFG_FPGA_TS_LOW 0x06
	328	#define CFG_FPGA_TS_CAP0 0x10
	329	#define CFG_FPGA_TS_CAP0_LOW 0x12
	330	#define CFG_FPGA_TS_CAP1 0x14
	331	#define CFG_FPGA_TS_CAP1_LOW 0x16
	332	#define CFG_FPGA_TS_CAP2 0x18
	333	#define CFG_FPGA_TS_CAP2_LOW 0x1a
	334	#define CFG_FPGA_TS_CAP3 0x1c
335	#define CFG_FPGA_TS_CAP3_LOW 0x1e
336
337	/* FPGA Mode Reg */
338	#define CFG_FPGA_MODE_CF_RESET 0x0001
339	#define CFG_FPGA_MODE_DUART_RESET 0x0002
340	#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
341	#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
342	#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
343	#define CFG_FPGA_MODE_TS_CLEAR 0x2000
344
345	/* FPGA Status Reg */
346	#define CFG_FPGA_STATUS_DIP0 0x0001
347	#define CFG_FPGA_STATUS_DIP1 0x0002
348	#define CFG_FPGA_STATUS_DIP2 0x0004
349	#define CFG_FPGA_STATUS_FLASH 0x0008
350	#define CFG_FPGA_STATUS_TS_IRQ 0x1000
351
352	#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
53cf9435	353	#define CFG_FPGA_MAX_SIZE 1281024 / 128kByte is enough for XC2S30 */
d4629c8c SR	354
	355	/* FPGA program pin configuration */
	356	#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	357	#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	358	#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	359	#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
	360	#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
	361
	362	/*-----------------------------------------------------------------------
	363	* Definitions for initial stack pointer and data area (in data cache)
	364	*/
	365	#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
	366
	367	#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
	368	#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
	369	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	370	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	371	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	372
	373
	374	/*
	375	* Internal Definitions
	376	*
	377	* Boot Flags
	378	*/
	379	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	380	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	381
	382	#endif /* __CONFIG_H */