projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 384cc687 WD |
1 | /* |
| 2 | * (C) Copyright 2001-2005 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 31 | /* | |
| 32 | * High Level Configuration Options | |
| 33 | * (easy to change) | |
| 34 | */ | |
| 35 | ||
| 36 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
| 37 | #define CONFIG_CPU87 1 /* ...on a CPU87 board */ | |
| 38 | #define CONFIG_PCI | |
| 9c4c5ae3 | 39 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
| 384cc687 WD |
40 | |
| 41 | /* | |
| 42 | * select serial console configuration | |
| 43 | * | |
| 44 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
| 45 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
| 46 | * for SCC). | |
| 47 | * | |
| 48 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
| 49 | * defined elsewhere (for example, on the cogent platform, there are serial | |
| 50 | * ports on the motherboard which are used for the serial console - see | |
| 51 | * cogent/cma101/serial.[ch]). | |
| 52 | */ | |
| 53 | #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
| 54 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
| 55 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
| 56 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
| 57 | ||
| 58 | #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) | |
| 59 | #define CONFIG_BAUDRATE 230400 | |
| 60 | #else | |
| 61 | #define CONFIG_BAUDRATE 9600 | |
| 62 | #endif | |
| 63 | ||
| 64 | /* | |
| 65 | * select ethernet configuration | |
| 66 | * | |
| 67 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
| 68 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
| 69 | * for FCC) | |
| 70 | * | |
| 71 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
| 639221c7 | 72 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
| 384cc687 WD |
73 | */ |
| 74 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
| 75 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
| 76 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
| 77 | #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ | |
| 78 | ||
| 79 | #define CONFIG_HAS_ETH1 1 | |
| 80 | #define CONFIG_HAS_ETH2 1 | |
| 81 | ||
| 82 | #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) | |
| 83 | ||
| 84 | /* | |
| 85 | * - Rx-CLK is CLK11 | |
| 86 | * - Tx-CLK is CLK12 | |
| 87 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
| 88 | * - Enable Full Duplex in FSMR | |
| 89 | */ | |
| 90 | # define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) | |
| 91 | # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) | |
| 92 | # define CFG_CPMFCR_RAMTYPE 0 | |
| 93 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
| 94 | ||
| 95 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
| 96 | ||
| 97 | /* | |
| 98 | * - Rx-CLK is CLK13 | |
| 99 | * - Tx-CLK is CLK14 | |
| 100 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
| 101 | * - Enable Full Duplex in FSMR | |
| 102 | */ | |
| 103 | # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) | |
| 104 | # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
| 105 | # define CFG_CPMFCR_RAMTYPE 0 | |
| 106 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
| 107 | ||
| 108 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ | |
| 109 | ||
| 110 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
| 111 | #define CONFIG_8260_CLKIN 100000000 /* in Hz */ | |
| 112 | ||
| 113 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 114 | ||
| 384cc687 WD |
115 | #define CONFIG_PREBOOT \ |
| 116 | "echo; " \ | |
| 32bf3d14 | 117 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \ |
| 384cc687 WD |
118 | "echo" |
| 119 | ||
| 120 | #undef CONFIG_BOOTARGS | |
| 121 | #define CONFIG_BOOTCOMMAND \ | |
| 122 | "bootp; " \ | |
| fe126d8b WD |
123 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
| 124 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
| 384cc687 WD |
125 | "bootm" |
| 126 | ||
| 127 | /*----------------------------------------------------------------------- | |
| 128 | * I2C/EEPROM/RTC configuration | |
| 129 | */ | |
| 130 | #define CONFIG_SOFT_I2C /* Software I2C support enabled */ | |
| 131 | ||
| 132 | # define CFG_I2C_SPEED 50000 | |
| 133 | # define CFG_I2C_SLAVE 0xFE | |
| 134 | /* | |
| 135 | * Software (bit-bang) I2C driver configuration | |
| 136 | */ | |
| 137 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
| 138 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
| 139 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
| 140 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
| 141 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
| 142 | else iop->pdat &= ~0x00010000 | |
| 143 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
| 144 | else iop->pdat &= ~0x00020000 | |
| 145 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
| 146 | ||
| 147 | #define CONFIG_RTC_PCF8563 | |
| 148 | #define CFG_I2C_RTC_ADDR 0x51 | |
| 149 | ||
| 150 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 151 | ||
| 152 | /*----------------------------------------------------------------------- | |
| 153 | * Disk-On-Chip configuration | |
| 154 | */ | |
| 155 | ||
| 156 | #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ | |
| 157 | ||
| 158 | #define CFG_DOC_SUPPORT_2000 | |
| 159 | #define CFG_DOC_SUPPORT_MILLENNIUM | |
| 160 | ||
| 161 | /*----------------------------------------------------------------------- | |
| 162 | * Miscellaneous configuration options | |
| 163 | */ | |
| 164 | ||
| 165 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 166 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
| 167 | ||
| 5d2ebe1b JL |
168 | /* |
| 169 | * BOOTP options | |
| 170 | */ | |
| 171 | #define CONFIG_BOOTP_SUBNETMASK | |
| 172 | #define CONFIG_BOOTP_GATEWAY | |
| 173 | #define CONFIG_BOOTP_HOSTNAME | |
| 174 | #define CONFIG_BOOTP_BOOTPATH | |
| 175 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 384cc687 | 176 | |
| 49cf7e8e JL |
177 | |
| 178 | /* | |
| 179 | * Command line configuration. | |
| 180 | */ | |
| 181 | #include <config_cmd_default.h> | |
| 182 | ||
| 183 | #define CONFIG_CMD_BEDBUG | |
| 184 | #define CONFIG_CMD_DATE | |
| 185 | #define CONFIG_CMD_DOC | |
| 186 | #define CONFIG_CMD_EEPROM | |
| 187 | #define CONFIG_CMD_I2C | |
| 188 | ||
| 384cc687 | 189 | #ifdef CONFIG_PCI |
| 49cf7e8e JL |
190 | #define CONFIG_CMD_PCI |
| 191 | #endif | |
| 192 | ||
| 384cc687 | 193 | |
| addb2e16 BS |
194 | #define CFG_NAND_LEGACY |
| 195 | ||
| 384cc687 WD |
196 | /* |
| 197 | * Miscellaneous configurable options | |
| 198 | */ | |
| 199 | #define CFG_LONGHELP /* undef to save memory */ | |
| 200 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 49cf7e8e | 201 | #if defined(CONFIG_CMD_KGDB) |
| 384cc687 WD |
202 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 203 | #else | |
| 204 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 205 | #endif | |
| 206 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 207 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 208 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 209 | ||
| 210 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
| 211 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 212 | ||
| 213 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
| 214 | ||
| 215 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| 216 | ||
| 217 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
| 218 | ||
| 219 | #define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ | |
| 220 | ||
| 221 | #define CONFIG_LOOPW | |
| 222 | ||
| 223 | /* | |
| 224 | * For booting Linux, the board info and command line data | |
| 225 | * have to be in the first 8 MB of memory, since this is | |
| 226 | * the maximum mapped by the Linux kernel during initialization. | |
| 227 | */ | |
| 228 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 229 | ||
| 230 | /*----------------------------------------------------------------------- | |
| 231 | * Flash configuration | |
| 232 | */ | |
| 233 | ||
| 234 | #define CFG_BOOTROM_BASE 0xFF800000 | |
| 235 | #define CFG_BOOTROM_SIZE 0x00080000 | |
| 236 | #define CFG_FLASH_BASE 0xFF000000 | |
| 237 | #define CFG_FLASH_SIZE 0x00800000 | |
| 238 | ||
| 239 | /*----------------------------------------------------------------------- | |
| 240 | * FLASH organization | |
| 241 | */ | |
| 242 | #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ | |
| 243 | #define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */ | |
| 244 | ||
| 245 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ | |
| 246 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
| 247 | ||
| 248 | /*----------------------------------------------------------------------- | |
| 249 | * Other areas to be mapped | |
| 250 | */ | |
| 251 | ||
| 252 | /* CS3: Dual ported SRAM */ | |
| 253 | #define CFG_DPSRAM_BASE 0x40000000 | |
| 254 | #define CFG_DPSRAM_SIZE 0x00100000 | |
| 255 | ||
| 256 | /* CS4: DiskOnChip */ | |
| 257 | #define CFG_DOC_BASE 0xF4000000 | |
| 258 | #define CFG_DOC_SIZE 0x00100000 | |
| 259 | ||
| 260 | /* CS5: FDC37C78 controller */ | |
| 261 | #define CFG_FDC37C78_BASE 0xF1000000 | |
| 262 | #define CFG_FDC37C78_SIZE 0x00100000 | |
| 263 | ||
| 264 | /* CS6: Board configuration registers */ | |
| 265 | #define CFG_BCRS_BASE 0xF2000000 | |
| 266 | #define CFG_BCRS_SIZE 0x00010000 | |
| 267 | ||
| 268 | /* CS7: VME Extended Access Range */ | |
| 269 | #define CFG_VMEEAR_BASE 0x60000000 | |
| 270 | #define CFG_VMEEAR_SIZE 0x01000000 | |
| 271 | ||
| 272 | /* CS8: VME Standard Access Range */ | |
| 273 | #define CFG_VMESAR_BASE 0xFE000000 | |
| 274 | #define CFG_VMESAR_SIZE 0x01000000 | |
| 275 | ||
| 276 | /* CS9: VME Short I/O Access Range */ | |
| 277 | #define CFG_VMESIOAR_BASE 0xFD000000 | |
| 278 | #define CFG_VMESIOAR_SIZE 0x01000000 | |
| 279 | ||
| 280 | /*----------------------------------------------------------------------- | |
| 281 | * Hard Reset Configuration Words | |
| 282 | * | |
| 283 | * if you change bits in the HRCW, you must also change the CFG_* | |
| 284 | * defines for the various registers affected by the HRCW e.g. changing | |
| 285 | * HRCW_DPPCxx requires you to also change CFG_SIUMCR. | |
| 286 | */ | |
| 287 | #if defined(CONFIG_BOOT_ROM) | |
| 288 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ | |
| 289 | HRCW_BPS01 | HRCW_CS10PC01) | |
| 290 | #else | |
| 291 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01) | |
| 292 | #endif | |
| 293 | ||
| 294 | /* no slaves so just fill with zeros */ | |
| 295 | #define CFG_HRCW_SLAVE1 0 | |
| 296 | #define CFG_HRCW_SLAVE2 0 | |
| 297 | #define CFG_HRCW_SLAVE3 0 | |
| 298 | #define CFG_HRCW_SLAVE4 0 | |
| 299 | #define CFG_HRCW_SLAVE5 0 | |
| 300 | #define CFG_HRCW_SLAVE6 0 | |
| 301 | #define CFG_HRCW_SLAVE7 0 | |
| 302 | ||
| 303 | /*----------------------------------------------------------------------- | |
| 304 | * Internal Memory Mapped Register | |
| 305 | */ | |
| 306 | #define CFG_IMMR 0xF0000000 | |
| 307 | ||
| 308 | /*----------------------------------------------------------------------- | |
| 309 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 310 | */ | |
| 311 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
| 312 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
| 313 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ | |
| 314 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 315 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 316 | ||
| 317 | /*----------------------------------------------------------------------- | |
| 318 | * Start addresses for the final memory configuration | |
| 319 | * (Set up by the startup code) | |
| 320 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 321 | * | |
| 322 | * 60x SDRAM is mapped at CFG_SDRAM_BASE. | |
| 323 | */ | |
| 324 | #define CFG_SDRAM_BASE 0x00000000 | |
| 325 | #define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
| 326 | #define CFG_MONITOR_BASE TEXT_BASE | |
| 327 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 328 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
| 329 | ||
| 330 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
| 331 | # define CFG_RAMBOOT | |
| 332 | #endif | |
| 333 | ||
| 334 | #ifdef CONFIG_PCI | |
| 335 | #define CONFIG_PCI_PNP | |
| 336 | #define CONFIG_EEPRO100 | |
| 337 | #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ | |
| 338 | #endif | |
| 339 | ||
| 340 | #if 0 | |
| 341 | /* environment is in Flash */ | |
| 342 | #define CFG_ENV_IS_IN_FLASH 1 | |
| 343 | #ifdef CONFIG_BOOT_ROM | |
| 344 | # define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000) | |
| 345 | # define CFG_ENV_SIZE 0x10000 | |
| 346 | # define CFG_ENV_SECT_SIZE 0x10000 | |
| 347 | #endif | |
| 348 | #else | |
| 349 | /* environment is in EEPROM */ | |
| 350 | #define CFG_ENV_IS_IN_EEPROM 1 | |
| 351 | #define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ | |
| 352 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
| 353 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
| 354 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 | |
| 355 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 | |
| 356 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
| 357 | #define CFG_ENV_OFFSET 512 | |
| 358 | #define CFG_ENV_SIZE (2048 - 512) | |
| 359 | #endif | |
| 360 | ||
| 361 | /* | |
| 362 | * Internal Definitions | |
| 363 | * | |
| 364 | * Boot Flags | |
| 365 | */ | |
| 366 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
| 367 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 368 | ||
| 369 | ||
| 370 | /*----------------------------------------------------------------------- | |
| 371 | * Cache Configuration | |
| 372 | */ | |
| 373 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ | |
| 49cf7e8e | 374 | #if defined(CONFIG_CMD_KGDB) |
| 384cc687 WD |
375 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 376 | #endif | |
| 377 | ||
| 378 | /*----------------------------------------------------------------------- | |
| 379 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
| 380 | *----------------------------------------------------------------------- | |
| 381 | * HID0 also contains cache control - initially enable both caches and | |
| 382 | * invalidate contents, then the final state leaves only the instruction | |
| 383 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
| 384 | * but Soft reset does not. | |
| 385 | * | |
| 386 | * HID1 has only read-only information - nothing to set. | |
| 387 | */ | |
| 388 | #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ | |
| 389 | HID0_DCI|HID0_IFEM|HID0_ABE) | |
| 390 | #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) | |
| 391 | #define CFG_HID2 0 | |
| 392 | ||
| 393 | /*----------------------------------------------------------------------- | |
| 394 | * RMR - Reset Mode Register 5-5 | |
| 395 | *----------------------------------------------------------------------- | |
| 396 | * turn on Checkstop Reset Enable | |
| 397 | */ | |
| 398 | #define CFG_RMR RMR_CSRE | |
| 399 | ||
| 400 | /*----------------------------------------------------------------------- | |
| 401 | * BCR - Bus Configuration 4-25 | |
| 402 | *----------------------------------------------------------------------- | |
| 403 | */ | |
| 404 | #define BCR_APD01 0x10000000 | |
| 405 | #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ | |
| 406 | ||
| 407 | /*----------------------------------------------------------------------- | |
| 408 | * SIUMCR - SIU Module Configuration 4-31 | |
| 409 | *----------------------------------------------------------------------- | |
| 410 | */ | |
| 411 | #define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\ | |
| 412 | SIUMCR_CS10PC01|SIUMCR_BCTLC10) | |
| 413 | ||
| 414 | /*----------------------------------------------------------------------- | |
| 415 | * SYPCR - System Protection Control 4-35 | |
| 416 | * SYPCR can only be written once after reset! | |
| 417 | *----------------------------------------------------------------------- | |
| 418 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
| 419 | */ | |
| 420 | #if defined(CONFIG_WATCHDOG) | |
| 421 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
| 422 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) | |
| 423 | #else | |
| 424 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
| 425 | SYPCR_SWRI|SYPCR_SWP) | |
| 426 | #endif /* CONFIG_WATCHDOG */ | |
| 427 | ||
| 428 | /*----------------------------------------------------------------------- | |
| 429 | * TMCNTSC - Time Counter Status and Control 4-40 | |
| 430 | *----------------------------------------------------------------------- | |
| 431 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
| 432 | * and enable Time Counter | |
| 433 | */ | |
| 434 | #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) | |
| 435 | ||
| 436 | /*----------------------------------------------------------------------- | |
| 437 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
| 438 | *----------------------------------------------------------------------- | |
| 439 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
| 440 | * Periodic timer | |
| 441 | */ | |
| 442 | #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) | |
| 443 | ||
| 444 | /*----------------------------------------------------------------------- | |
| 445 | * SCCR - System Clock Control 9-8 | |
| 446 | *----------------------------------------------------------------------- | |
| 447 | * Ensure DFBRG is Divide by 16 | |
| 448 | */ | |
| 449 | #define CFG_SCCR SCCR_DFBRG01 | |
| 450 | ||
| 451 | /*----------------------------------------------------------------------- | |
| 452 | * RCCR - RISC Controller Configuration 13-7 | |
| 453 | *----------------------------------------------------------------------- | |
| 454 | */ | |
| 455 | #define CFG_RCCR 0 | |
| 456 | ||
| 457 | #define CFG_MIN_AM_MASK 0xC0000000 | |
| 458 | ||
| 459 | /* | |
| fd27996d | 460 | * we use the same values for 32 MB, 128 MB and 256 MB SDRAM |
| 384cc687 WD |
461 | * refresh rate = 7.68 uS (100 MHz Bus Clock) |
| 462 | */ | |
| 463 | ||
| 464 | /*----------------------------------------------------------------------- | |
| 465 | * MPTPR - Memory Refresh Timer Prescaler Register 10-18 | |
| 466 | *----------------------------------------------------------------------- | |
| 467 | */ | |
| 468 | #define CFG_MPTPR 0x2000 | |
| 469 | ||
| 470 | /*----------------------------------------------------------------------- | |
| 471 | * PSRT - Refresh Timer Register 10-16 | |
| 472 | *----------------------------------------------------------------------- | |
| 473 | */ | |
| 474 | #define CFG_PSRT 0x16 | |
| 475 | ||
| 476 | /*----------------------------------------------------------------------- | |
| 477 | * PSRT - SDRAM Mode Register 10-10 | |
| 478 | *----------------------------------------------------------------------- | |
| 479 | */ | |
| 480 | ||
| 481 | /* SDRAM initialization values for 8-column chips | |
| 482 | */ | |
| 483 | #define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ | |
| 484 | ORxS_BPD_4 |\ | |
| 485 | ORxS_ROWST_PBI0_A9 |\ | |
| 486 | ORxS_NUMR_12) | |
| 487 | ||
| 488 | #define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ | |
| 489 | PSDMR_BSMA_A14_A16 |\ | |
| 490 | PSDMR_SDA10_PBI0_A10 |\ | |
| 491 | PSDMR_RFRC_7_CLK |\ | |
| 492 | PSDMR_PRETOACT_2W |\ | |
| 493 | PSDMR_ACTTORW_2W |\ | |
| 494 | PSDMR_LDOTOPRE_1C |\ | |
| 495 | PSDMR_WRC_1C |\ | |
| 496 | PSDMR_CL_2) | |
| 497 | ||
| 498 | /* SDRAM initialization values for 9-column chips | |
| 499 | */ | |
| 500 | #define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ | |
| 501 | ORxS_BPD_4 |\ | |
| 502 | ORxS_ROWST_PBI0_A7 |\ | |
| 503 | ORxS_NUMR_13) | |
| 504 | ||
| 505 | #define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ | |
| 506 | PSDMR_BSMA_A13_A15 |\ | |
| 507 | PSDMR_SDA10_PBI0_A9 |\ | |
| 508 | PSDMR_RFRC_7_CLK |\ | |
| 509 | PSDMR_PRETOACT_2W |\ | |
| 510 | PSDMR_ACTTORW_2W |\ | |
| 511 | PSDMR_LDOTOPRE_1C |\ | |
| 512 | PSDMR_WRC_1C |\ | |
| 513 | PSDMR_CL_2) | |
| 514 | ||
| fd27996d WD |
515 | /* SDRAM initialization values for 10-column chips |
| 516 | */ | |
| 517 | #define CFG_OR2_10COL (CFG_MIN_AM_MASK |\ | |
| 518 | ORxS_BPD_4 |\ | |
| 519 | ORxS_ROWST_PBI1_A4 |\ | |
| 520 | ORxS_NUMR_13) | |
| 521 | ||
| 522 | #define CFG_PSDMR_10COL (PSDMR_PBI |\ | |
| 523 | PSDMR_SDAM_A17_IS_A5 |\ | |
| 524 | PSDMR_BSMA_A13_A15 |\ | |
| 525 | PSDMR_SDA10_PBI1_A6 |\ | |
| 526 | PSDMR_RFRC_7_CLK |\ | |
| 527 | PSDMR_PRETOACT_2W |\ | |
| 528 | PSDMR_ACTTORW_2W |\ | |
| 529 | PSDMR_LDOTOPRE_1C |\ | |
| 530 | PSDMR_WRC_1C |\ | |
| 531 | PSDMR_CL_2) | |
| 16850919 | 532 | |
| 384cc687 WD |
533 | /* |
| 534 | * Init Memory Controller: | |
| 535 | * | |
| 536 | * Bank Bus Machine PortSz Device | |
| 537 | * ---- --- ------- ------ ------ | |
| 538 | * 0 60x GPCM 8 bit Boot ROM | |
| 539 | * 1 60x GPCM 64 bit FLASH | |
| 540 | * 2 60x SDRAM 64 bit SDRAM | |
| 541 | * | |
| 542 | */ | |
| 543 | ||
| 544 | #define CFG_MRS_OFFS 0x00000000 | |
| 545 | ||
| 546 | #ifdef CONFIG_BOOT_ROM | |
| 547 | /* Bank 0 - Boot ROM | |
| 548 | */ | |
| 549 | #define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ | |
| 550 | BRx_PS_8 |\ | |
| 551 | BRx_MS_GPCM_P |\ | |
| 552 | BRx_V) | |
| 553 | ||
| 554 | #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ | |
| 555 | ORxG_CSNT |\ | |
| 556 | ORxG_ACS_DIV1 |\ | |
| 557 | ORxG_SCY_5_CLK |\ | |
| 558 | ORxU_EHTR_8IDLE) | |
| 559 | ||
| 560 | /* Bank 1 - FLASH | |
| 561 | */ | |
| 562 | #define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ | |
| 563 | BRx_PS_64 |\ | |
| 564 | BRx_MS_GPCM_P |\ | |
| 565 | BRx_V) | |
| 566 | ||
| 567 | #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ | |
| 568 | ORxG_CSNT |\ | |
| 569 | ORxG_ACS_DIV1 |\ | |
| 570 | ORxG_SCY_5_CLK |\ | |
| 571 | ORxU_EHTR_8IDLE) | |
| 572 | ||
| 573 | #else /* CONFIG_BOOT_ROM */ | |
| 574 | /* Bank 0 - FLASH | |
| 575 | */ | |
| 576 | #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ | |
| 577 | BRx_PS_64 |\ | |
| 578 | BRx_MS_GPCM_P |\ | |
| 579 | BRx_V) | |
| 580 | ||
| 581 | #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ | |
| 582 | ORxG_CSNT |\ | |
| 583 | ORxG_ACS_DIV1 |\ | |
| 584 | ORxG_SCY_5_CLK |\ | |
| 585 | ORxU_EHTR_8IDLE) | |
| 586 | ||
| 587 | /* Bank 1 - Boot ROM | |
| 588 | */ | |
| 589 | #define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ | |
| 590 | BRx_PS_8 |\ | |
| 591 | BRx_MS_GPCM_P |\ | |
| 592 | BRx_V) | |
| 593 | ||
| 594 | #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ | |
| 595 | ORxG_CSNT |\ | |
| 596 | ORxG_ACS_DIV1 |\ | |
| 597 | ORxG_SCY_5_CLK |\ | |
| 598 | ORxU_EHTR_8IDLE) | |
| 599 | ||
| 600 | #endif /* CONFIG_BOOT_ROM */ | |
| 601 | ||
| 602 | ||
| 603 | /* Bank 2 - 60x bus SDRAM | |
| 604 | */ | |
| 605 | #ifndef CFG_RAMBOOT | |
| 606 | #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ | |
| 607 | BRx_PS_64 |\ | |
| 608 | BRx_MS_SDRAM_P |\ | |
| 609 | BRx_V) | |
| 610 | ||
| fd27996d | 611 | #define CFG_OR2_PRELIM CFG_OR2_8COL |
| 384cc687 | 612 | |
| fd27996d | 613 | #define CFG_PSDMR CFG_PSDMR_8COL |
| 384cc687 WD |
614 | #endif /* CFG_RAMBOOT */ |
| 615 | ||
| 616 | /* Bank 3 - Dual Ported SRAM | |
| 617 | */ | |
| 618 | #define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\ | |
| 619 | BRx_PS_16 |\ | |
| 620 | BRx_MS_GPCM_P |\ | |
| 621 | BRx_V) | |
| 622 | ||
| 623 | #define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\ | |
| 624 | ORxG_CSNT |\ | |
| 625 | ORxG_ACS_DIV1 |\ | |
| 626 | ORxG_SCY_7_CLK |\ | |
| 627 | ORxG_SETA) | |
| 628 | ||
| 629 | /* Bank 4 - DiskOnChip | |
| 630 | */ | |
| 631 | #define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ | |
| 632 | BRx_PS_8 |\ | |
| 633 | BRx_MS_GPCM_P |\ | |
| 634 | BRx_V) | |
| 635 | ||
| 636 | #define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ | |
| 637 | ORxG_CSNT |\ | |
| 638 | ORxG_ACS_DIV2 |\ | |
| 639 | ORxG_SCY_9_CLK |\ | |
| 640 | ORxU_EHTR_8IDLE) | |
| 641 | ||
| 642 | /* Bank 5 - FDC37C78 controller | |
| 643 | */ | |
| 644 | #define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\ | |
| 645 | BRx_PS_8 |\ | |
| 646 | BRx_MS_GPCM_P |\ | |
| 647 | BRx_V) | |
| 648 | ||
| 649 | #define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\ | |
| 650 | ORxG_ACS_DIV2 |\ | |
| 651 | ORxG_SCY_10_CLK |\ | |
| 652 | ORxU_EHTR_8IDLE) | |
| 653 | ||
| 654 | /* Bank 6 - Board control registers | |
| 655 | */ | |
| 656 | #define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\ | |
| 657 | BRx_PS_8 |\ | |
| 658 | BRx_MS_GPCM_P |\ | |
| 659 | BRx_V) | |
| 660 | ||
| 661 | #define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\ | |
| 662 | ORxG_CSNT |\ | |
| 663 | ORxG_SCY_7_CLK) | |
| 664 | ||
| 665 | /* Bank 7 - VME Extended Access Range | |
| 666 | */ | |
| 667 | #define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\ | |
| 668 | BRx_PS_32 |\ | |
| 669 | BRx_MS_GPCM_P |\ | |
| 670 | BRx_V) | |
| 671 | ||
| 672 | #define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\ | |
| 673 | ORxG_CSNT |\ | |
| 674 | ORxG_ACS_DIV1 |\ | |
| 675 | ORxG_SCY_7_CLK |\ | |
| 676 | ORxG_SETA) | |
| 677 | ||
| 678 | /* Bank 8 - VME Standard Access Range | |
| 679 | */ | |
| 680 | #define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\ | |
| 681 | BRx_PS_16 |\ | |
| 682 | BRx_MS_GPCM_P |\ | |
| 683 | BRx_V) | |
| 684 | ||
| 685 | #define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\ | |
| 686 | ORxG_CSNT |\ | |
| 687 | ORxG_ACS_DIV1 |\ | |
| 688 | ORxG_SCY_7_CLK |\ | |
| 689 | ORxG_SETA) | |
| 690 | ||
| 691 | /* Bank 9 - VME Short I/O Access Range | |
| 692 | */ | |
| 693 | #define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\ | |
| 694 | BRx_PS_16 |\ | |
| 695 | BRx_MS_GPCM_P |\ | |
| 696 | BRx_V) | |
| 697 | ||
| 698 | #define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\ | |
| 699 | ORxG_CSNT |\ | |
| 700 | ORxG_ACS_DIV1 |\ | |
| 701 | ORxG_SCY_7_CLK |\ | |
| 702 | ORxG_SETA) | |
| 703 | ||
| 704 | #endif /* __CONFIG_H */ |