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384cc687 WD |
1 | /* |
2 | * (C) Copyright 2001-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
37 | #define CONFIG_CPU87 1 /* ...on a CPU87 board */ | |
38 | #define CONFIG_PCI | |
9c4c5ae3 | 39 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
384cc687 WD |
40 | |
41 | /* | |
42 | * select serial console configuration | |
43 | * | |
44 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
45 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
46 | * for SCC). | |
47 | * | |
48 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
49 | * defined elsewhere (for example, on the cogent platform, there are serial | |
50 | * ports on the motherboard which are used for the serial console - see | |
51 | * cogent/cma101/serial.[ch]). | |
52 | */ | |
53 | #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
54 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
55 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
56 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
57 | ||
58 | #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) | |
59 | #define CONFIG_BAUDRATE 230400 | |
60 | #else | |
61 | #define CONFIG_BAUDRATE 9600 | |
62 | #endif | |
63 | ||
64 | /* | |
65 | * select ethernet configuration | |
66 | * | |
67 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
68 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
69 | * for FCC) | |
70 | * | |
71 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 72 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
384cc687 WD |
73 | */ |
74 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
75 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
76 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
77 | #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ | |
78 | ||
79 | #define CONFIG_HAS_ETH1 1 | |
80 | #define CONFIG_HAS_ETH2 1 | |
81 | ||
82 | #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) | |
83 | ||
84 | /* | |
85 | * - Rx-CLK is CLK11 | |
86 | * - Tx-CLK is CLK12 | |
87 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
88 | * - Enable Full Duplex in FSMR | |
89 | */ | |
6d0f6bcf JCPV |
90 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) |
91 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) | |
92 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
93 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
384cc687 WD |
94 | |
95 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
96 | ||
97 | /* | |
98 | * - Rx-CLK is CLK13 | |
99 | * - Tx-CLK is CLK14 | |
100 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
101 | * - Enable Full Duplex in FSMR | |
102 | */ | |
6d0f6bcf JCPV |
103 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
104 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
105 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
106 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
384cc687 WD |
107 | |
108 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ | |
109 | ||
110 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
111 | #define CONFIG_8260_CLKIN 100000000 /* in Hz */ | |
112 | ||
113 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
114 | ||
384cc687 WD |
115 | #define CONFIG_PREBOOT \ |
116 | "echo; " \ | |
32bf3d14 | 117 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \ |
384cc687 WD |
118 | "echo" |
119 | ||
120 | #undef CONFIG_BOOTARGS | |
121 | #define CONFIG_BOOTCOMMAND \ | |
122 | "bootp; " \ | |
fe126d8b WD |
123 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
124 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
384cc687 WD |
125 | "bootm" |
126 | ||
127 | /*----------------------------------------------------------------------- | |
128 | * I2C/EEPROM/RTC configuration | |
129 | */ | |
130 | #define CONFIG_SOFT_I2C /* Software I2C support enabled */ | |
131 | ||
6d0f6bcf JCPV |
132 | # define CONFIG_SYS_I2C_SPEED 50000 |
133 | # define CONFIG_SYS_I2C_SLAVE 0xFE | |
384cc687 WD |
134 | /* |
135 | * Software (bit-bang) I2C driver configuration | |
136 | */ | |
137 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
138 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
139 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
140 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
141 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
142 | else iop->pdat &= ~0x00010000 | |
143 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
144 | else iop->pdat &= ~0x00020000 | |
145 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
146 | ||
147 | #define CONFIG_RTC_PCF8563 | |
6d0f6bcf | 148 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
384cc687 WD |
149 | |
150 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
151 | ||
152 | /*----------------------------------------------------------------------- | |
153 | * Disk-On-Chip configuration | |
154 | */ | |
155 | ||
6d0f6bcf | 156 | #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ |
384cc687 | 157 | |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_DOC_SUPPORT_2000 |
159 | #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM | |
384cc687 WD |
160 | |
161 | /*----------------------------------------------------------------------- | |
162 | * Miscellaneous configuration options | |
163 | */ | |
164 | ||
165 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 166 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
384cc687 | 167 | |
5d2ebe1b JL |
168 | /* |
169 | * BOOTP options | |
170 | */ | |
171 | #define CONFIG_BOOTP_SUBNETMASK | |
172 | #define CONFIG_BOOTP_GATEWAY | |
173 | #define CONFIG_BOOTP_HOSTNAME | |
174 | #define CONFIG_BOOTP_BOOTPATH | |
175 | #define CONFIG_BOOTP_BOOTFILESIZE | |
384cc687 | 176 | |
49cf7e8e JL |
177 | |
178 | /* | |
179 | * Command line configuration. | |
180 | */ | |
181 | #include <config_cmd_default.h> | |
182 | ||
183 | #define CONFIG_CMD_BEDBUG | |
184 | #define CONFIG_CMD_DATE | |
49cf7e8e JL |
185 | #define CONFIG_CMD_EEPROM |
186 | #define CONFIG_CMD_I2C | |
187 | ||
384cc687 | 188 | #ifdef CONFIG_PCI |
49cf7e8e JL |
189 | #define CONFIG_CMD_PCI |
190 | #endif | |
191 | ||
384cc687 WD |
192 | /* |
193 | * Miscellaneous configurable options | |
194 | */ | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
196 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
49cf7e8e | 197 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 198 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
384cc687 | 199 | #else |
6d0f6bcf | 200 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
384cc687 | 201 | #endif |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
203 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
204 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
384cc687 | 205 | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
207 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
384cc687 | 208 | |
6d0f6bcf | 209 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
384cc687 | 210 | |
6d0f6bcf | 211 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
384cc687 | 212 | |
6d0f6bcf | 213 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
384cc687 | 214 | |
6d0f6bcf | 215 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */ |
384cc687 WD |
216 | |
217 | #define CONFIG_LOOPW | |
218 | ||
219 | /* | |
220 | * For booting Linux, the board info and command line data | |
221 | * have to be in the first 8 MB of memory, since this is | |
222 | * the maximum mapped by the Linux kernel during initialization. | |
223 | */ | |
6d0f6bcf | 224 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
384cc687 WD |
225 | |
226 | /*----------------------------------------------------------------------- | |
227 | * Flash configuration | |
228 | */ | |
229 | ||
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_BOOTROM_BASE 0xFF800000 |
231 | #define CONFIG_SYS_BOOTROM_SIZE 0x00080000 | |
232 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
233 | #define CONFIG_SYS_FLASH_SIZE 0x00800000 | |
384cc687 WD |
234 | |
235 | /*----------------------------------------------------------------------- | |
236 | * FLASH organization | |
237 | */ | |
6d0f6bcf JCPV |
238 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ |
239 | #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ | |
384cc687 | 240 | |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
242 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
384cc687 WD |
243 | |
244 | /*----------------------------------------------------------------------- | |
245 | * Other areas to be mapped | |
246 | */ | |
247 | ||
248 | /* CS3: Dual ported SRAM */ | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_DPSRAM_BASE 0x40000000 |
250 | #define CONFIG_SYS_DPSRAM_SIZE 0x00100000 | |
384cc687 WD |
251 | |
252 | /* CS4: DiskOnChip */ | |
6d0f6bcf JCPV |
253 | #define CONFIG_SYS_DOC_BASE 0xF4000000 |
254 | #define CONFIG_SYS_DOC_SIZE 0x00100000 | |
384cc687 WD |
255 | |
256 | /* CS5: FDC37C78 controller */ | |
6d0f6bcf JCPV |
257 | #define CONFIG_SYS_FDC37C78_BASE 0xF1000000 |
258 | #define CONFIG_SYS_FDC37C78_SIZE 0x00100000 | |
384cc687 WD |
259 | |
260 | /* CS6: Board configuration registers */ | |
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_BCRS_BASE 0xF2000000 |
262 | #define CONFIG_SYS_BCRS_SIZE 0x00010000 | |
384cc687 WD |
263 | |
264 | /* CS7: VME Extended Access Range */ | |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_VMEEAR_BASE 0x60000000 |
266 | #define CONFIG_SYS_VMEEAR_SIZE 0x01000000 | |
384cc687 WD |
267 | |
268 | /* CS8: VME Standard Access Range */ | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_VMESAR_BASE 0xFE000000 |
270 | #define CONFIG_SYS_VMESAR_SIZE 0x01000000 | |
384cc687 WD |
271 | |
272 | /* CS9: VME Short I/O Access Range */ | |
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_VMESIOAR_BASE 0xFD000000 |
274 | #define CONFIG_SYS_VMESIOAR_SIZE 0x01000000 | |
384cc687 WD |
275 | |
276 | /*----------------------------------------------------------------------- | |
277 | * Hard Reset Configuration Words | |
278 | * | |
6d0f6bcf | 279 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
384cc687 | 280 | * defines for the various registers affected by the HRCW e.g. changing |
6d0f6bcf | 281 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
384cc687 WD |
282 | */ |
283 | #if defined(CONFIG_BOOT_ROM) | |
6d0f6bcf | 284 | #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ |
384cc687 WD |
285 | HRCW_BPS01 | HRCW_CS10PC01) |
286 | #else | |
6d0f6bcf | 287 | #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01) |
384cc687 WD |
288 | #endif |
289 | ||
290 | /* no slaves so just fill with zeros */ | |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
292 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
293 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
294 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
295 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
296 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
297 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
384cc687 WD |
298 | |
299 | /*----------------------------------------------------------------------- | |
300 | * Internal Memory Mapped Register | |
301 | */ | |
6d0f6bcf | 302 | #define CONFIG_SYS_IMMR 0xF0000000 |
384cc687 WD |
303 | |
304 | /*----------------------------------------------------------------------- | |
305 | * Definitions for initial stack pointer and data area (in DPRAM) | |
306 | */ | |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
308 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
309 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ | |
310 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
311 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
384cc687 WD |
312 | |
313 | /*----------------------------------------------------------------------- | |
314 | * Start addresses for the final memory configuration | |
315 | * (Set up by the startup code) | |
6d0f6bcf | 316 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
384cc687 | 317 | * |
6d0f6bcf | 318 | * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE. |
384cc687 | 319 | */ |
6d0f6bcf JCPV |
320 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
321 | #define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
322 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
323 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
324 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
384cc687 | 325 | |
6d0f6bcf JCPV |
326 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
327 | # define CONFIG_SYS_RAMBOOT | |
384cc687 WD |
328 | #endif |
329 | ||
330 | #ifdef CONFIG_PCI | |
331 | #define CONFIG_PCI_PNP | |
332 | #define CONFIG_EEPRO100 | |
6d0f6bcf | 333 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
384cc687 WD |
334 | #endif |
335 | ||
336 | #if 0 | |
337 | /* environment is in Flash */ | |
5a1aceb0 | 338 | #define CONFIG_ENV_IS_IN_FLASH 1 |
384cc687 | 339 | #ifdef CONFIG_BOOT_ROM |
6d0f6bcf | 340 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x70000) |
0e8d1586 JCPV |
341 | # define CONFIG_ENV_SIZE 0x10000 |
342 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
384cc687 WD |
343 | #endif |
344 | #else | |
345 | /* environment is in EEPROM */ | |
bb1f8b4f | 346 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ |
348 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
384cc687 | 349 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
350 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
351 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
352 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
0e8d1586 JCPV |
353 | #define CONFIG_ENV_OFFSET 512 |
354 | #define CONFIG_ENV_SIZE (2048 - 512) | |
384cc687 WD |
355 | #endif |
356 | ||
357 | /* | |
358 | * Internal Definitions | |
359 | * | |
360 | * Boot Flags | |
361 | */ | |
362 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
363 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
364 | ||
365 | ||
366 | /*----------------------------------------------------------------------- | |
367 | * Cache Configuration | |
368 | */ | |
6d0f6bcf | 369 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
49cf7e8e | 370 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 371 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
384cc687 WD |
372 | #endif |
373 | ||
374 | /*----------------------------------------------------------------------- | |
375 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
376 | *----------------------------------------------------------------------- | |
377 | * HID0 also contains cache control - initially enable both caches and | |
378 | * invalidate contents, then the final state leaves only the instruction | |
379 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
380 | * but Soft reset does not. | |
381 | * | |
382 | * HID1 has only read-only information - nothing to set. | |
383 | */ | |
6d0f6bcf | 384 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ |
384cc687 | 385 | HID0_DCI|HID0_IFEM|HID0_ABE) |
6d0f6bcf JCPV |
386 | #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) |
387 | #define CONFIG_SYS_HID2 0 | |
384cc687 WD |
388 | |
389 | /*----------------------------------------------------------------------- | |
390 | * RMR - Reset Mode Register 5-5 | |
391 | *----------------------------------------------------------------------- | |
392 | * turn on Checkstop Reset Enable | |
393 | */ | |
6d0f6bcf | 394 | #define CONFIG_SYS_RMR RMR_CSRE |
384cc687 WD |
395 | |
396 | /*----------------------------------------------------------------------- | |
397 | * BCR - Bus Configuration 4-25 | |
398 | *----------------------------------------------------------------------- | |
399 | */ | |
400 | #define BCR_APD01 0x10000000 | |
6d0f6bcf | 401 | #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
384cc687 WD |
402 | |
403 | /*----------------------------------------------------------------------- | |
404 | * SIUMCR - SIU Module Configuration 4-31 | |
405 | *----------------------------------------------------------------------- | |
406 | */ | |
6d0f6bcf | 407 | #define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\ |
384cc687 WD |
408 | SIUMCR_CS10PC01|SIUMCR_BCTLC10) |
409 | ||
410 | /*----------------------------------------------------------------------- | |
411 | * SYPCR - System Protection Control 4-35 | |
412 | * SYPCR can only be written once after reset! | |
413 | *----------------------------------------------------------------------- | |
414 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
415 | */ | |
416 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 417 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
384cc687 WD |
418 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
419 | #else | |
6d0f6bcf | 420 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
384cc687 WD |
421 | SYPCR_SWRI|SYPCR_SWP) |
422 | #endif /* CONFIG_WATCHDOG */ | |
423 | ||
424 | /*----------------------------------------------------------------------- | |
425 | * TMCNTSC - Time Counter Status and Control 4-40 | |
426 | *----------------------------------------------------------------------- | |
427 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
428 | * and enable Time Counter | |
429 | */ | |
6d0f6bcf | 430 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
384cc687 WD |
431 | |
432 | /*----------------------------------------------------------------------- | |
433 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
434 | *----------------------------------------------------------------------- | |
435 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
436 | * Periodic timer | |
437 | */ | |
6d0f6bcf | 438 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
384cc687 WD |
439 | |
440 | /*----------------------------------------------------------------------- | |
441 | * SCCR - System Clock Control 9-8 | |
442 | *----------------------------------------------------------------------- | |
443 | * Ensure DFBRG is Divide by 16 | |
444 | */ | |
6d0f6bcf | 445 | #define CONFIG_SYS_SCCR SCCR_DFBRG01 |
384cc687 WD |
446 | |
447 | /*----------------------------------------------------------------------- | |
448 | * RCCR - RISC Controller Configuration 13-7 | |
449 | *----------------------------------------------------------------------- | |
450 | */ | |
6d0f6bcf | 451 | #define CONFIG_SYS_RCCR 0 |
384cc687 | 452 | |
6d0f6bcf | 453 | #define CONFIG_SYS_MIN_AM_MASK 0xC0000000 |
384cc687 WD |
454 | |
455 | /* | |
fd27996d | 456 | * we use the same values for 32 MB, 128 MB and 256 MB SDRAM |
384cc687 WD |
457 | * refresh rate = 7.68 uS (100 MHz Bus Clock) |
458 | */ | |
459 | ||
460 | /*----------------------------------------------------------------------- | |
461 | * MPTPR - Memory Refresh Timer Prescaler Register 10-18 | |
462 | *----------------------------------------------------------------------- | |
463 | */ | |
6d0f6bcf | 464 | #define CONFIG_SYS_MPTPR 0x2000 |
384cc687 WD |
465 | |
466 | /*----------------------------------------------------------------------- | |
467 | * PSRT - Refresh Timer Register 10-16 | |
468 | *----------------------------------------------------------------------- | |
469 | */ | |
6d0f6bcf | 470 | #define CONFIG_SYS_PSRT 0x16 |
384cc687 WD |
471 | |
472 | /*----------------------------------------------------------------------- | |
473 | * PSRT - SDRAM Mode Register 10-10 | |
474 | *----------------------------------------------------------------------- | |
475 | */ | |
476 | ||
477 | /* SDRAM initialization values for 8-column chips | |
478 | */ | |
6d0f6bcf | 479 | #define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ |
384cc687 WD |
480 | ORxS_BPD_4 |\ |
481 | ORxS_ROWST_PBI0_A9 |\ | |
482 | ORxS_NUMR_12) | |
483 | ||
6d0f6bcf | 484 | #define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ |
384cc687 WD |
485 | PSDMR_BSMA_A14_A16 |\ |
486 | PSDMR_SDA10_PBI0_A10 |\ | |
487 | PSDMR_RFRC_7_CLK |\ | |
488 | PSDMR_PRETOACT_2W |\ | |
489 | PSDMR_ACTTORW_2W |\ | |
490 | PSDMR_LDOTOPRE_1C |\ | |
491 | PSDMR_WRC_1C |\ | |
492 | PSDMR_CL_2) | |
493 | ||
494 | /* SDRAM initialization values for 9-column chips | |
495 | */ | |
6d0f6bcf | 496 | #define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ |
384cc687 WD |
497 | ORxS_BPD_4 |\ |
498 | ORxS_ROWST_PBI0_A7 |\ | |
499 | ORxS_NUMR_13) | |
500 | ||
6d0f6bcf | 501 | #define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ |
384cc687 WD |
502 | PSDMR_BSMA_A13_A15 |\ |
503 | PSDMR_SDA10_PBI0_A9 |\ | |
504 | PSDMR_RFRC_7_CLK |\ | |
505 | PSDMR_PRETOACT_2W |\ | |
506 | PSDMR_ACTTORW_2W |\ | |
507 | PSDMR_LDOTOPRE_1C |\ | |
508 | PSDMR_WRC_1C |\ | |
509 | PSDMR_CL_2) | |
510 | ||
fd27996d WD |
511 | /* SDRAM initialization values for 10-column chips |
512 | */ | |
6d0f6bcf | 513 | #define CONFIG_SYS_OR2_10COL (CONFIG_SYS_MIN_AM_MASK |\ |
fd27996d WD |
514 | ORxS_BPD_4 |\ |
515 | ORxS_ROWST_PBI1_A4 |\ | |
516 | ORxS_NUMR_13) | |
517 | ||
6d0f6bcf | 518 | #define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\ |
fd27996d WD |
519 | PSDMR_SDAM_A17_IS_A5 |\ |
520 | PSDMR_BSMA_A13_A15 |\ | |
521 | PSDMR_SDA10_PBI1_A6 |\ | |
522 | PSDMR_RFRC_7_CLK |\ | |
523 | PSDMR_PRETOACT_2W |\ | |
524 | PSDMR_ACTTORW_2W |\ | |
525 | PSDMR_LDOTOPRE_1C |\ | |
526 | PSDMR_WRC_1C |\ | |
527 | PSDMR_CL_2) | |
16850919 | 528 | |
384cc687 WD |
529 | /* |
530 | * Init Memory Controller: | |
531 | * | |
532 | * Bank Bus Machine PortSz Device | |
533 | * ---- --- ------- ------ ------ | |
534 | * 0 60x GPCM 8 bit Boot ROM | |
535 | * 1 60x GPCM 64 bit FLASH | |
536 | * 2 60x SDRAM 64 bit SDRAM | |
537 | * | |
538 | */ | |
539 | ||
6d0f6bcf | 540 | #define CONFIG_SYS_MRS_OFFS 0x00000000 |
384cc687 WD |
541 | |
542 | #ifdef CONFIG_BOOT_ROM | |
543 | /* Bank 0 - Boot ROM | |
544 | */ | |
6d0f6bcf | 545 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ |
384cc687 WD |
546 | BRx_PS_8 |\ |
547 | BRx_MS_GPCM_P |\ | |
548 | BRx_V) | |
549 | ||
6d0f6bcf | 550 | #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ |
384cc687 WD |
551 | ORxG_CSNT |\ |
552 | ORxG_ACS_DIV1 |\ | |
553 | ORxG_SCY_5_CLK |\ | |
554 | ORxU_EHTR_8IDLE) | |
555 | ||
556 | /* Bank 1 - FLASH | |
557 | */ | |
6d0f6bcf | 558 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
384cc687 WD |
559 | BRx_PS_64 |\ |
560 | BRx_MS_GPCM_P |\ | |
561 | BRx_V) | |
562 | ||
6d0f6bcf | 563 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
384cc687 WD |
564 | ORxG_CSNT |\ |
565 | ORxG_ACS_DIV1 |\ | |
566 | ORxG_SCY_5_CLK |\ | |
567 | ORxU_EHTR_8IDLE) | |
568 | ||
569 | #else /* CONFIG_BOOT_ROM */ | |
570 | /* Bank 0 - FLASH | |
571 | */ | |
6d0f6bcf | 572 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
384cc687 WD |
573 | BRx_PS_64 |\ |
574 | BRx_MS_GPCM_P |\ | |
575 | BRx_V) | |
576 | ||
6d0f6bcf | 577 | #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
384cc687 WD |
578 | ORxG_CSNT |\ |
579 | ORxG_ACS_DIV1 |\ | |
580 | ORxG_SCY_5_CLK |\ | |
581 | ORxU_EHTR_8IDLE) | |
582 | ||
583 | /* Bank 1 - Boot ROM | |
584 | */ | |
6d0f6bcf | 585 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ |
384cc687 WD |
586 | BRx_PS_8 |\ |
587 | BRx_MS_GPCM_P |\ | |
588 | BRx_V) | |
589 | ||
6d0f6bcf | 590 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ |
384cc687 WD |
591 | ORxG_CSNT |\ |
592 | ORxG_ACS_DIV1 |\ | |
593 | ORxG_SCY_5_CLK |\ | |
594 | ORxU_EHTR_8IDLE) | |
595 | ||
596 | #endif /* CONFIG_BOOT_ROM */ | |
597 | ||
598 | ||
599 | /* Bank 2 - 60x bus SDRAM | |
600 | */ | |
6d0f6bcf JCPV |
601 | #ifndef CONFIG_SYS_RAMBOOT |
602 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ | |
384cc687 WD |
603 | BRx_PS_64 |\ |
604 | BRx_MS_SDRAM_P |\ | |
605 | BRx_V) | |
606 | ||
6d0f6bcf | 607 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL |
384cc687 | 608 | |
6d0f6bcf JCPV |
609 | #define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL |
610 | #endif /* CONFIG_SYS_RAMBOOT */ | |
384cc687 WD |
611 | |
612 | /* Bank 3 - Dual Ported SRAM | |
613 | */ | |
6d0f6bcf | 614 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\ |
384cc687 WD |
615 | BRx_PS_16 |\ |
616 | BRx_MS_GPCM_P |\ | |
617 | BRx_V) | |
618 | ||
6d0f6bcf | 619 | #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE) |\ |
384cc687 WD |
620 | ORxG_CSNT |\ |
621 | ORxG_ACS_DIV1 |\ | |
622 | ORxG_SCY_7_CLK |\ | |
623 | ORxG_SETA) | |
624 | ||
625 | /* Bank 4 - DiskOnChip | |
626 | */ | |
6d0f6bcf | 627 | #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ |
384cc687 WD |
628 | BRx_PS_8 |\ |
629 | BRx_MS_GPCM_P |\ | |
630 | BRx_V) | |
631 | ||
6d0f6bcf | 632 | #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ |
384cc687 WD |
633 | ORxG_CSNT |\ |
634 | ORxG_ACS_DIV2 |\ | |
635 | ORxG_SCY_9_CLK |\ | |
636 | ORxU_EHTR_8IDLE) | |
637 | ||
638 | /* Bank 5 - FDC37C78 controller | |
639 | */ | |
6d0f6bcf | 640 | #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\ |
384cc687 WD |
641 | BRx_PS_8 |\ |
642 | BRx_MS_GPCM_P |\ | |
643 | BRx_V) | |
644 | ||
6d0f6bcf | 645 | #define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE) |\ |
384cc687 WD |
646 | ORxG_ACS_DIV2 |\ |
647 | ORxG_SCY_10_CLK |\ | |
648 | ORxU_EHTR_8IDLE) | |
649 | ||
650 | /* Bank 6 - Board control registers | |
651 | */ | |
6d0f6bcf | 652 | #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK) |\ |
384cc687 WD |
653 | BRx_PS_8 |\ |
654 | BRx_MS_GPCM_P |\ | |
655 | BRx_V) | |
656 | ||
6d0f6bcf | 657 | #define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE) |\ |
384cc687 WD |
658 | ORxG_CSNT |\ |
659 | ORxG_SCY_7_CLK) | |
660 | ||
661 | /* Bank 7 - VME Extended Access Range | |
662 | */ | |
6d0f6bcf | 663 | #define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\ |
384cc687 WD |
664 | BRx_PS_32 |\ |
665 | BRx_MS_GPCM_P |\ | |
666 | BRx_V) | |
667 | ||
6d0f6bcf | 668 | #define CONFIG_SYS_OR7_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE) |\ |
384cc687 WD |
669 | ORxG_CSNT |\ |
670 | ORxG_ACS_DIV1 |\ | |
671 | ORxG_SCY_7_CLK |\ | |
672 | ORxG_SETA) | |
673 | ||
674 | /* Bank 8 - VME Standard Access Range | |
675 | */ | |
6d0f6bcf | 676 | #define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\ |
384cc687 WD |
677 | BRx_PS_16 |\ |
678 | BRx_MS_GPCM_P |\ | |
679 | BRx_V) | |
680 | ||
6d0f6bcf | 681 | #define CONFIG_SYS_OR8_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE) |\ |
384cc687 WD |
682 | ORxG_CSNT |\ |
683 | ORxG_ACS_DIV1 |\ | |
684 | ORxG_SCY_7_CLK |\ | |
685 | ORxG_SETA) | |
686 | ||
687 | /* Bank 9 - VME Short I/O Access Range | |
688 | */ | |
6d0f6bcf | 689 | #define CONFIG_SYS_BR9_PRELIM ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\ |
384cc687 WD |
690 | BRx_PS_16 |\ |
691 | BRx_MS_GPCM_P |\ | |
692 | BRx_V) | |
693 | ||
6d0f6bcf | 694 | #define CONFIG_SYS_OR9_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE) |\ |
384cc687 WD |
695 | ORxG_CSNT |\ |
696 | ORxG_ACS_DIV1 |\ | |
697 | ORxG_SCY_7_CLK |\ | |
698 | ORxG_SETA) | |
699 | ||
700 | #endif /* __CONFIG_H */ |