[people/ms/u-boot.git] / include / configs / CRAYL1.h

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * David Updegraff, Cray, Inc.  dave@cray.com: our 405 is walnut-lite..
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_CRAYL1
/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU	*/
#define CONFIG_4xx		    1   /* ...member of PPC405 family */

/*
 * Note: I make an "image" from U-Boot itself, which prefixes 0x40
 * bytes of header info, hence start address is thus shifted.
 */
#define	CONFIG_SYS_TEXT_BASE	0xFFFD0040

#define CONFIG_SYS_CLK_FREQ 25000000
#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		    1	/* MII PHY management */
#define	CONFIG_PHY_ADDR		1	/* PHY address; handling of ENET */
#define CONFIG_BOARD_EARLY_INIT_F 1	/* early setup for 405gp */
#define CONFIG_MISC_INIT_R	1	/* so that a misc_init_r() is called */

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
 * keep possible initrd ramdisk decompression out.  This is in k (1024 bytes)
 #define CONFIG_PRAM			16
 */
#define	CONFIG_LOADADDR		0x100000	/* where TFTP images go */
#undef CONFIG_BOOTARGS

/* Bootcmd is overridden by the bootscript in board/cray/L1
 */
#define	CONFIG_SYS_AUTOLOAD		"no"
#define CONFIG_BOOTCOMMAND	"dhcp"

/*
 * ..during experiments..
 #define CONFIG_SERVERIP         10.0.0.1
 #define CONFIG_ETHADDR          00:40:a6:80:14:5
 */
#define CONFIG_HARD_I2C         1		/* hardware support for i2c */
#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
#define CONFIG_SDRAM_BANK0		1
#define CONFIG_SYS_I2C_SPEED		    400000	/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		    0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_IDENT_STRING     "Cray L1"
#define CONFIG_ENV_OVERWRITE     1
#define	CONFIG_SYS_HZ		             1000	/* decrementer freq: 1 ms ticks	*/
#define CONFIG_SYS_HUSH_PARSER			1
#define CONFIG_SOURCE			1


/*
 * Command line configuration.
 */

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SETGETDCR
#define CONFIG_CMD_SOURCE


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_VENDOREX
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * how many time to fail & restart a net-TFTP before giving up & resetting
 * the board hoping that a reset of net interface might help..
 */
#define CONFIG_NET_RESET 5

/*
 * bauds.  Just to make it compile; in our case, I read the base_baud
 * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
 * drives the system clock.
 */
#define CONFIG_SYS_BASE_BAUD       403225
#define CONFIG_SYS_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_PROMPT	"=> "				/* Monitor Command Prompt	*/
#define	CONFIG_SYS_CBSIZE	256				/* Console I/O Buffer Size	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE			/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16				/* max number of command args	*/


#define CONFIG_SYS_LOAD_ADDR		0x100000	/* where to load what we get from TFTP */
#define CONFIG_SYS_TFTP_LOADADDR	CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_EXTBDINFO		1		/* To use extended board_into (bd_t) */
#define CONFIG_SYS_DRAM_TEST		1

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFC00000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE


#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	 1		/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	 64		/* max number of sectors on one chip	*/
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT 500	/* Timeout for Flash Write (in ms)	*/

/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector  */
#define CONFIG_ENV_OFFSET		0x3c8000
#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
#define	CONFIG_ENV_SIZE		0x1000	 /* Total Size of Environment area	*/
#define CONFIG_ENV_SECT_SIZE	0x10000	 /* see README - env sector total size	*/

/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
 * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
 */
#define CONFIG_SYS_SDRAM_SIZE		32		/* megs of ram */
#define CONFIG_SYS_MEMTEST_START	0x2000  /* memtest works from the end of */
									/* the exception vector table */
									/* to the end of the DRAM  */
									/* less monitor and malloc area */
#define CONFIG_SYS_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* 128k for malloc space */
#define CONFIG_SYS_MEM_END_USAGE	( CONFIG_SYS_MONITOR_LEN \
				+ CONFIG_SYS_MALLOC_LEN \
				+ CONFIG_ENV_SECT_SIZE \
				+ CONFIG_SYS_STACK_USAGE )

#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE)
/* END ENVIRONNEMENT FLASH */

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in OnChipMem )
 */
#if 1
/* On Chip Memory location */
#define CONFIG_SYS_TEMP_STACK_OCM	1
#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000

#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
#else
#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	     */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#endif

/*-----------------------------------------------------------------------
 * Definitions for Serial Presence Detect EEPROM address
 */
#define EEPROM_WRITE_ADDRESS 0xA0
#define EEPROM_READ_ADDRESS  0xA1

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b	1	/*
c837dcb1	2	* (C) Copyright 2000-2004
c609719b WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite..
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	#define CONFIG_CRAYL1
	32	/*
	33	* High Level Configuration Options
	34	* (easy to change)
	35	*/
	36
	37	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
	38	#define CONFIG_4xx 1 /* ...member of PPC405 family */
2ae18241 WD	39
	40	/*
	41	* Note: I make an "image" from U-Boot itself, which prefixes 0x40
	42	* bytes of header info, hence start address is thus shifted.
	43	*/
	44	#define CONFIG_SYS_TEXT_BASE 0xFFFD0040
	45
c609719b WD	46	#define CONFIG_SYS_CLK_FREQ 25000000
	47	#define CONFIG_BAUDRATE 9600
	48	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
96e21f86 BW	49
96e21f86 BW	50	#define CONFIG_PPC4xx_EMAC
c609719b WD	51	#define CONFIG_MII 1 /* MII PHY management */
c609719b WD	52	#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */
c837dcb1	53	#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */
c609719b WD	54	#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */
c609719b WD	55
550650dd SR	56	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	57	#define CONFIG_SYS_NS16550
	58	#define CONFIG_SYS_NS16550_SERIAL
	59	#define CONFIG_SYS_NS16550_REG_SIZE 1
	60	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	61
c609719b WD	62	/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
c609719b WD	63	* keep possible initrd ramdisk decompression out. This is in k (1024 bytes)
8bde7f77	64	#define CONFIG_PRAM 16
c609719b	65	*/
7f70e853	66	#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */
c609719b WD	67	#undef CONFIG_BOOTARGS
c609719b WD	68
7f70e853 WD	69	/* Bootcmd is overridden by the bootscript in board/cray/L1
7f70e853 WD	70	*/
6d0f6bcf	71	#define CONFIG_SYS_AUTOLOAD "no"
7f70e853	72	#define CONFIG_BOOTCOMMAND "dhcp"
c609719b	73
8bde7f77	74	/*
c609719b WD	75	* ..during experiments..
c609719b WD	76	#define CONFIG_SERVERIP 10.0.0.1
8bde7f77	77	#define CONFIG_ETHADDR 00:40:a6:80:14:5
c609719b WD	78	*/
c609719b WD	79	#define CONFIG_HARD_I2C 1 /* hardware support for i2c */
d0b0dcaa	80	#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
7f70e853	81	#define CONFIG_SDRAM_BANK0 1
6d0f6bcf JCPV	82	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
	83	#define CONFIG_SYS_I2C_SLAVE 0x7F
	84	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	85	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
c609719b WD	86	#define CONFIG_IDENT_STRING "Cray L1"
c609719b WD	87	#define CONFIG_ENV_OVERWRITE 1
6d0f6bcf JCPV	88	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
6d0f6bcf JCPV	89	#define CONFIG_SYS_HUSH_PARSER 1
74de7aef	90	#define CONFIG_SOURCE 1
c609719b WD	91
c609719b WD	92
49cf7e8e JL	93	/*
	94	* Command line configuration.
	95	*/
	96
74de7aef	97	#define CONFIG_CMD_ASKENV
49cf7e8e	98	#define CONFIG_CMD_BDI
49cf7e8e	99	#define CONFIG_CMD_CONSOLE
74de7aef WD	100	#define CONFIG_CMD_DATE
	101	#define CONFIG_CMD_DHCP
	102	#define CONFIG_CMD_DIAG
49cf7e8e	103	#define CONFIG_CMD_ECHO
74de7aef WD	104	#define CONFIG_CMD_EEPROM
	105	#define CONFIG_CMD_FLASH
	106	#define CONFIG_CMD_I2C
	107	#define CONFIG_CMD_IMI
49cf7e8e	108	#define CONFIG_CMD_IMMAP
74de7aef WD	109	#define CONFIG_CMD_MEMORY
74de7aef WD	110	#define CONFIG_CMD_NET
49cf7e8e	111	#define CONFIG_CMD_REGINFO
49cf7e8e	112	#define CONFIG_CMD_RUN
74de7aef	113	#define CONFIG_CMD_SAVEENV
49cf7e8e	114	#define CONFIG_CMD_SETGETDCR
74de7aef	115	#define CONFIG_CMD_SOURCE
49cf7e8e	116
c609719b WD	117
c609719b WD	118	/*
5d2ebe1b	119	* BOOTP options
c609719b	120	*/
5d2ebe1b JL	121	#define CONFIG_BOOTP_SUBNETMASK
	122	#define CONFIG_BOOTP_GATEWAY
	123	#define CONFIG_BOOTP_HOSTNAME
	124	#define CONFIG_BOOTP_BOOTPATH
	125	#define CONFIG_BOOTP_VENDOREX
	126	#define CONFIG_BOOTP_DNS
	127	#define CONFIG_BOOTP_BOOTFILESIZE
	128
c609719b	129
8bde7f77	130	/*
7f70e853 WD	131	* how many time to fail & restart a net-TFTP before giving up & resetting
	132	* the board hoping that a reset of net interface might help..
	133	*/
	134	#define CONFIG_NET_RESET 5
	135
8bde7f77	136	/*
c609719b WD	137	* bauds. Just to make it compile; in our case, I read the base_baud
	138	* from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
	139	* drives the system clock.
	140	*/
6d0f6bcf JCPV	141	#define CONFIG_SYS_BASE_BAUD 403225
6d0f6bcf JCPV	142	#define CONFIG_SYS_BAUDRATE_TABLE \
c609719b WD	143	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
c609719b WD	144
c609719b WD	145	/*
	146	* Miscellaneous configurable options
	147	*/
6d0f6bcf JCPV	148	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	149	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	150	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	151	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	152	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
c609719b WD	153
c609719b WD	154
6d0f6bcf JCPV	155	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */
	156	#define CONFIG_SYS_TFTP_LOADADDR CONFIG_SYS_LOAD_ADDR
	157	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	158	#define CONFIG_SYS_DRAM_TEST 1
c609719b WD	159
	160	/*-----------------------------------------------------------------------
	161	* Start addresses for the final memory configuration
	162	* (Set up by the startup code)
6d0f6bcf	163	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	164	*/
6d0f6bcf JCPV	165	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	166	#define CONFIG_SYS_FLASH_BASE 0xFFC00000
14d0a02a	167	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
c609719b	168
c609719b	169
6d0f6bcf	170	#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
c609719b WD	171
	172	/*
	173	* For booting Linux, the board info and command line data
	174	* have to be in the first 8 MB of memory, since this is
	175	* the maximum mapped by the Linux kernel during initialization.
	176	*/
6d0f6bcf	177	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	178	/*-----------------------------------------------------------------------
	179	* FLASH organization
	180	*/
6d0f6bcf JCPV	181	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	182	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
	183	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	184	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b WD	185
c609719b WD	186	/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */
0e8d1586	187	#define CONFIG_ENV_OFFSET 0x3c8000
5a1aceb0	188	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
0e8d1586 JCPV	189	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment area */
0e8d1586 JCPV	190	#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
c609719b	191
7f70e853	192	/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
c609719b WD	193	* 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
c609719b WD	194	*/
6d0f6bcf JCPV	195	#define CONFIG_SYS_SDRAM_SIZE 32 /* megs of ram */
6d0f6bcf JCPV	196	#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
c609719b WD	197	/* the exception vector table */
	198	/* to the end of the DRAM */
	199	/* less monitor and malloc area */
6d0f6bcf JCPV	200	#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
	201	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128k for malloc space */
	202	#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
	203	+ CONFIG_SYS_MALLOC_LEN \
0e8d1586	204	+ CONFIG_ENV_SECT_SIZE \
6d0f6bcf	205	+ CONFIG_SYS_STACK_USAGE )
c609719b	206
6d0f6bcf	207	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE)
c609719b WD	208	/* END ENVIRONNEMENT FLASH */
c609719b WD	209
c609719b WD	210	/*
	211	* Init Memory Controller:
	212	*
	213	* BR0/1 and OR0/1 (FLASH)
	214	*/
	215
6d0f6bcf	216	#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
c609719b WD	217
	218
	219	/*-----------------------------------------------------------------------
	220	* Definitions for initial stack pointer and data area (in OnChipMem )
	221	*/
7f70e853 WD	222	#if 1
7f70e853 WD	223	/* On Chip Memory location */
6d0f6bcf JCPV	224	#define CONFIG_SYS_TEMP_STACK_OCM 1
	225	#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
	226	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	227
	228	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
553f0982	229	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
25ddd1fb	230	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	231	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
7f70e853	232	#else
6d0f6bcf JCPV	233	#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
	234	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	235	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
553f0982	236	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
25ddd1fb	237	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	238	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
7f70e853	239	#endif
c609719b WD	240
	241	/*-----------------------------------------------------------------------
	242	* Definitions for Serial Presence Detect EEPROM address
	243	*/
	244	#define EEPROM_WRITE_ADDRESS 0xA0
	245	#define EEPROM_READ_ADDRESS 0xA1
	246
c609719b	247	#endif /* __CONFIG_H */