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c609719b | 1 | /* |
c837dcb1 | 2 | * (C) Copyright 2000-2004 |
c609719b WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite.. | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | #define CONFIG_CRAYL1 | |
32 | /* | |
33 | * High Level Configuration Options | |
34 | * (easy to change) | |
35 | */ | |
36 | ||
37 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
38 | #define CONFIG_4xx 1 /* ...member of PPC405 family */ | |
2ae18241 WD |
39 | |
40 | /* | |
41 | * Note: I make an "image" from U-Boot itself, which prefixes 0x40 | |
42 | * bytes of header info, hence start address is thus shifted. | |
43 | */ | |
44 | #define CONFIG_SYS_TEXT_BASE 0xFFFD0040 | |
45 | ||
c609719b WD |
46 | #define CONFIG_SYS_CLK_FREQ 25000000 |
47 | #define CONFIG_BAUDRATE 9600 | |
48 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
96e21f86 BW |
49 | |
50 | #define CONFIG_PPC4xx_EMAC | |
c609719b WD |
51 | #define CONFIG_MII 1 /* MII PHY management */ |
52 | #define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */ | |
c837dcb1 | 53 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */ |
c609719b WD |
54 | #define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */ |
55 | ||
550650dd SR |
56 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
57 | #define CONFIG_SYS_NS16550 | |
58 | #define CONFIG_SYS_NS16550_SERIAL | |
59 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
60 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
61 | ||
c609719b WD |
62 | /* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to |
63 | * keep possible initrd ramdisk decompression out. This is in k (1024 bytes) | |
8bde7f77 | 64 | #define CONFIG_PRAM 16 |
c609719b | 65 | */ |
7f70e853 | 66 | #define CONFIG_LOADADDR 0x100000 /* where TFTP images go */ |
c609719b WD |
67 | #undef CONFIG_BOOTARGS |
68 | ||
7f70e853 WD |
69 | /* Bootcmd is overridden by the bootscript in board/cray/L1 |
70 | */ | |
6d0f6bcf | 71 | #define CONFIG_SYS_AUTOLOAD "no" |
7f70e853 | 72 | #define CONFIG_BOOTCOMMAND "dhcp" |
c609719b | 73 | |
8bde7f77 | 74 | /* |
c609719b WD |
75 | * ..during experiments.. |
76 | #define CONFIG_SERVERIP 10.0.0.1 | |
8bde7f77 | 77 | #define CONFIG_ETHADDR 00:40:a6:80:14:5 |
c609719b WD |
78 | */ |
79 | #define CONFIG_HARD_I2C 1 /* hardware support for i2c */ | |
d0b0dcaa | 80 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
7f70e853 | 81 | #define CONFIG_SDRAM_BANK0 1 |
6d0f6bcf JCPV |
82 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
83 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
84 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
85 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
c609719b WD |
86 | #define CONFIG_IDENT_STRING "Cray L1" |
87 | #define CONFIG_ENV_OVERWRITE 1 | |
6d0f6bcf JCPV |
88 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
89 | #define CONFIG_SYS_HUSH_PARSER 1 | |
90 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
74de7aef | 91 | #define CONFIG_SOURCE 1 |
c609719b WD |
92 | |
93 | ||
49cf7e8e JL |
94 | /* |
95 | * Command line configuration. | |
96 | */ | |
97 | ||
74de7aef | 98 | #define CONFIG_CMD_ASKENV |
49cf7e8e | 99 | #define CONFIG_CMD_BDI |
49cf7e8e | 100 | #define CONFIG_CMD_CONSOLE |
74de7aef WD |
101 | #define CONFIG_CMD_DATE |
102 | #define CONFIG_CMD_DHCP | |
103 | #define CONFIG_CMD_DIAG | |
49cf7e8e | 104 | #define CONFIG_CMD_ECHO |
74de7aef WD |
105 | #define CONFIG_CMD_EEPROM |
106 | #define CONFIG_CMD_FLASH | |
107 | #define CONFIG_CMD_I2C | |
108 | #define CONFIG_CMD_IMI | |
49cf7e8e | 109 | #define CONFIG_CMD_IMMAP |
74de7aef WD |
110 | #define CONFIG_CMD_MEMORY |
111 | #define CONFIG_CMD_NET | |
49cf7e8e | 112 | #define CONFIG_CMD_REGINFO |
49cf7e8e | 113 | #define CONFIG_CMD_RUN |
74de7aef | 114 | #define CONFIG_CMD_SAVEENV |
49cf7e8e | 115 | #define CONFIG_CMD_SETGETDCR |
74de7aef | 116 | #define CONFIG_CMD_SOURCE |
49cf7e8e | 117 | |
c609719b WD |
118 | |
119 | /* | |
5d2ebe1b | 120 | * BOOTP options |
c609719b | 121 | */ |
5d2ebe1b JL |
122 | #define CONFIG_BOOTP_SUBNETMASK |
123 | #define CONFIG_BOOTP_GATEWAY | |
124 | #define CONFIG_BOOTP_HOSTNAME | |
125 | #define CONFIG_BOOTP_BOOTPATH | |
126 | #define CONFIG_BOOTP_VENDOREX | |
127 | #define CONFIG_BOOTP_DNS | |
128 | #define CONFIG_BOOTP_BOOTFILESIZE | |
129 | ||
c609719b | 130 | |
8bde7f77 | 131 | /* |
7f70e853 WD |
132 | * how many time to fail & restart a net-TFTP before giving up & resetting |
133 | * the board hoping that a reset of net interface might help.. | |
134 | */ | |
135 | #define CONFIG_NET_RESET 5 | |
136 | ||
8bde7f77 | 137 | /* |
c609719b WD |
138 | * bauds. Just to make it compile; in our case, I read the base_baud |
139 | * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn | |
140 | * drives the system clock. | |
141 | */ | |
6d0f6bcf JCPV |
142 | #define CONFIG_SYS_BASE_BAUD 403225 |
143 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
c609719b WD |
144 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
145 | ||
c609719b WD |
146 | /* |
147 | * Miscellaneous configurable options | |
148 | */ | |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
150 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
151 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
152 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
153 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
c609719b WD |
154 | |
155 | ||
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */ |
157 | #define CONFIG_SYS_TFTP_LOADADDR CONFIG_SYS_LOAD_ADDR | |
158 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
159 | #define CONFIG_SYS_DRAM_TEST 1 | |
c609719b WD |
160 | |
161 | /*----------------------------------------------------------------------- | |
162 | * Start addresses for the final memory configuration | |
163 | * (Set up by the startup code) | |
6d0f6bcf | 164 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 165 | */ |
6d0f6bcf JCPV |
166 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
167 | #define CONFIG_SYS_FLASH_BASE 0xFFC00000 | |
14d0a02a | 168 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
c609719b | 169 | |
c609719b | 170 | |
6d0f6bcf | 171 | #define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ |
c609719b WD |
172 | |
173 | /* | |
174 | * For booting Linux, the board info and command line data | |
175 | * have to be in the first 8 MB of memory, since this is | |
176 | * the maximum mapped by the Linux kernel during initialization. | |
177 | */ | |
6d0f6bcf | 178 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c609719b WD |
179 | /*----------------------------------------------------------------------- |
180 | * FLASH organization | |
181 | */ | |
6d0f6bcf JCPV |
182 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
183 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ | |
184 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
185 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c609719b WD |
186 | |
187 | /* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */ | |
0e8d1586 | 188 | #define CONFIG_ENV_OFFSET 0x3c8000 |
5a1aceb0 | 189 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
0e8d1586 JCPV |
190 | #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment area */ |
191 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ | |
c609719b | 192 | |
7f70e853 | 193 | /* Memory tests: U-BOOT relocates itself to the top of Ram, so its at |
c609719b WD |
194 | * 32meg-(128k+some_malloc_space+copy-of-ENV sector).. |
195 | */ | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_SDRAM_SIZE 32 /* megs of ram */ |
197 | #define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ | |
c609719b WD |
198 | /* the exception vector table */ |
199 | /* to the end of the DRAM */ | |
200 | /* less monitor and malloc area */ | |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ |
202 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128k for malloc space */ | |
203 | #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ | |
204 | + CONFIG_SYS_MALLOC_LEN \ | |
0e8d1586 | 205 | + CONFIG_ENV_SECT_SIZE \ |
6d0f6bcf | 206 | + CONFIG_SYS_STACK_USAGE ) |
c609719b | 207 | |
6d0f6bcf | 208 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE) |
c609719b WD |
209 | /* END ENVIRONNEMENT FLASH */ |
210 | ||
c609719b WD |
211 | /* |
212 | * Init Memory Controller: | |
213 | * | |
214 | * BR0/1 and OR0/1 (FLASH) | |
215 | */ | |
216 | ||
6d0f6bcf | 217 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ |
c609719b WD |
218 | |
219 | ||
220 | /*----------------------------------------------------------------------- | |
221 | * Definitions for initial stack pointer and data area (in OnChipMem ) | |
222 | */ | |
7f70e853 WD |
223 | #if 1 |
224 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
226 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 | |
227 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
228 | ||
229 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 230 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
25ddd1fb | 231 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 232 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
7f70e853 | 233 | #else |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 |
235 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
236 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ | |
553f0982 | 237 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */ |
25ddd1fb | 238 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 239 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
7f70e853 | 240 | #endif |
c609719b WD |
241 | |
242 | /*----------------------------------------------------------------------- | |
243 | * Definitions for Serial Presence Detect EEPROM address | |
244 | */ | |
245 | #define EEPROM_WRITE_ADDRESS 0xA0 | |
246 | #define EEPROM_READ_ADDRESS 0xA1 | |
247 | ||
c609719b | 248 | #endif /* __CONFIG_H */ |