projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c609719b | 1 | /* |
| 414eec35 | 2 | * (C) Copyright 2001-2005 |
| c609719b WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| c609719b WD |
6 | */ |
| 7 | ||
| 8 | /* | |
| 9 | * | |
| 10 | * Configuration settings for the CU824 board. | |
| 11 | * | |
| 12 | */ | |
| 13 | ||
| 14 | /* ------------------------------------------------------------------------- */ | |
| 15 | ||
| 16 | /* | |
| 17 | * board/config.h - configuration options, board specific | |
| 18 | */ | |
| 19 | ||
| 20 | #ifndef __CONFIG_H | |
| 21 | #define __CONFIG_H | |
| 22 | ||
| 23 | /* | |
| 24 | * High Level Configuration Options | |
| 25 | * (easy to change) | |
| 26 | */ | |
| 27 | ||
| 28 | #define CONFIG_MPC824X 1 | |
| 29 | #define CONFIG_MPC8240 1 | |
| 30 | #define CONFIG_CU824 1 | |
| 31 | ||
| 2ae18241 | 32 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
| c609719b WD |
33 | |
| 34 | #define CONFIG_CONS_INDEX 1 | |
| 35 | #define CONFIG_BAUDRATE 9600 | |
| c609719b | 36 | |
| 32bf3d14 | 37 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
| c609719b WD |
38 | |
| 39 | #define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ | |
| 40 | #define CONFIG_BOOTDELAY 5 | |
| 41 | ||
| 5d2ebe1b JL |
42 | /* |
| 43 | * BOOTP options | |
| 44 | */ | |
| 45 | #define CONFIG_BOOTP_SUBNETMASK | |
| 46 | #define CONFIG_BOOTP_GATEWAY | |
| 47 | #define CONFIG_BOOTP_HOSTNAME | |
| 48 | #define CONFIG_BOOTP_BOOTPATH | |
| 49 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 50 | ||
| c609719b | 51 | |
| 414eec35 WD |
52 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
| 53 | ||
| 49cf7e8e JL |
54 | |
| 55 | /* | |
| 56 | * Command line configuration. | |
| c609719b | 57 | */ |
| 49cf7e8e JL |
58 | #include <config_cmd_default.h> |
| 59 | ||
| 5728be38 | 60 | #define CONFIG_CMD_BEDBUG |
| 49cf7e8e JL |
61 | #define CONFIG_CMD_DHCP |
| 62 | #define CONFIG_CMD_PCI | |
| 63 | #define CONFIG_CMD_NFS | |
| 64 | #define CONFIG_CMD_SNTP | |
| c609719b WD |
65 | |
| 66 | ||
| 67 | /* | |
| 68 | * Miscellaneous configurable options | |
| 69 | */ | |
| 6d0f6bcf JCPV |
70 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 71 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 72 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| c609719b WD |
73 | |
| 74 | #if 1 | |
| 6d0f6bcf | 75 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
| c609719b | 76 | #endif |
| c609719b WD |
77 | |
| 78 | /* Print Buffer Size | |
| 79 | */ | |
| 6d0f6bcf | 80 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| c609719b | 81 | |
| 6d0f6bcf JCPV |
82 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 83 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 84 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ | |
| c609719b WD |
85 | |
| 86 | /*----------------------------------------------------------------------- | |
| 87 | * Start addresses for the final memory configuration | |
| 88 | * (Set up by the startup code) | |
| 6d0f6bcf | 89 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| c609719b | 90 | */ |
| 6d0f6bcf JCPV |
91 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 92 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
| c609719b | 93 | |
| 6d0f6bcf | 94 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
| c609719b | 95 | |
| 6d0f6bcf | 96 | #define CONFIG_SYS_EUMB_ADDR 0xFCE00000 |
| c609719b | 97 | |
| 14d0a02a | 98 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| c609719b | 99 | |
| 6d0f6bcf JCPV |
100 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 101 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| c609719b | 102 | |
| 6d0f6bcf JCPV |
103 | #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ |
| 104 | #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ | |
| c609719b WD |
105 | |
| 106 | /* Maximum amount of RAM. | |
| 107 | */ | |
| 6d0f6bcf | 108 | #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 |
| c609719b WD |
109 | |
| 110 | ||
| 6d0f6bcf JCPV |
111 | #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE |
| 112 | #undef CONFIG_SYS_RAMBOOT | |
| c609719b | 113 | #else |
| 6d0f6bcf | 114 | #define CONFIG_SYS_RAMBOOT |
| c609719b WD |
115 | #endif |
| 116 | ||
| 117 | ||
| 118 | /*----------------------------------------------------------------------- | |
| 119 | * Definitions for initial stack pointer and data area | |
| 120 | */ | |
| 121 | ||
| 6d0f6bcf | 122 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
| 553f0982 | 123 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
| 25ddd1fb | 124 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| c609719b WD |
125 | |
| 126 | /* | |
| 127 | * NS16550 Configuration | |
| 128 | */ | |
| 6d0f6bcf JCPV |
129 | #define CONFIG_SYS_NS16550 |
| 130 | #define CONFIG_SYS_NS16550_SERIAL | |
| c609719b | 131 | |
| 6d0f6bcf | 132 | #define CONFIG_SYS_NS16550_REG_SIZE 4 |
| c609719b | 133 | |
| 6d0f6bcf | 134 | #define CONFIG_SYS_NS16550_CLK (14745600 / 2) |
| c609719b | 135 | |
| 6d0f6bcf JCPV |
136 | #define CONFIG_SYS_NS16550_COM1 0xFE800080 |
| 137 | #define CONFIG_SYS_NS16550_COM2 0xFE8000C0 | |
| c609719b WD |
138 | |
| 139 | /* | |
| 140 | * Low Level Configuration Settings | |
| 141 | * (address mappings, register initial values, etc.) | |
| 142 | * You should know what you are doing if you make changes here. | |
| 143 | * For the detail description refer to the MPC8240 user's manual. | |
| 144 | */ | |
| 145 | ||
| 146 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
| 6d0f6bcf | 147 | #define CONFIG_SYS_HZ 1000 |
| c609719b WD |
148 | |
| 149 | /* Bit-field values for MCCR1. | |
| 150 | */ | |
| 6d0f6bcf JCPV |
151 | #define CONFIG_SYS_ROMNAL 0 |
| 152 | #define CONFIG_SYS_ROMFAL 7 | |
| c609719b WD |
153 | |
| 154 | /* Bit-field values for MCCR2. | |
| 155 | */ | |
| 6d0f6bcf | 156 | #define CONFIG_SYS_REFINT 430 /* Refresh interval */ |
| c609719b WD |
157 | |
| 158 | /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. | |
| 159 | */ | |
| 6d0f6bcf | 160 | #define CONFIG_SYS_BSTOPRE 192 |
| c609719b WD |
161 | |
| 162 | /* Bit-field values for MCCR3. | |
| 163 | */ | |
| 6d0f6bcf JCPV |
164 | #define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ |
| 165 | #define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */ | |
| c609719b WD |
166 | |
| 167 | /* Bit-field values for MCCR4. | |
| 168 | */ | |
| 6d0f6bcf JCPV |
169 | #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ |
| 170 | #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ | |
| 171 | #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ | |
| 172 | #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ | |
| 173 | #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ | |
| 174 | #define CONFIG_SYS_ACTORW 2 | |
| 175 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 | |
| c609719b WD |
176 | |
| 177 | /* Memory bank settings. | |
| 178 | * Only bits 20-29 are actually used from these vales to set the | |
| 179 | * start/end addresses. The upper two bits will always be 0, and the lower | |
| 180 | * 20 bits will be 0x00000 for a start address, or 0xfffff for an end | |
| 181 | * address. Refer to the MPC8240 book. | |
| 182 | */ | |
| 183 | ||
| 6d0f6bcf JCPV |
184 | #define CONFIG_SYS_BANK0_START 0x00000000 |
| 185 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) | |
| 186 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
| 187 | #define CONFIG_SYS_BANK1_START 0x3ff00000 | |
| 188 | #define CONFIG_SYS_BANK1_END 0x3fffffff | |
| 189 | #define CONFIG_SYS_BANK1_ENABLE 0 | |
| 190 | #define CONFIG_SYS_BANK2_START 0x3ff00000 | |
| 191 | #define CONFIG_SYS_BANK2_END 0x3fffffff | |
| 192 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
| 193 | #define CONFIG_SYS_BANK3_START 0x3ff00000 | |
| 194 | #define CONFIG_SYS_BANK3_END 0x3fffffff | |
| 195 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
| 196 | #define CONFIG_SYS_BANK4_START 0x3ff00000 | |
| 197 | #define CONFIG_SYS_BANK4_END 0x3fffffff | |
| 198 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
| 199 | #define CONFIG_SYS_BANK5_START 0x3ff00000 | |
| 200 | #define CONFIG_SYS_BANK5_END 0x3fffffff | |
| 201 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
| 202 | #define CONFIG_SYS_BANK6_START 0x3ff00000 | |
| 203 | #define CONFIG_SYS_BANK6_END 0x3fffffff | |
| 204 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
| 205 | #define CONFIG_SYS_BANK7_START 0x3ff00000 | |
| 206 | #define CONFIG_SYS_BANK7_END 0x3fffffff | |
| 207 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
| 208 | ||
| 209 | #define CONFIG_SYS_ODCR 0xff | |
| 210 | ||
| 211 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 212 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 213 | ||
| 214 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 215 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 216 | ||
| 217 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) | |
| 218 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 219 | ||
| 220 | #define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) | |
| 221 | #define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) | |
| 222 | ||
| 223 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
| 224 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| 225 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 226 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| 227 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
| 228 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
| 229 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
| 230 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| c609719b WD |
231 | |
| 232 | /* | |
| 233 | * For booting Linux, the board info and command line data | |
| 234 | * have to be in the first 8 MB of memory, since this is | |
| 235 | * the maximum mapped by the Linux kernel during initialization. | |
| 236 | */ | |
| 6d0f6bcf | 237 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| c609719b WD |
238 | |
| 239 | /*----------------------------------------------------------------------- | |
| 240 | * FLASH organization | |
| 241 | */ | |
| 6d0f6bcf JCPV |
242 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */ |
| 243 | #define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ | |
| c609719b | 244 | |
| 6d0f6bcf JCPV |
245 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 246 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| c609719b WD |
247 | |
| 248 | /* Warining: environment is not EMBEDDED in the U-Boot code. | |
| 249 | * It's stored in flash separately. | |
| 250 | */ | |
| 5a1aceb0 | 251 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| c609719b | 252 | #if 0 |
| 0e8d1586 JCPV |
253 | #define CONFIG_ENV_ADDR 0xFF008000 |
| 254 | #define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment Sector */ | |
| c609719b | 255 | #else |
| 0e8d1586 JCPV |
256 | #define CONFIG_ENV_ADDR 0xFFFC0000 |
| 257 | #define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */ | |
| 258 | #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ | |
| 259 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ | |
| c609719b WD |
260 | #endif |
| 261 | ||
| 262 | /*----------------------------------------------------------------------- | |
| 263 | * Cache Configuration | |
| 264 | */ | |
| 6d0f6bcf | 265 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
| 49cf7e8e | 266 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 267 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| c609719b WD |
268 | #endif |
| 269 | ||
| c609719b WD |
270 | /*----------------------------------------------------------------------- |
| 271 | * PCI stuff | |
| 272 | *----------------------------------------------------------------------- | |
| 273 | */ | |
| 274 | #define CONFIG_PCI /* include pci support */ | |
| 842033e6 | 275 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
| c609719b WD |
276 | #undef CONFIG_PCI_PNP |
| 277 | ||
| c609719b WD |
278 | |
| 279 | #define CONFIG_TULIP | |
| 280 | #define CONFIG_TULIP_USE_IO | |
| 281 | ||
| 6d0f6bcf JCPV |
282 | #define CONFIG_SYS_ETH_DEV_FN 0x7800 |
| 283 | #define CONFIG_SYS_ETH_IOBASE 0x00104000 | |
| c609719b | 284 | |
| 3bac3513 | 285 | #define CONFIG_EEPRO100 |
| 6d0f6bcf | 286 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
| 3bac3513 WD |
287 | #define PCI_ENET0_IOADDR 0x00104000 |
| 288 | #define PCI_ENET0_MEMADDR 0x80000000 | |
| c609719b | 289 | #endif /* __CONFIG_H */ |