projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 3a473b2a WD |
1 | /* |
| 2 | * (C) Copyright 2001 | |
| 3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | /************************************************************************* | |
| 29 | * (c) 2002 Datentechnik AG - Project: Dino | |
| 30 | * | |
| 31 | * | |
| 32 | * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $ | |
| 33 | * | |
| 34 | ************************************************************************/ | |
| 35 | ||
| 36 | /************************************************************************* | |
| 37 | * | |
| 38 | * History: | |
| 39 | * | |
| 40 | * $Log: DB64360.h,v $ | |
| 41 | * Revision 1.3 2003/04/26 04:58:13 brad | |
| 42 | * Cosmetic changes and compiler warning cleanups | |
| 43 | * | |
| 44 | * Revision 1.2 2003/04/23 15:48:15 ingo | |
| 45 | * mem. map output added | |
| 46 | * | |
| 47 | * Revision 1.1 2003/04/17 09:31:42 ias | |
| 48 | * keymile changes 17_04_2003 | |
| 49 | * | |
| 50 | * Revision 1.10 2003/03/06 12:25:04 ias | |
| 51 | * 750 FX CPU HID settings updated | |
| 52 | * | |
| 53 | * Revision 1.9 2003/03/03 16:14:36 ias | |
| 54 | * cleanup compiler warnings of printf fuctions | |
| 55 | * | |
| 56 | * Revision 1.8 2003/03/03 15:11:44 ias | |
| 57 | * Marvell MPSC-UART is working | |
| 58 | * | |
| 59 | * Revision 1.7 2003/02/26 12:15:45 ssu | |
| 60 | * adapted default parameters to new board flash address | |
| 61 | * | |
| 62 | * Revision 1.6 2003/02/25 14:55:42 ssu | |
| 63 | * changed default environment parameters | |
| 64 | * | |
| 65 | * Revision 1.5 2003/02/21 17:14:23 ias | |
| 66 | * added extended SPD handling | |
| 67 | * | |
| 68 | * Revision 1.4 2003/01/14 09:16:08 ias | |
| 69 | * PPCBoot for Marvel Beta 0.9 | |
| 70 | * | |
| 71 | * Revision 1.3 2002/12/03 13:56:26 ias | |
| 72 | * Environment in flash support added | |
| 73 | * | |
| 74 | * Revision 1.2 2002/11/29 16:53:29 ias | |
| 75 | * Flash support for STM added | |
| 76 | * | |
| 77 | * Revision 1.1 2002/11/29 13:36:31 ias | |
| 78 | * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board | |
| 79 | * - working DDRRAM (only 32MByte of 128MB Modul) | |
| 80 | * - working I2C Driver for SPD EEPROM read | |
| 81 | * - working DUART 16650 for Serial Console | |
| 82 | * - working "console" | |
| 83 | * | |
| 84 | * | |
| 85 | * | |
| 86 | ************************************************************************/ | |
| 87 | ||
| 88 | #ifndef __CONFIG_H | |
| 89 | #define __CONFIG_H | |
| 90 | ||
| 3a473b2a WD |
91 | /* This define must be before the core.h include */ |
| 92 | #define CONFIG_DB64360 1 /* this is an DB64360 board */ | |
| 93 | ||
| 94 | #ifndef __ASSEMBLY__ | |
| 95 | #include "../board/Marvell/include/core.h" | |
| 96 | #endif | |
| 97 | ||
| 98 | /*-----------------------------------------------------*/ | |
| 99 | /* #include "../board/db64360/local.h" */ | |
| 100 | #ifndef __LOCAL_H | |
| 101 | #define __LOCAL_H | |
| 102 | ||
| 103 | /* first ethernet */ | |
| 104 | #define CONFIG_ETHADDR 64:36:00:00:00:01 | |
| 105 | /* next two ethernet hwaddrs */ | |
| e2ffd59b | 106 | #define CONFIG_HAS_ETH1 |
| 3a473b2a WD |
107 | #define CONFIG_ETH1ADDR 64:36:00:00:00:02 |
| 108 | /* in the atlantis 64360 we have only 2 ETH port on the board, | |
| 109 | if we use PCI it has its own MAC addr */ | |
| 110 | ||
| 111 | #define CONFIG_ENV_OVERWRITE | |
| 112 | #endif /* __CONFIG_H */ | |
| 113 | ||
| 114 | /* | |
| 115 | * High Level Configuration Options | |
| 116 | * (easy to change) | |
| 117 | */ | |
| 118 | ||
| 119 | #define CONFIG_74xx /* we have a 750FX (override local.h) */ | |
| 120 | ||
| 121 | #define CONFIG_DB64360 1 /* this is an DB64360 board */ | |
| 122 | ||
| 2ae18241 WD |
123 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
| 124 | ||
| 3a473b2a WD |
125 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ |
| 126 | /*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the | |
| 127 | DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. | |
| 128 | so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, | |
| 129 | see sdram_init.c */ | |
| 130 | #undef CONFIG_ECC /* enable ECC support */ | |
| 131 | #define CONFIG_MV64360_ECC | |
| 132 | ||
| 133 | /* which initialization functions to call for this board */ | |
| 134 | #define CONFIG_MISC_INIT_R /* initialize the icache L1 */ | |
| c837dcb1 | 135 | #define CONFIG_BOARD_EARLY_INIT_F |
| 3a473b2a | 136 | |
| 6d0f6bcf | 137 | #define CONFIG_SYS_BOARD_NAME "DB64360" |
| 3a473b2a WD |
138 | #define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)" |
| 139 | ||
| 6d0f6bcf JCPV |
140 | /*#define CONFIG_SYS_HUSH_PARSER */ |
| 141 | #undef CONFIG_SYS_HUSH_PARSER | |
| 3a473b2a | 142 | |
| 6d0f6bcf | 143 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| 3a473b2a WD |
144 | |
| 145 | /* | |
| 146 | * The following defines let you select what serial you want to use | |
| 147 | * for your console driver. | |
| 148 | * | |
| 149 | * what to do: | |
| 150 | * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial | |
| 6d0f6bcf | 151 | * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 |
| 3a473b2a WD |
152 | * to 0 below. |
| 153 | * | |
| 154 | * to use the MPSC, #define CONFIG_MPSC. If you have wired up another | |
| 155 | * mpsc channel, change CONFIG_MPSC_PORT to the desired value. | |
| 156 | */ | |
| 157 | ||
| 158 | #define CONFIG_MPSC_PORT 0 | |
| 159 | ||
| 160 | /* to change the default ethernet port, use this define (options: 0, 1, 2) */ | |
| 3a473b2a WD |
161 | #define MV_ETH_DEVS 2 |
| 162 | ||
| 163 | /* #undef CONFIG_ETHER_PORT_MII */ | |
| 164 | #if 0 | |
| 165 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
| 166 | #else | |
| 167 | #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ | |
| 168 | #endif | |
| 169 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
| 170 | ||
| 171 | ||
| 172 | #undef CONFIG_BOOTARGS | |
| 32bf3d14 | 173 | /*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ |
| 3a473b2a WD |
174 | |
| 175 | /* ronen - autoboot using tftp */ | |
| 176 | #if (CONFIG_BOOTDELAY >= 0) | |
| 177 | #define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ | |
| fe126d8b WD |
178 | setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ |
| 179 | ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " | |
| 3a473b2a WD |
180 | |
| 181 | #define CONFIG_BOOTARGS "console=ttyS0,115200" | |
| 182 | ||
| 183 | #endif | |
| 184 | ||
| 185 | /* ronen - the u-boot.bin should be ~0x30000 bytes */ | |
| 186 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 187 | "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ | |
| 188 | cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ | |
| 189 | "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ | |
| 190 | cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ | |
| 191 | "bootargs_root=root=/dev/nfs rw\0" \ | |
| 192 | "bootargs_end=:::DB64360:eth0:none \0"\ | |
| 193 | "ethprime=mv_enet0\0"\ | |
| fe126d8b WD |
194 | "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ |
| 195 | ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" | |
| 3a473b2a WD |
196 | |
| 197 | /* --------------------------------------------------------------------------------------------------------------- */ | |
| 198 | /* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */ | |
| 199 | ||
| 200 | #define CONFIG_IPADDR 10.2.40.90 | |
| 201 | ||
| 202 | #define CONFIG_SERIAL "No. 1" | |
| 203 | #define CONFIG_SERVERIP 10.2.1.126 | |
| 8b3637c6 | 204 | #define CONFIG_ROOTPATH "/mnt/yellow_dog_mini" |
| 3a473b2a WD |
205 | |
| 206 | ||
| 207 | #define CONFIG_TESTDRAMDATA y | |
| 208 | #define CONFIG_TESTDRAMADDRESS n | |
| 209 | #define CONFIG_TESETDRAMWALK n | |
| 210 | ||
| 211 | /* --------------------------------------------------------------------------------------------------------------- */ | |
| 212 | ||
| 213 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ | |
| 6d0f6bcf | 214 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ |
| 3a473b2a WD |
215 | |
| 216 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 217 | #undef CONFIG_ALTIVEC /* undef to disable */ | |
| 218 | ||
| 5d2ebe1b JL |
219 | /* |
| 220 | * BOOTP options | |
| 221 | */ | |
| 222 | #define CONFIG_BOOTP_SUBNETMASK | |
| 223 | #define CONFIG_BOOTP_GATEWAY | |
| 224 | #define CONFIG_BOOTP_HOSTNAME | |
| 225 | #define CONFIG_BOOTP_BOOTPATH | |
| 226 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 227 | ||
| 228 | ||
| 700a0c64 WD |
229 | /* |
| 230 | * JFFS2 partitions | |
| 231 | * | |
| 232 | */ | |
| 233 | /* No command line, one static partition, whole device */ | |
| 68d7d651 | 234 | #undef CONFIG_CMD_MTDPARTS |
| 700a0c64 WD |
235 | #define CONFIG_JFFS2_DEV "nor1" |
| 236 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
| 237 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
| 3a473b2a | 238 | |
| 700a0c64 WD |
239 | /* mtdparts command line support */ |
| 240 | ||
| 241 | /* Use first bank for JFFS2, second bank contains U-Boot. | |
| 242 | * | |
| 243 | * Note: fake mtd_id's used, no linux mtd map file. | |
| 244 | */ | |
| 245 | /* | |
| 68d7d651 | 246 | #define CONFIG_CMD_MTDPARTS |
| 700a0c64 WD |
247 | #define MTDIDS_DEFAULT "nor1=db64360-1" |
| 248 | #define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)" | |
| 249 | */ | |
| 3a473b2a | 250 | |
| 3c3227f3 JL |
251 | |
| 252 | /* | |
| 253 | * Command line configuration. | |
| 254 | */ | |
| 255 | #include <config_cmd_default.h> | |
| 256 | ||
| 257 | #define CONFIG_CMD_ASKENV | |
| 258 | #define CONFIG_CMD_I2C | |
| 259 | #define CONFIG_CMD_EEPROM | |
| 260 | #define CONFIG_CMD_CACHE | |
| 261 | #define CONFIG_CMD_JFFS2 | |
| 262 | #define CONFIG_CMD_PCI | |
| 263 | #define CONFIG_CMD_NET | |
| 264 | ||
| 3a473b2a WD |
265 | |
| 266 | /* | |
| 267 | * Miscellaneous configurable options | |
| 268 | */ | |
| 6d0f6bcf JCPV |
269 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 270 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
| 271 | #define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */ | |
| 3a473b2a | 272 | |
| 6d0f6bcf JCPV |
273 | /* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */ |
| 274 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 275 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 3c3227f3 | 276 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 277 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 3a473b2a | 278 | #else |
| 6d0f6bcf | 279 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 3a473b2a | 280 | #endif |
| 6d0f6bcf JCPV |
281 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 282 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 283 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 3a473b2a | 284 | |
| 6d0f6bcf JCPV |
285 | /*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */ |
| 286 | /*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ | |
| 287 | /*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ | |
| 3a473b2a WD |
288 | |
| 289 | /* | |
| 6d0f6bcf | 290 | #define CONFIG_SYS_DRAM_TEST |
| 3a473b2a | 291 | * DRAM tests |
| 6d0f6bcf | 292 | * CONFIG_SYS_DRAM_TEST - enables the following tests. |
| 3a473b2a | 293 | * |
| 6d0f6bcf | 294 | * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines |
| 3a473b2a WD |
295 | * Environment variable 'test_dram_data' must be |
| 296 | * set to 'y'. | |
| 6d0f6bcf | 297 | * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely |
| 3a473b2a WD |
298 | * addressable. Environment variable |
| 299 | * 'test_dram_address' must be set to 'y'. | |
| 6d0f6bcf | 300 | * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. |
| 3a473b2a WD |
301 | * This test takes about 6 minutes to test 64 MB. |
| 302 | * Environment variable 'test_dram_walk' must be | |
| 303 | * set to 'y'. | |
| 304 | */ | |
| 6d0f6bcf JCPV |
305 | #define CONFIG_SYS_DRAM_TEST |
| 306 | #if defined(CONFIG_SYS_DRAM_TEST) | |
| 307 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ | |
| 308 | /* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ | |
| 309 | #define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ | |
| 310 | #define CONFIG_SYS_DRAM_TEST_DATA | |
| 311 | #define CONFIG_SYS_DRAM_TEST_ADDRESS | |
| 312 | #define CONFIG_SYS_DRAM_TEST_WALK | |
| 313 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
| 3a473b2a WD |
314 | |
| 315 | #undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ | |
| 6d0f6bcf | 316 | #undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ |
| 3a473b2a | 317 | |
| 6d0f6bcf | 318 | #define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ |
| 3a473b2a | 319 | |
| 6d0f6bcf | 320 | #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ |
| 3a473b2a | 321 | /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ |
| ee80fa7b | 322 | #define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ |
| 3a473b2a | 323 | |
| 6d0f6bcf JCPV |
324 | #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ |
| 325 | #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */ | |
| 3a473b2a WD |
326 | |
| 327 | /*ronen - this is the Tclk (MV64360 core) */ | |
| 6d0f6bcf | 328 | #define CONFIG_SYS_TCLK 133000000 |
| 3a473b2a WD |
329 | |
| 330 | ||
| 6d0f6bcf | 331 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
| 3a473b2a | 332 | |
| 6d0f6bcf JCPV |
333 | #define CONFIG_SYS_750FX_HID0 0x8000c084 |
| 334 | #define CONFIG_SYS_750FX_HID1 0x54800000 | |
| 335 | #define CONFIG_SYS_750FX_HID2 0x00000000 | |
| 3a473b2a WD |
336 | |
| 337 | /* | |
| 338 | * Low Level Configuration Settings | |
| 339 | * (address mappings, register initial values, etc.) | |
| 340 | * You should know what you are doing if you make changes here. | |
| 341 | */ | |
| 342 | ||
| 343 | /*----------------------------------------------------------------------- | |
| 344 | * Definitions for initial stack pointer and data area | |
| 345 | */ | |
| 346 | ||
| 347 | /* | |
| 6d0f6bcf | 348 | * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS |
| 3a473b2a WD |
349 | * To an unused memory region. The stack will remain in cache until RAM |
| 350 | * is initialized | |
| 351 | */ | |
| 6d0f6bcf JCPV |
352 | #define CONFIG_SYS_INIT_RAM_LOCK |
| 353 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */ | |
| 553f0982 | 354 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
| 25ddd1fb | 355 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 3a473b2a WD |
356 | |
| 357 | #define RELOCATE_INTERNAL_RAM_ADDR | |
| 358 | #ifdef RELOCATE_INTERNAL_RAM_ADDR | |
| 6d0f6bcf | 359 | #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000 |
| 3a473b2a WD |
360 | #endif |
| 361 | ||
| 362 | /*----------------------------------------------------------------------- | |
| 363 | * Start addresses for the final memory configuration | |
| 364 | * (Set up by the startup code) | |
| 6d0f6bcf | 365 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 3a473b2a | 366 | */ |
| 6d0f6bcf | 367 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 3a473b2a | 368 | /* Dummies for BAT 4-7 */ |
| 6d0f6bcf JCPV |
369 | #define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ |
| 370 | #define CONFIG_SYS_SDRAM2_BASE 0x20000000 | |
| 371 | #define CONFIG_SYS_SDRAM3_BASE 0x30000000 | |
| 372 | #define CONFIG_SYS_SDRAM4_BASE 0x40000000 | |
| 373 | #define CONFIG_SYS_FLASH_BASE 0xfff00000 | |
| 3a473b2a | 374 | |
| 6d0f6bcf | 375 | #define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000 |
| 3a473b2a WD |
376 | #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ |
| 377 | ||
| 378 | #define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ | |
| 379 | #define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ | |
| 380 | #define PCI0_IO_BASE_BOOTM 0xfd000000 | |
| 381 | ||
| 6d0f6bcf JCPV |
382 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 |
| 383 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 384 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
| 385 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ | |
| 3a473b2a WD |
386 | |
| 387 | /* areas to map different things with the GT in physical space */ | |
| 6d0f6bcf | 388 | #define CONFIG_SYS_DRAM_BANKS 4 |
| 3a473b2a WD |
389 | |
| 390 | /* What to put in the bats. */ | |
| 6d0f6bcf | 391 | #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 |
| 3a473b2a WD |
392 | |
| 393 | /* Peripheral Device section */ | |
| 394 | ||
| 395 | /*******************************************************/ | |
| 396 | /* We have on the db64360 Board : */ | |
| 397 | /* GT-Chipset Register Area */ | |
| 398 | /* GT-Chipset internal SRAM 256k */ | |
| 399 | /* SRAM on external device module */ | |
| 400 | /* Real time clock on external device module */ | |
| 401 | /* dobble UART on external device module */ | |
| 402 | /* Data flash on external device module */ | |
| 403 | /* Boot flash on external device module */ | |
| 404 | /*******************************************************/ | |
| 6d0f6bcf JCPV |
405 | #define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ |
| 406 | #define CONFIG_SYS_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */ | |
| 3a473b2a WD |
407 | |
| 408 | /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ | |
| 6d0f6bcf JCPV |
409 | #define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ |
| 410 | #define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */ | |
| 411 | ||
| 412 | #define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */ | |
| 413 | #define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ | |
| 414 | #define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ | |
| 415 | #define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */ | |
| 416 | ||
| 417 | #define CONFIG_SYS_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */ | |
| 418 | #define CONFIG_SYS_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */ | |
| 419 | #define CONFIG_SYS_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */ | |
| 420 | #define CONFIG_SYS_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */ | |
| 3a473b2a WD |
421 | /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ |
| 422 | ||
| 423 | /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ | |
| 6d0f6bcf JCPV |
424 | #define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ |
| 425 | #define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ | |
| 426 | #define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ | |
| 427 | #define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ | |
| 428 | #define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ | |
| 3a473b2a WD |
429 | |
| 430 | /* c 4 a 8 2 4 1 c */ | |
| 431 | /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ | |
| 432 | /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ | |
| 433 | /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ | |
| 434 | /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ | |
| 435 | ||
| 436 | ||
| 437 | /* ronen - update MPP Control MV64360*/ | |
| 6d0f6bcf JCPV |
438 | #define CONFIG_SYS_MPP_CONTROL_0 0x02222222 |
| 439 | #define CONFIG_SYS_MPP_CONTROL_1 0x11333011 | |
| 440 | #define CONFIG_SYS_MPP_CONTROL_2 0x40431111 | |
| 441 | #define CONFIG_SYS_MPP_CONTROL_3 0x00000044 | |
| 3a473b2a | 442 | |
| 6d0f6bcf | 443 | /*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ |
| 3a473b2a WD |
444 | |
| 445 | ||
| 6d0f6bcf | 446 | # define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ |
| 3a473b2a WD |
447 | /* gpp[31] gpp[30] gpp[29] gpp[28] */ |
| 448 | /* gpp[27] gpp[24]*/ | |
| 449 | /* gpp[19:14] */ | |
| 450 | ||
| 451 | /* setup new config_value for MV64360 DDR-RAM !! */ | |
| 6d0f6bcf | 452 | # define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ |
| 3a473b2a | 453 | |
| 6d0f6bcf JCPV |
454 | #define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE |
| 455 | #define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ | |
| 456 | #define CONFIG_SYS_INIT_CHAN1 | |
| 457 | #define CONFIG_SYS_INIT_CHAN2 | |
| 3a473b2a | 458 | |
| 6d0f6bcf | 459 | #define SRAM_BASE CONFIG_SYS_DEV0_SPACE |
| 3a473b2a WD |
460 | #define SRAM_SIZE 0x00100000 /* 1 MB of sram */ |
| 461 | ||
| 462 | ||
| 463 | /*----------------------------------------------------------------------- | |
| 464 | * PCI stuff | |
| 465 | *----------------------------------------------------------------------- | |
| 466 | */ | |
| 467 | ||
| 468 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ | |
| 469 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
| 470 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
| 471 | ||
| 472 | #define CONFIG_PCI /* include pci support */ | |
| 473 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
| 474 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 475 | #define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ | |
| 476 | ||
| 477 | /* PCI MEMORY MAP section */ | |
| 6d0f6bcf JCPV |
478 | #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 |
| 479 | #define CONFIG_SYS_PCI0_MEM_SIZE _128M | |
| 480 | #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 | |
| 481 | #define CONFIG_SYS_PCI1_MEM_SIZE _128M | |
| 3a473b2a | 482 | |
| 6d0f6bcf JCPV |
483 | #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) |
| 484 | #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) | |
| 3a473b2a WD |
485 | |
| 486 | /* PCI I/O MAP section */ | |
| 6d0f6bcf JCPV |
487 | #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 |
| 488 | #define CONFIG_SYS_PCI0_IO_SIZE _16M | |
| 489 | #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 | |
| 490 | #define CONFIG_SYS_PCI1_IO_SIZE _16M | |
| 3a473b2a | 491 | |
| 6d0f6bcf JCPV |
492 | #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) |
| 493 | #define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ | |
| 494 | #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) | |
| 495 | #define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ | |
| 3a473b2a WD |
496 | |
| 497 | #if defined (CONFIG_750CX) | |
| 6d0f6bcf | 498 | #define CONFIG_SYS_PCI_IDSEL 0x0 |
| 3a473b2a | 499 | #else |
| 6d0f6bcf | 500 | #define CONFIG_SYS_PCI_IDSEL 0x30 |
| 3a473b2a WD |
501 | #endif |
| 502 | /*---------------------------------------------------------------------- | |
| 503 | * Initial BAT mappings | |
| 504 | */ | |
| 505 | ||
| 506 | /* NOTES: | |
| 507 | * 1) GUARDED and WRITE_THRU not allowed in IBATS | |
| 508 | * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT | |
| 509 | */ | |
| 510 | ||
| 511 | /* SDRAM */ | |
| 6d0f6bcf JCPV |
512 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 513 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 514 | #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 515 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| 3a473b2a WD |
516 | |
| 517 | /* init ram */ | |
| 6d0f6bcf JCPV |
518 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 519 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) | |
| 520 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 521 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| 3a473b2a WD |
522 | |
| 523 | /* PCI0, PCI1 in one BAT */ | |
| 6d0f6bcf JCPV |
524 | #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS |
| 525 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
| 526 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
| 527 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 3a473b2a WD |
528 | |
| 529 | /* GT regs, bootrom, all the devices, PCI I/O */ | |
| 6d0f6bcf JCPV |
530 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) |
| 531 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) | |
| 532 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
| 533 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| 3a473b2a WD |
534 | |
| 535 | /* I2C addresses for the two DIMM SPD chips */ | |
| 536 | #define DIMM0_I2C_ADDR 0x56 | |
| 537 | #define DIMM1_I2C_ADDR 0x54 | |
| 538 | ||
| 539 | /* | |
| 540 | * For booting Linux, the board info and command line data | |
| 541 | * have to be in the first 8 MB of memory, since this is | |
| 542 | * the maximum mapped by the Linux kernel during initialization. | |
| 543 | */ | |
| 6d0f6bcf | 544 | #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ |
| 3a473b2a WD |
545 | |
| 546 | /*----------------------------------------------------------------------- | |
| 547 | * FLASH organization | |
| 548 | */ | |
| 6d0f6bcf JCPV |
549 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| 550 | #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ | |
| 3a473b2a | 551 | |
| 6d0f6bcf JCPV |
552 | #define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ |
| 553 | #define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ | |
| 554 | #define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */ | |
| 3a473b2a | 555 | |
| 6d0f6bcf JCPV |
556 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 557 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 558 | #define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ | |
| 559 | #define CONFIG_SYS_FLASH_CFI 1 | |
| 3a473b2a | 560 | |
| 5a1aceb0 | 561 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 0e8d1586 JCPV |
562 | #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
| 563 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 564 | #define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ | |
| 6d0f6bcf | 565 | /* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ |
| 3a473b2a WD |
566 | |
| 567 | /*----------------------------------------------------------------------- | |
| 568 | * Cache Configuration | |
| 569 | */ | |
| 6d0f6bcf | 570 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ |
| 3c3227f3 | 571 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 572 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 3a473b2a WD |
573 | #endif |
| 574 | ||
| 575 | /*----------------------------------------------------------------------- | |
| 576 | * L2CR setup -- make sure this is right for your board! | |
| 577 | * look in include/mpc74xx.h for the defines used here | |
| 578 | */ | |
| 579 | ||
| 6d0f6bcf | 580 | #define CONFIG_SYS_L2 |
| 3a473b2a WD |
581 | |
| 582 | ||
| 583 | #if defined (CONFIG_750CX) || defined (CONFIG_750FX) | |
| 584 | #define L2_INIT 0 | |
| 585 | #else | |
| 586 | ||
| 587 | #define L2_INIT 0 | |
| 588 | /* | |
| 589 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ | |
| 590 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) | |
| 591 | */ | |
| 592 | #endif | |
| 593 | ||
| 594 | #define L2_ENABLE (L2_INIT | L2CR_L2E) | |
| 595 | ||
| 6d0f6bcf | 596 | #define CONFIG_SYS_BOARD_ASM_INIT 1 |
| 3a473b2a WD |
597 | |
| 598 | #endif /* __CONFIG_H */ |