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3a473b2a WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
3a473b2a WD |
31 | /* This define must be before the core.h include */ |
32 | #define CONFIG_DB64460 1 /* this is an DB64460 board */ | |
33 | ||
34 | #ifndef __ASSEMBLY__ | |
35 | #include "../board/Marvell/include/core.h" | |
36 | #endif | |
37 | ||
38 | /*-----------------------------------------------------*/ | |
39 | /* #include "../board/db64460/local.h" */ | |
40 | #ifndef __LOCAL_H | |
41 | #define __LOCAL_H | |
42 | ||
43 | #define CONFIG_ETHADDR 64:46:00:00:00:01 | |
e2ffd59b | 44 | #define CONFIG_HAS_ETH1 |
3a473b2a | 45 | #define CONFIG_ETH1ADDR 64:46:00:00:00:02 |
e2ffd59b | 46 | #define CONFIG_HAS_ETH2 |
3a473b2a WD |
47 | #define CONFIG_ETH2ADDR 64:46:00:00:00:03 |
48 | ||
49 | #define CONFIG_ENV_OVERWRITE | |
50 | #endif /* __CONFIG_H */ | |
51 | ||
52 | /* | |
53 | * High Level Configuration Options | |
54 | * (easy to change) | |
55 | */ | |
56 | ||
57 | #define CONFIG_74xx /* we have a 750FX (override local.h) */ | |
58 | ||
59 | #define CONFIG_DB64460 1 /* this is an DB64460 board */ | |
60 | ||
61 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ | |
62 | /*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the | |
63 | DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. | |
64 | so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, | |
65 | see sdram_init.c */ | |
66 | #undef CONFIG_ECC /* enable ECC support */ | |
67 | #define CONFIG_MV64460_ECC | |
68 | ||
69 | /* which initialization functions to call for this board */ | |
70 | #define CONFIG_MISC_INIT_R /* initialize the icache L1 */ | |
c837dcb1 | 71 | #define CONFIG_BOARD_EARLY_INIT_F |
3a473b2a | 72 | |
6d0f6bcf | 73 | #define CONFIG_SYS_BOARD_NAME "DB64460" |
3a473b2a WD |
74 | #define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)" |
75 | ||
6d0f6bcf JCPV |
76 | /*#define CONFIG_SYS_HUSH_PARSER */ |
77 | #undef CONFIG_SYS_HUSH_PARSER | |
3a473b2a | 78 | |
6d0f6bcf | 79 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
3a473b2a WD |
80 | |
81 | /* | |
82 | * The following defines let you select what serial you want to use | |
83 | * for your console driver. | |
84 | * | |
85 | * what to do: | |
86 | * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial | |
6d0f6bcf | 87 | * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 |
3a473b2a WD |
88 | * to 0 below. |
89 | * | |
90 | * to use the MPSC, #define CONFIG_MPSC. If you have wired up another | |
91 | * mpsc channel, change CONFIG_MPSC_PORT to the desired value. | |
92 | */ | |
93 | ||
94 | #define CONFIG_MPSC_PORT 0 | |
95 | ||
96 | /* to change the default ethernet port, use this define (options: 0, 1, 2) */ | |
97 | #define CONFIG_NET_MULTI | |
98 | #define MV_ETH_DEVS 3 | |
99 | ||
100 | /* #undef CONFIG_ETHER_PORT_MII */ | |
101 | #if 0 | |
102 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
103 | #else | |
104 | #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ | |
105 | #endif | |
106 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
107 | ||
108 | ||
109 | #undef CONFIG_BOOTARGS | |
32bf3d14 | 110 | /*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ |
3a473b2a WD |
111 | |
112 | /* ronen - autoboot using tftp */ | |
113 | #if (CONFIG_BOOTDELAY >= 0) | |
114 | #define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ | |
fe126d8b WD |
115 | setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ |
116 | ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " | |
3a473b2a WD |
117 | |
118 | #define CONFIG_BOOTARGS "console=ttyS0,115200" | |
119 | ||
120 | #endif | |
121 | ||
122 | /* ronen - the u-boot.bin should be ~0x30000 bytes */ | |
123 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
124 | "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ | |
125 | cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ | |
126 | "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ | |
127 | cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ | |
128 | "bootargs_root=root=/dev/nfs rw\0" \ | |
129 | "bootargs_end=:::DB64460:eth0:none \0"\ | |
130 | "ethprime=mv_enet0\0"\ | |
fe126d8b WD |
131 | "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ |
132 | ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" | |
3a473b2a WD |
133 | |
134 | /* --------------------------------------------------------------------------------------------------------------- */ | |
135 | /* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */ | |
136 | ||
137 | #define CONFIG_IPADDR 10.2.40.90 | |
138 | ||
139 | #define CONFIG_SERIAL "No. 1" | |
140 | #define CONFIG_SERVERIP 10.2.1.126 | |
141 | #define CONFIG_ROOTPATH /mnt/yellow_dog_mini | |
142 | ||
143 | ||
144 | #define CONFIG_TESTDRAMDATA y | |
145 | #define CONFIG_TESTDRAMADDRESS n | |
146 | #define CONFIG_TESETDRAMWALK n | |
147 | ||
148 | /* --------------------------------------------------------------------------------------------------------------- */ | |
149 | ||
150 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ | |
6d0f6bcf | 151 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ |
3a473b2a WD |
152 | |
153 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
154 | #undef CONFIG_ALTIVEC /* undef to disable */ | |
155 | ||
5d2ebe1b JL |
156 | /* |
157 | * BOOTP options | |
158 | */ | |
159 | #define CONFIG_BOOTP_SUBNETMASK | |
160 | #define CONFIG_BOOTP_GATEWAY | |
161 | #define CONFIG_BOOTP_HOSTNAME | |
162 | #define CONFIG_BOOTP_BOOTPATH | |
163 | #define CONFIG_BOOTP_BOOTFILESIZE | |
164 | ||
165 | ||
700a0c64 WD |
166 | /* |
167 | * JFFS2 partitions | |
168 | * | |
169 | */ | |
170 | /* No command line, one static partition, whole device */ | |
68d7d651 | 171 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
172 | #define CONFIG_JFFS2_DEV "nor1" |
173 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
174 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
3a473b2a | 175 | |
700a0c64 WD |
176 | /* mtdparts command line support */ |
177 | ||
178 | /* Use first bank for JFFS2, second bank contains U-Boot. | |
179 | * | |
180 | * Note: fake mtd_id's used, no linux mtd map file. | |
181 | */ | |
182 | /* | |
68d7d651 | 183 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
184 | #define MTDIDS_DEFAULT "nor1=db64460-1" |
185 | #define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)" | |
186 | */ | |
3a473b2a | 187 | |
3c3227f3 JL |
188 | |
189 | /* | |
190 | * Command line configuration. | |
191 | */ | |
192 | #include <config_cmd_default.h> | |
193 | ||
194 | #define CONFIG_CMD_ASKENV | |
195 | #define CONFIG_CMD_I2C | |
196 | #define CONFIG_CMD_EEPROM | |
197 | #define CONFIG_CMD_CACHE | |
198 | #define CONFIG_CMD_JFFS2 | |
199 | #define CONFIG_CMD_PCI | |
200 | #define CONFIG_CMD_NET | |
201 | ||
3a473b2a WD |
202 | |
203 | /* | |
204 | * Miscellaneous configurable options | |
205 | */ | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
207 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
208 | #define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */ | |
3a473b2a | 209 | |
6d0f6bcf JCPV |
210 | /* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */ |
211 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
212 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
3c3227f3 | 213 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 214 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
3a473b2a | 215 | #else |
6d0f6bcf | 216 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
3a473b2a | 217 | #endif |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
219 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
220 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
3a473b2a | 221 | |
6d0f6bcf JCPV |
222 | /*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */ |
223 | /*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ | |
224 | /*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ | |
3a473b2a WD |
225 | |
226 | /* | |
6d0f6bcf | 227 | #define CONFIG_SYS_DRAM_TEST |
3a473b2a | 228 | * DRAM tests |
6d0f6bcf | 229 | * CONFIG_SYS_DRAM_TEST - enables the following tests. |
3a473b2a | 230 | * |
6d0f6bcf | 231 | * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines |
3a473b2a WD |
232 | * Environment variable 'test_dram_data' must be |
233 | * set to 'y'. | |
6d0f6bcf | 234 | * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely |
3a473b2a WD |
235 | * addressable. Environment variable |
236 | * 'test_dram_address' must be set to 'y'. | |
6d0f6bcf | 237 | * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. |
3a473b2a WD |
238 | * This test takes about 6 minutes to test 64 MB. |
239 | * Environment variable 'test_dram_walk' must be | |
240 | * set to 'y'. | |
241 | */ | |
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_DRAM_TEST |
243 | #if defined(CONFIG_SYS_DRAM_TEST) | |
244 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ | |
245 | /* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ | |
246 | #define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ | |
247 | #define CONFIG_SYS_DRAM_TEST_DATA | |
248 | #define CONFIG_SYS_DRAM_TEST_ADDRESS | |
249 | #define CONFIG_SYS_DRAM_TEST_WALK | |
250 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
3a473b2a WD |
251 | |
252 | #undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ | |
6d0f6bcf | 253 | #undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ |
3a473b2a | 254 | |
6d0f6bcf | 255 | #define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ |
3a473b2a | 256 | |
6d0f6bcf | 257 | #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ |
3a473b2a | 258 | /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ |
ee80fa7b | 259 | #define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ |
3a473b2a | 260 | |
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ |
262 | #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */ | |
3a473b2a WD |
263 | |
264 | /*ronen - this is the Tclk (MV64460 core) */ | |
6d0f6bcf | 265 | #define CONFIG_SYS_TCLK 133000000 |
3a473b2a WD |
266 | |
267 | ||
6d0f6bcf | 268 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
3a473b2a | 269 | |
6d0f6bcf JCPV |
270 | #define CONFIG_SYS_750FX_HID0 0x8000c084 |
271 | #define CONFIG_SYS_750FX_HID1 0x54800000 | |
272 | #define CONFIG_SYS_750FX_HID2 0x00000000 | |
3a473b2a WD |
273 | |
274 | /* | |
275 | * Low Level Configuration Settings | |
276 | * (address mappings, register initial values, etc.) | |
277 | * You should know what you are doing if you make changes here. | |
278 | */ | |
279 | ||
280 | /*----------------------------------------------------------------------- | |
281 | * Definitions for initial stack pointer and data area | |
282 | */ | |
283 | ||
284 | /* | |
6d0f6bcf | 285 | * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS |
3a473b2a WD |
286 | * To an unused memory region. The stack will remain in cache until RAM |
287 | * is initialized | |
288 | */ | |
6d0f6bcf JCPV |
289 | #define CONFIG_SYS_INIT_RAM_LOCK |
290 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */ | |
291 | #define CONFIG_SYS_INIT_RAM_END 0x1000 | |
292 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ | |
293 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
3a473b2a WD |
294 | |
295 | #define RELOCATE_INTERNAL_RAM_ADDR | |
296 | #ifdef RELOCATE_INTERNAL_RAM_ADDR | |
6d0f6bcf | 297 | #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000 |
3a473b2a WD |
298 | #endif |
299 | ||
300 | /*----------------------------------------------------------------------- | |
301 | * Start addresses for the final memory configuration | |
302 | * (Set up by the startup code) | |
6d0f6bcf | 303 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
3a473b2a | 304 | */ |
6d0f6bcf | 305 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
3a473b2a | 306 | /* Dummies for BAT 4-7 */ |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ |
308 | #define CONFIG_SYS_SDRAM2_BASE 0x20000000 | |
309 | #define CONFIG_SYS_SDRAM3_BASE 0x30000000 | |
310 | #define CONFIG_SYS_SDRAM4_BASE 0x40000000 | |
311 | #define CONFIG_SYS_FLASH_BASE 0xfff00000 | |
3a473b2a | 312 | |
6d0f6bcf | 313 | #define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000 |
3a473b2a WD |
314 | #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ |
315 | ||
316 | #define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ | |
317 | #define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ | |
318 | #define PCI0_IO_BASE_BOOTM 0xfd000000 | |
319 | ||
6d0f6bcf JCPV |
320 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 |
321 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
322 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
323 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ | |
3a473b2a WD |
324 | |
325 | /* areas to map different things with the GT in physical space */ | |
6d0f6bcf | 326 | #define CONFIG_SYS_DRAM_BANKS 4 |
3a473b2a WD |
327 | |
328 | /* What to put in the bats. */ | |
6d0f6bcf | 329 | #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 |
3a473b2a WD |
330 | |
331 | /* Peripheral Device section */ | |
332 | ||
333 | /*******************************************************/ | |
334 | /* We have on the db64460 Board : */ | |
335 | /* GT-Chipset Register Area */ | |
336 | /* GT-Chipset internal SRAM 256k */ | |
337 | /* SRAM on external device module */ | |
338 | /* Real time clock on external device module */ | |
339 | /* dobble UART on external device module */ | |
340 | /* Data flash on external device module */ | |
341 | /* Boot flash on external device module */ | |
342 | /*******************************************************/ | |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ |
344 | #define CONFIG_SYS_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */ | |
3a473b2a WD |
345 | |
346 | /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ | |
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ |
348 | #define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */ | |
349 | ||
350 | #define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */ | |
351 | #define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ | |
352 | #define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ | |
353 | #define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */ | |
354 | ||
355 | #define CONFIG_SYS_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */ | |
356 | #define CONFIG_SYS_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */ | |
357 | #define CONFIG_SYS_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */ | |
358 | #define CONFIG_SYS_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */ | |
3a473b2a WD |
359 | /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ |
360 | ||
361 | /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ | |
6d0f6bcf JCPV |
362 | #define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ |
363 | #define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ | |
364 | #define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ | |
365 | #define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ | |
366 | #define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ | |
3a473b2a WD |
367 | |
368 | /* c 4 a 8 2 4 1 c */ | |
369 | /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ | |
370 | /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ | |
371 | /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ | |
372 | /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ | |
373 | ||
374 | ||
375 | /* ronen - update MPP Control MV64460*/ | |
6d0f6bcf JCPV |
376 | #define CONFIG_SYS_MPP_CONTROL_0 0x02222222 |
377 | #define CONFIG_SYS_MPP_CONTROL_1 0x11333011 | |
378 | #define CONFIG_SYS_MPP_CONTROL_2 0x40431111 | |
379 | #define CONFIG_SYS_MPP_CONTROL_3 0x00000044 | |
3a473b2a | 380 | |
6d0f6bcf | 381 | /*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ |
3a473b2a WD |
382 | |
383 | ||
6d0f6bcf | 384 | # define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ |
3a473b2a WD |
385 | /* gpp[31] gpp[30] gpp[29] gpp[28] */ |
386 | /* gpp[27] gpp[24]*/ | |
387 | /* gpp[19:14] */ | |
388 | ||
389 | /* setup new config_value for MV64460 DDR-RAM !! */ | |
6d0f6bcf | 390 | # define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ |
3a473b2a | 391 | |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE |
393 | #define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ | |
394 | #define CONFIG_SYS_INIT_CHAN1 | |
395 | #define CONFIG_SYS_INIT_CHAN2 | |
3a473b2a | 396 | |
6d0f6bcf | 397 | #define SRAM_BASE CONFIG_SYS_DEV0_SPACE |
3a473b2a WD |
398 | #define SRAM_SIZE 0x00100000 /* 1 MB of sram */ |
399 | ||
400 | ||
401 | /*----------------------------------------------------------------------- | |
402 | * PCI stuff | |
403 | *----------------------------------------------------------------------- | |
404 | */ | |
405 | ||
406 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ | |
407 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
408 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
409 | ||
410 | #define CONFIG_PCI /* include pci support */ | |
411 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
412 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
413 | #define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ | |
414 | ||
415 | /* PCI MEMORY MAP section */ | |
6d0f6bcf JCPV |
416 | #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 |
417 | #define CONFIG_SYS_PCI0_MEM_SIZE _128M | |
418 | #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 | |
419 | #define CONFIG_SYS_PCI1_MEM_SIZE _128M | |
3a473b2a | 420 | |
6d0f6bcf JCPV |
421 | #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) |
422 | #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) | |
3a473b2a WD |
423 | |
424 | /* PCI I/O MAP section */ | |
6d0f6bcf JCPV |
425 | #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 |
426 | #define CONFIG_SYS_PCI0_IO_SIZE _16M | |
427 | #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 | |
428 | #define CONFIG_SYS_PCI1_IO_SIZE _16M | |
3a473b2a | 429 | |
6d0f6bcf JCPV |
430 | #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) |
431 | #define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ | |
432 | #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) | |
433 | #define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ | |
3a473b2a WD |
434 | |
435 | #if defined (CONFIG_750CX) | |
6d0f6bcf | 436 | #define CONFIG_SYS_PCI_IDSEL 0x0 |
3a473b2a | 437 | #else |
6d0f6bcf | 438 | #define CONFIG_SYS_PCI_IDSEL 0x30 |
3a473b2a WD |
439 | #endif |
440 | /*---------------------------------------------------------------------- | |
441 | * Initial BAT mappings | |
442 | */ | |
443 | ||
444 | /* NOTES: | |
445 | * 1) GUARDED and WRITE_THRU not allowed in IBATS | |
446 | * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT | |
447 | */ | |
448 | ||
449 | /* SDRAM */ | |
6d0f6bcf JCPV |
450 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
451 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
452 | #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
453 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
3a473b2a WD |
454 | |
455 | /* init ram */ | |
6d0f6bcf JCPV |
456 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
457 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) | |
458 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
459 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
3a473b2a WD |
460 | |
461 | /* PCI0, PCI1 in one BAT */ | |
6d0f6bcf JCPV |
462 | #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS |
463 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
464 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
465 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
3a473b2a WD |
466 | |
467 | /* GT regs, bootrom, all the devices, PCI I/O */ | |
6d0f6bcf JCPV |
468 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) |
469 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) | |
470 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
471 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
3a473b2a WD |
472 | |
473 | /* I2C addresses for the two DIMM SPD chips */ | |
474 | #define DIMM0_I2C_ADDR 0x56 | |
475 | #define DIMM1_I2C_ADDR 0x54 | |
476 | ||
477 | /* | |
478 | * For booting Linux, the board info and command line data | |
479 | * have to be in the first 8 MB of memory, since this is | |
480 | * the maximum mapped by the Linux kernel during initialization. | |
481 | */ | |
6d0f6bcf | 482 | #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ |
3a473b2a WD |
483 | |
484 | /*----------------------------------------------------------------------- | |
485 | * FLASH organization | |
486 | */ | |
6d0f6bcf JCPV |
487 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
488 | #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ | |
3a473b2a | 489 | |
6d0f6bcf JCPV |
490 | #define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ |
491 | #define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ | |
492 | #define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */ | |
3a473b2a | 493 | |
6d0f6bcf JCPV |
494 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
495 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
496 | #define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ | |
497 | #define CONFIG_SYS_FLASH_CFI 1 | |
3a473b2a | 498 | |
5a1aceb0 | 499 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
500 | #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
501 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
502 | #define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ | |
6d0f6bcf | 503 | /* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ |
3a473b2a WD |
504 | |
505 | /*----------------------------------------------------------------------- | |
506 | * Cache Configuration | |
507 | */ | |
6d0f6bcf | 508 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ |
3c3227f3 | 509 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 510 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
3a473b2a WD |
511 | #endif |
512 | ||
513 | /*----------------------------------------------------------------------- | |
514 | * L2CR setup -- make sure this is right for your board! | |
515 | * look in include/mpc74xx.h for the defines used here | |
516 | */ | |
517 | ||
6d0f6bcf | 518 | #define CONFIG_SYS_L2 |
3a473b2a WD |
519 | |
520 | ||
521 | #if defined (CONFIG_750CX) || defined (CONFIG_750FX) | |
522 | #define L2_INIT 0 | |
523 | #else | |
524 | ||
525 | #define L2_INIT 0 | |
526 | /* | |
527 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ | |
528 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) | |
529 | */ | |
530 | #endif | |
531 | ||
532 | #define L2_ENABLE (L2_INIT | L2CR_L2E) | |
533 | ||
534 | /* | |
535 | * Internal Definitions | |
536 | * | |
537 | * Boot Flags | |
538 | */ | |
539 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
540 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
541 | ||
6d0f6bcf | 542 | #define CONFIG_SYS_BOARD_ASM_INIT 1 |
3a473b2a WD |
543 | |
544 | #endif /* __CONFIG_H */ |