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4a551709 WD |
1 | /* |
2 | * (C) Copyright 2003, Psyent Corporation <www.psyent.com> | |
3 | * Scott McNutt <smcnutt@psyent.com> | |
c935d3bd | 4 | * Stephan Linz <linz@li-pro.net> |
4a551709 | 5 | * |
d06a5f7e WD |
6 | * CompactFlash/IDE: |
7 | * (C) Copyright 2004, Shlomo Kut <skut@vyyo.com> | |
8 | * | |
4a551709 WD |
9 | * See file CREDITS for list of people who contributed to this |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
ec4c544b WD |
31 | /*********************************************************************** |
32 | * Include the whole NIOS CPU configuration. | |
c935d3bd | 33 | * |
ec4c544b | 34 | * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! |
c935d3bd | 35 | * |
ec4c544b | 36 | ***********************************************************************/ |
c935d3bd WD |
37 | |
38 | #if defined(CONFIG_NIOS_SAFE_32) | |
ec4c544b | 39 | #include <configs/DK1C20_safe_32.h> |
c935d3bd | 40 | #elif defined(CONFIG_NIOS_STANDARD_32) |
ec4c544b | 41 | #include <configs/DK1C20_standard_32.h> |
c935d3bd | 42 | #else |
6d0f6bcf | 43 | #error *** CONFIG_SYS_ERROR: you have to setup right NIOS CPU configuration |
c935d3bd WD |
44 | #endif |
45 | ||
4a551709 WD |
46 | /*------------------------------------------------------------------------ |
47 | * BOARD/CPU -- TOP-LEVEL | |
48 | *----------------------------------------------------------------------*/ | |
49 | #define CONFIG_NIOS 1 /* NIOS-32 core */ | |
50 | #define CONFIG_DK1C20 1 /* Cyclone DK-1C20 board*/ | |
6d0f6bcf JCPV |
51 | #define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */ |
52 | #define CONFIG_SYS_HZ 1000 /* 1 msec time tick */ | |
c837dcb1 | 53 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ |
4a551709 WD |
54 | |
55 | /*------------------------------------------------------------------------ | |
c935d3bd | 56 | * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) |
4a551709 | 57 | *----------------------------------------------------------------------*/ |
6d0f6bcf | 58 | #if (CONFIG_SYS_NIOS_CPU_SDRAM_SIZE != 0) |
c935d3bd | 59 | |
6d0f6bcf JCPV |
60 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_NIOS_CPU_SDRAM_BASE |
61 | #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_NIOS_CPU_SDRAM_SIZE | |
c935d3bd WD |
62 | |
63 | #else | |
6d0f6bcf | 64 | #error *** CONFIG_SYS_ERROR: you have to setup any SDRAM in NIOS CPU config |
c935d3bd WD |
65 | #endif |
66 | ||
6d0f6bcf JCPV |
67 | #define CONFIG_SYS_SRAM_BASE CONFIG_SYS_NIOS_CPU_SRAM_BASE |
68 | #define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_NIOS_CPU_SRAM_SIZE | |
69 | #define CONFIG_SYS_VECT_BASE CONFIG_SYS_NIOS_CPU_VEC_BASE | |
4a551709 WD |
70 | |
71 | /*------------------------------------------------------------------------ | |
72 | * MEMORY ORGANIZATION - For the most part, you can put things pretty | |
73 | * much anywhere. This is pretty flexible for Nios. So here we make some | |
74 | * arbitrary choices & assume that the monitor is placed at the end of | |
75 | * a memory resource (so you must make sure TEXT_BASE is chosen | |
76 | * appropriately). | |
77 | * | |
53677ef1 WD |
78 | * -The heap is placed below the monitor. |
79 | * -Global data is placed below the heap. | |
80 | * -The stack is placed below global data (&grows down). | |
4a551709 | 81 | *----------------------------------------------------------------------*/ |
6d0f6bcf JCPV |
82 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ |
83 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ | |
84 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) | |
4a551709 | 85 | |
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
87 | #define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) | |
88 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) | |
89 | #define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET | |
4a551709 WD |
90 | |
91 | /*------------------------------------------------------------------------ | |
c935d3bd | 92 | * FLASH (AM29LV065D) |
4a551709 | 93 | *----------------------------------------------------------------------*/ |
6d0f6bcf | 94 | #if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) |
c935d3bd | 95 | |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_NIOS_CPU_FLASH_BASE |
97 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_NIOS_CPU_FLASH_SIZE | |
98 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ | |
99 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ | |
100 | #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ | |
101 | #define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ | |
102 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ | |
c935d3bd WD |
103 | |
104 | #else | |
6d0f6bcf | 105 | #error *** CONFIG_SYS_ERROR: you have to setup any Flash memory in NIOS CPU config |
c935d3bd | 106 | #endif |
4a551709 WD |
107 | |
108 | /*------------------------------------------------------------------------ | |
109 | * ENVIRONMENT | |
110 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 111 | #if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) |
c935d3bd | 112 | |
5a1aceb0 | 113 | #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ |
6d0f6bcf | 114 | #define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Mem addr of env */ |
0e8d1586 | 115 | #define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ |
4a551709 WD |
116 | #define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ |
117 | ||
c935d3bd | 118 | #else |
93f6d725 | 119 | #define CONFIG_ENV_IS_NOWHERE 1 /* NO Environment */ |
c935d3bd WD |
120 | #endif |
121 | ||
4a551709 WD |
122 | /*------------------------------------------------------------------------ |
123 | * CONSOLE | |
124 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 125 | #if (CONFIG_SYS_NIOS_CPU_UART_NUMS != 0) |
c935d3bd | 126 | |
6d0f6bcf | 127 | #define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_NIOS_CPU_UART0 /* 1st UART is Cons. */ |
c935d3bd | 128 | |
6d0f6bcf JCPV |
129 | #if (CONFIG_SYS_NIOS_CPU_UART0_BR != 0) |
130 | #define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ | |
131 | #define CONFIG_BAUDRATE CONFIG_SYS_NIOS_CPU_UART0_BR | |
c935d3bd | 132 | #else |
6d0f6bcf | 133 | #undef CONFIG_SYS_NIOS_FIXEDBAUD |
4a551709 | 134 | #define CONFIG_BAUDRATE 115200 |
c935d3bd WD |
135 | #endif |
136 | ||
6d0f6bcf | 137 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
c935d3bd WD |
138 | |
139 | #else | |
6d0f6bcf | 140 | #error *** CONFIG_SYS_ERROR: you have to setup at least one UART in NIOS CPU config |
c935d3bd | 141 | #endif |
4a551709 WD |
142 | |
143 | /*------------------------------------------------------------------------ | |
144 | * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, | |
145 | * so an avalon bus timer is required. | |
146 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 147 | #if (CONFIG_SYS_NIOS_CPU_TIMER_NUMS != 0) |
c935d3bd | 148 | |
6d0f6bcf | 149 | #if (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 0) |
c935d3bd | 150 | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER0 /* TIMER0 as tick */ |
152 | #define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER0_IRQ | |
63e73c9a | 153 | |
6d0f6bcf | 154 | #if (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ |
63e73c9a | 155 | |
6d0f6bcf JCPV |
156 | #if (CONFIG_SYS_NIOS_CPU_TIMER0_PER >= CONFIG_SYS_HZ) |
157 | #define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER0_PER / CONFIG_SYS_HZ) | |
63e73c9a | 158 | #else |
6d0f6bcf | 159 | #error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ |
63e73c9a WD |
160 | #endif |
161 | ||
6d0f6bcf | 162 | #undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ |
63e73c9a | 163 | |
6d0f6bcf | 164 | #elif (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 0) /* variable period */ |
63e73c9a | 165 | |
6d0f6bcf JCPV |
166 | #if (CONFIG_SYS_HZ <= 1000) |
167 | #define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) | |
63e73c9a | 168 | #else |
6d0f6bcf | 169 | #error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 |
63e73c9a WD |
170 | #endif |
171 | ||
6d0f6bcf | 172 | #define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) |
63e73c9a WD |
173 | |
174 | #else | |
6d0f6bcf | 175 | #error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER0_FP correct |
63e73c9a | 176 | #endif |
c935d3bd | 177 | |
6d0f6bcf | 178 | #elif (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 1) |
c935d3bd | 179 | |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER1 /* TIMER1 as tick */ |
181 | #define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER1_IRQ | |
c935d3bd | 182 | |
6d0f6bcf | 183 | #if (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ |
63e73c9a | 184 | |
6d0f6bcf JCPV |
185 | #if (CONFIG_SYS_NIOS_CPU_TIMER1_PER >= CONFIG_SYS_HZ) |
186 | #define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER1_PER / CONFIG_SYS_HZ) | |
c935d3bd | 187 | #else |
6d0f6bcf | 188 | #error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ |
63e73c9a WD |
189 | #endif |
190 | ||
6d0f6bcf | 191 | #undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ |
63e73c9a | 192 | |
6d0f6bcf | 193 | #elif (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 0) /* variable period */ |
63e73c9a | 194 | |
6d0f6bcf JCPV |
195 | #if (CONFIG_SYS_HZ <= 1000) |
196 | #define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) | |
63e73c9a | 197 | #else |
6d0f6bcf | 198 | #error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 |
63e73c9a WD |
199 | #endif |
200 | ||
6d0f6bcf | 201 | #define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) |
63e73c9a WD |
202 | |
203 | #else | |
6d0f6bcf | 204 | #error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER1_FP correct |
c935d3bd WD |
205 | #endif |
206 | ||
6d0f6bcf | 207 | #endif /* CONFIG_SYS_NIOS_CPU_TICK_TIMER */ |
c935d3bd WD |
208 | |
209 | #else | |
6d0f6bcf | 210 | #error *** CONFIG_SYS_ERROR: you have to setup at least one TIMER in NIOS CPU config |
c935d3bd | 211 | #endif |
4a551709 WD |
212 | |
213 | /*------------------------------------------------------------------------ | |
180d3f74 | 214 | * Ethernet |
4a551709 | 215 | *----------------------------------------------------------------------*/ |
6d0f6bcf | 216 | #if (CONFIG_SYS_NIOS_CPU_LAN_NUMS == 1) |
c935d3bd | 217 | |
6d0f6bcf | 218 | #if (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ |
c935d3bd | 219 | |
c935d3bd WD |
220 | #define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ |
221 | #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ | |
6d0f6bcf | 222 | #define CONFIG_SMC91111_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) |
c935d3bd | 223 | |
6d0f6bcf | 224 | #if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) |
c935d3bd WD |
225 | #define CONFIG_SMC_USE_32_BIT 1 |
226 | #else /* no */ | |
227 | #undef CONFIG_SMC_USE_32_BIT | |
228 | #endif | |
229 | ||
6d0f6bcf | 230 | #elif (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ |
c935d3bd WD |
231 | |
232 | /********************************************/ | |
233 | /* !!! CS8900 is __not__ tested on NIOS !!! */ | |
234 | /********************************************/ | |
b1c0eaac BW |
235 | #define CONFIG_NET_MULTI |
236 | #define CONFIG_CS8900 /* Using CS8900 */ | |
237 | #define CONFIG_CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + \ | |
238 | CONFIG_SYS_NIOS_CPU_LAN0_OFFS) | |
c935d3bd | 239 | |
6d0f6bcf | 240 | #if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) |
b1c0eaac BW |
241 | #undef CONFIG_CS8900_BUS16 |
242 | #define CONFIG_CS8900_BUS32 | |
c935d3bd | 243 | #else /* no */ |
b1c0eaac BW |
244 | #define CONFIG_CS8900_BUS16 |
245 | #undef CONFIG_CS8900_BUS32 | |
c935d3bd WD |
246 | #endif |
247 | ||
248 | #else | |
6d0f6bcf | 249 | #error *** CONFIG_SYS_ERROR: invalid LAN0 chip type, check your NIOS CPU config |
c935d3bd | 250 | #endif |
4a551709 WD |
251 | |
252 | #define CONFIG_ETHADDR 08:00:3e:26:0a:5b | |
253 | #define CONFIG_NETMASK 255.255.255.0 | |
254 | #define CONFIG_IPADDR 192.168.2.21 | |
255 | #define CONFIG_SERVERIP 192.168.2.16 | |
256 | ||
c935d3bd | 257 | #else |
6d0f6bcf | 258 | #error *** CONFIG_SYS_ERROR: you have to setup just one LAN only or expand your config.h |
c935d3bd WD |
259 | #endif |
260 | ||
261 | /*------------------------------------------------------------------------ | |
262 | * STATUS LEDs | |
263 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 264 | #if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) |
c935d3bd | 265 | |
6d0f6bcf | 266 | #if (CONFIG_SYS_NIOS_CPU_LED_PIO == 0) |
c935d3bd | 267 | |
6d0f6bcf | 268 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO0 not supported, expand your config.h |
c935d3bd | 269 | |
6d0f6bcf | 270 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 1) |
c935d3bd | 271 | |
6d0f6bcf | 272 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO1 not supported, expand your config.h |
c935d3bd | 273 | |
6d0f6bcf | 274 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 2) |
c935d3bd | 275 | |
6d0f6bcf JCPV |
276 | #define STATUS_LED_BASE CONFIG_SYS_NIOS_CPU_PIO2 |
277 | #define STATUS_LED_BITS CONFIG_SYS_NIOS_CPU_PIO2_BITS | |
c935d3bd WD |
278 | #define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ |
279 | ||
6d0f6bcf | 280 | #if (CONFIG_SYS_NIOS_CPU_PIO2_TYPE == 1) |
c935d3bd WD |
281 | #define STATUS_LED_WRONLY 1 |
282 | #else | |
283 | #undef STATUS_LED_WRONLY | |
284 | #endif | |
285 | ||
6d0f6bcf | 286 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 3) |
c935d3bd | 287 | |
6d0f6bcf | 288 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO3 not supported, expand your config.h |
c935d3bd | 289 | |
6d0f6bcf | 290 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 4) |
c935d3bd | 291 | |
6d0f6bcf | 292 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO4 not supported, expand your config.h |
c935d3bd | 293 | |
6d0f6bcf | 294 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 5) |
c935d3bd | 295 | |
6d0f6bcf | 296 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO5 not supported, expand your config.h |
c935d3bd | 297 | |
6d0f6bcf | 298 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 6) |
c935d3bd | 299 | |
6d0f6bcf | 300 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO6 not supported, expand your config.h |
c935d3bd | 301 | |
6d0f6bcf | 302 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 7) |
c935d3bd | 303 | |
6d0f6bcf | 304 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO7 not supported, expand your config.h |
c935d3bd | 305 | |
6d0f6bcf | 306 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 8) |
c935d3bd | 307 | |
6d0f6bcf | 308 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO8 not supported, expand your config.h |
c935d3bd | 309 | |
6d0f6bcf | 310 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 9) |
c935d3bd | 311 | |
6d0f6bcf | 312 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO9 not supported, expand your config.h |
c935d3bd WD |
313 | |
314 | #else | |
6d0f6bcf | 315 | #error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_LED_PIO in right case |
c935d3bd WD |
316 | #endif |
317 | ||
318 | #define CONFIG_STATUS_LED 1 /* enable status led driver */ | |
319 | ||
320 | #define STATUS_LED_BIT (1 << 0) /* LED[0] */ | |
321 | #define STATUS_LED_STATE STATUS_LED_BLINKING | |
322 | #define STATUS_LED_BOOT_STATE STATUS_LED_OFF | |
6d0f6bcf | 323 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ |
c935d3bd WD |
324 | #define STATUS_LED_BOOT 0 /* boot LED */ |
325 | ||
326 | #if (STATUS_LED_BITS > 1) | |
327 | #define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ | |
328 | #define STATUS_LED_STATE1 STATUS_LED_OFF | |
6d0f6bcf | 329 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 50) /* ca. 5 Hz */ |
c935d3bd WD |
330 | #define STATUS_LED_RED 1 /* fail LED */ |
331 | #endif | |
332 | ||
333 | #if (STATUS_LED_BITS > 2) | |
334 | #define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ | |
335 | #define STATUS_LED_STATE2 STATUS_LED_OFF | |
6d0f6bcf | 336 | #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ |
c935d3bd WD |
337 | #define STATUS_LED_YELLOW 2 /* info LED */ |
338 | #endif | |
339 | ||
340 | #if (STATUS_LED_BITS > 3) | |
341 | #define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ | |
342 | #define STATUS_LED_STATE3 STATUS_LED_OFF | |
6d0f6bcf | 343 | #define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ |
c935d3bd WD |
344 | #define STATUS_LED_GREEN 3 /* info LED */ |
345 | #endif | |
346 | ||
347 | #define STATUS_LED_PAR 1 /* makes status_led.h happy */ | |
348 | ||
6d0f6bcf | 349 | #endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ |
c935d3bd WD |
350 | |
351 | /*------------------------------------------------------------------------ | |
352 | * SEVEN SEGMENT LED DISPLAY | |
353 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 354 | #if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) |
c935d3bd | 355 | |
6d0f6bcf | 356 | #if (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 0) |
c935d3bd | 357 | |
6d0f6bcf | 358 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO0 not supported, expand your config.h |
c935d3bd | 359 | |
6d0f6bcf | 360 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 1) |
c935d3bd | 361 | |
6d0f6bcf | 362 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO1 not supported, expand your config.h |
c935d3bd | 363 | |
6d0f6bcf | 364 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 2) |
c935d3bd | 365 | |
6d0f6bcf | 366 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO2 not supported, expand your config.h |
c935d3bd | 367 | |
6d0f6bcf | 368 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 3) |
c935d3bd | 369 | |
6d0f6bcf JCPV |
370 | #define SEVENSEG_BASE CONFIG_SYS_NIOS_CPU_PIO3 |
371 | #define SEVENSEG_BITS CONFIG_SYS_NIOS_CPU_PIO3_BITS | |
c935d3bd WD |
372 | #define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */ |
373 | ||
6d0f6bcf | 374 | #if (CONFIG_SYS_NIOS_CPU_PIO3_TYPE == 1) |
c935d3bd WD |
375 | #define SEVENSEG_WRONLY 1 |
376 | #else | |
377 | #undef SEVENSEG_WRONLY | |
378 | #endif | |
379 | ||
6d0f6bcf | 380 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 4) |
c935d3bd | 381 | |
6d0f6bcf | 382 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO4 not supported, expand your config.h |
c935d3bd | 383 | |
6d0f6bcf | 384 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 5) |
c935d3bd | 385 | |
6d0f6bcf | 386 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO5 not supported, expand your config.h |
c935d3bd | 387 | |
6d0f6bcf | 388 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 6) |
c935d3bd | 389 | |
6d0f6bcf | 390 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO6 not supported, expand your config.h |
c935d3bd | 391 | |
6d0f6bcf | 392 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 7) |
c935d3bd | 393 | |
6d0f6bcf | 394 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO7 not supported, expand your config.h |
c935d3bd | 395 | |
6d0f6bcf | 396 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 8) |
c935d3bd | 397 | |
6d0f6bcf | 398 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO8 not supported, expand your config.h |
c935d3bd | 399 | |
6d0f6bcf | 400 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 9) |
c935d3bd | 401 | |
6d0f6bcf | 402 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO9 not supported, expand your config.h |
c935d3bd WD |
403 | |
404 | #else | |
6d0f6bcf | 405 | #error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO in right case |
c935d3bd WD |
406 | #endif |
407 | ||
408 | #define CONFIG_SEVENSEG 1 /* enable seven segment led driver */ | |
409 | ||
410 | /* | |
411 | * Dual 7-Segment Display pin assignment -- read more in your | |
412 | * "Nios Development Board Reference Manual" | |
413 | * | |
414 | * | |
415 | * (U8) HI:D[15..8] (U9) LO:D[7..0] | |
416 | * ______ ______ | |
417 | * | D14 | | D6 | | |
418 | * | | | | | |
419 | * D9| |D13 D1| |D5 | |
420 | * |______| |______| ___ | |
421 | * | D8 | | D0 | | A | | |
422 | * | | | | F|___|B | |
423 | * D10| |D12 D2| |D4 | G | | |
424 | * |______| |______| E|___|C | |
425 | * D11 * D3 * D * | |
426 | * D15 D7 DP | |
427 | * | |
428 | */ | |
429 | #define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */ | |
430 | #define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */ | |
431 | #define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */ | |
432 | #define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */ | |
433 | #define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */ | |
434 | #define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */ | |
435 | #define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */ | |
436 | #define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */ | |
437 | #define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */ | |
438 | ||
6d0f6bcf | 439 | #endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ |
c935d3bd | 440 | |
180d3f74 WD |
441 | /*------------------------------------------------------------------------ |
442 | * ASMI - Active Serial Memory Interface. | |
443 | * | |
444 | * ASMI is for Cyclone devices only and only works when the configuration | |
445 | * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details. | |
446 | *----------------------------------------------------------------------*/ | |
5653fc33 | 447 | #define CONFIG_NIOS_ASMI /* Enable ASMI */ |
6d0f6bcf | 448 | #define CONFIG_SYS_NIOS_ASMIBASE CONFIG_SYS_NIOS_CPU_ASMI0 /* ASMI base address */ |
180d3f74 | 449 | |
3c3227f3 | 450 | |
11799434 JL |
451 | /* |
452 | * BOOTP options | |
453 | */ | |
454 | #define CONFIG_BOOTP_BOOTFILESIZE | |
455 | #define CONFIG_BOOTP_BOOTPATH | |
456 | #define CONFIG_BOOTP_GATEWAY | |
457 | #define CONFIG_BOOTP_HOSTNAME | |
458 | ||
459 | ||
3c3227f3 JL |
460 | /* |
461 | * Command line configuration. | |
462 | */ | |
4e620410 JCPV |
463 | #include <config_cmd_default.h> |
464 | ||
465 | #define CONFIG_CMD_CDP | |
466 | #define CONFIG_CMD_DHCP | |
467 | #define CONFIG_CMD_DIAG | |
468 | #define CONFIG_CMD_DISPLAY | |
469 | #define CONFIG_CMD_EXT2 | |
470 | #define CONFIG_CMD_FAT | |
471 | #define CONFIG_CMD_IDE | |
472 | #define CONFIG_CMD_IMMAP | |
473 | #define CONFIG_CMD_IRQ | |
474 | #define CONFIG_CMD_PING | |
475 | #define CONFIG_CMD_PORTIO | |
476 | #define CONFIG_CMD_REGINFO | |
477 | #define CONFIG_CMD_SAVES | |
478 | #define CONFIG_CMD_SDRAM | |
479 | #define CONFIG_CMD_SNTP | |
480 | ||
3c3227f3 | 481 | #undef CONFIG_CMD_NFS |
3c3227f3 JL |
482 | #undef CONFIG_CMD_XIMG |
483 | ||
d06a5f7e WD |
484 | /*------------------------------------------------------------------------ |
485 | * COMPACT FLASH | |
486 | *----------------------------------------------------------------------*/ | |
3c3227f3 | 487 | #if defined(CONFIG_CMD_IDE) |
d06a5f7e | 488 | #define CONFIG_IDE_PREINIT /* Implement id_preinit */ |
6d0f6bcf JCPV |
489 | #define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ |
490 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ | |
491 | ||
492 | #define CONFIG_SYS_ATA_BASE_ADDR 0x00920a00 /* IDE/ATA base addr */ | |
493 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ | |
494 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ | |
495 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0040 /* Register offset */ | |
496 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ | |
497 | #define CONFIG_SYS_ATA_STRIDE 4 /* Width betwix addrs */ | |
d06a5f7e WD |
498 | #define CONFIG_DOS_PARTITION |
499 | ||
500 | /* Board-specific cf regs */ | |
6d0f6bcf JCPV |
501 | #define CONFIG_SYS_CF_PRESENT 0x009209b0 /* CF Present PIO base */ |
502 | #define CONFIG_SYS_CF_POWER 0x009209c0 /* CF Power FET PIO base*/ | |
503 | #define CONFIG_SYS_CF_ATASEL 0x009209d0 /* CF ATASEL PIO base */ | |
d06a5f7e | 504 | |
3c3227f3 | 505 | #endif |
d06a5f7e | 506 | |
4a551709 WD |
507 | /*------------------------------------------------------------------------ |
508 | * KGDB | |
509 | *----------------------------------------------------------------------*/ | |
3c3227f3 | 510 | #if defined(CONFIG_CMD_KGDB) |
4a551709 WD |
511 | #define CONFIG_KGDB_BAUDRATE 9600 |
512 | #endif | |
513 | ||
514 | /*------------------------------------------------------------------------ | |
515 | * MISC | |
516 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
517 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
518 | #define CONFIG_SYS_PROMPT "DK1C20 > " /* Monitor Command Prompt */ | |
519 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
520 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
521 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ | |
522 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
523 | ||
524 | #if (CONFIG_SYS_SRAM_SIZE != 0) | |
525 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SRAM_BASE /* Default load address */ | |
c935d3bd | 526 | #else |
6d0f6bcf | 527 | #undef CONFIG_SYS_LOAD_ADDR |
c935d3bd | 528 | #endif |
4a551709 | 529 | |
6d0f6bcf JCPV |
530 | #if (CONFIG_SYS_SDRAM_SIZE != 0) |
531 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* SDRAM til stack area */ | |
532 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) /* 1MB stack */ | |
c935d3bd | 533 | #else |
6d0f6bcf JCPV |
534 | #undef CONFIG_SYS_MEMTEST_START |
535 | #undef CONFIG_SYS_MEMTEST_END | |
c935d3bd | 536 | #endif |
4a551709 | 537 | |
700a0c64 WD |
538 | /* |
539 | * JFFS2 partitions | |
540 | * | |
541 | */ | |
542 | /* No command line, one static partition, whole device */ | |
68d7d651 | 543 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
544 | #define CONFIG_JFFS2_DEV "nor0" |
545 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
546 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
547 | ||
548 | /* mtdparts command line support */ | |
549 | /* | |
68d7d651 | 550 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
551 | #define MTDIDS_DEFAULT "" |
552 | #define MTDPARTS_DEFAULT "" | |
553 | */ | |
4a551709 WD |
554 | |
555 | #endif /* __CONFIG_H */ |