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c935d3bd WD |
1 | /* |
2 | * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> | |
3 | * Stephan Linz <linz@li-pro.net> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
ec4c544b WD |
27 | /*********************************************************************** |
28 | * Include the whole NIOS CPU configuration. | |
c935d3bd | 29 | * |
ec4c544b | 30 | * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! |
c935d3bd | 31 | * |
ec4c544b | 32 | ***********************************************************************/ |
c935d3bd WD |
33 | |
34 | #if defined(CONFIG_NIOS_SAFE_32) | |
ec4c544b | 35 | #include <configs/DK1S10_safe_32.h> |
c935d3bd | 36 | #elif defined(CONFIG_NIOS_STANDARD_32) |
ec4c544b WD |
37 | #include <configs/DK1S10_standard_32.h> |
38 | #elif defined(CONFIG_NIOS_MTX_LDK_20) | |
39 | #include <configs/DK1S10_mtx_ldk_20.h> | |
c935d3bd | 40 | #else |
6d0f6bcf | 41 | #error *** CONFIG_SYS_ERROR: you have to setup right NIOS CPU configuration |
c935d3bd WD |
42 | #endif |
43 | ||
44 | /*------------------------------------------------------------------------ | |
45 | * BOARD/CPU -- TOP-LEVEL | |
46 | *----------------------------------------------------------------------*/ | |
47 | #define CONFIG_NIOS 1 /* NIOS-32 core */ | |
48 | #define CONFIG_DK1S10 1 /* Stratix DK-1S10 board*/ | |
6d0f6bcf JCPV |
49 | #define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */ |
50 | #define CONFIG_SYS_HZ 1000 /* 1 msec time tick */ | |
51 | #undef CONFIG_SYS_CLKS_IN_HZ | |
c837dcb1 | 52 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ |
c935d3bd WD |
53 | |
54 | /*------------------------------------------------------------------------ | |
55 | * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) | |
56 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 57 | #if (CONFIG_SYS_NIOS_CPU_SDRAM_SIZE != 0) |
c935d3bd | 58 | |
6d0f6bcf JCPV |
59 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_NIOS_CPU_SDRAM_BASE |
60 | #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_NIOS_CPU_SDRAM_SIZE | |
c935d3bd WD |
61 | |
62 | #else | |
6d0f6bcf | 63 | #error *** CONFIG_SYS_ERROR: you have to setup any SDRAM in NIOS CPU config |
c935d3bd WD |
64 | #endif |
65 | ||
6d0f6bcf | 66 | #if defined(CONFIG_SYS_NIOS_CPU_SRAM_BASE) && defined(CONFIG_SYS_NIOS_CPU_SRAM_SIZE) |
ec4c544b | 67 | |
6d0f6bcf JCPV |
68 | #define CONFIG_SYS_SRAM_BASE CONFIG_SYS_NIOS_CPU_SRAM_BASE |
69 | #define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_NIOS_CPU_SRAM_SIZE | |
ec4c544b WD |
70 | |
71 | #else | |
72 | ||
6d0f6bcf JCPV |
73 | #undef CONFIG_SYS_SRAM_BASE |
74 | #undef CONFIG_SYS_SRAM_SIZE | |
ec4c544b WD |
75 | |
76 | #endif | |
77 | ||
6d0f6bcf | 78 | #define CONFIG_SYS_VECT_BASE CONFIG_SYS_NIOS_CPU_VEC_BASE |
c935d3bd WD |
79 | |
80 | /*------------------------------------------------------------------------ | |
81 | * MEMORY ORGANIZATION - For the most part, you can put things pretty | |
82 | * much anywhere. This is pretty flexible for Nios. So here we make some | |
83 | * arbitrary choices & assume that the monitor is placed at the end of | |
84 | * a memory resource (so you must make sure TEXT_BASE is chosen | |
85 | * appropriately). | |
86 | * | |
53677ef1 WD |
87 | * -The heap is placed below the monitor. |
88 | * -Global data is placed below the heap. | |
89 | * -The stack is placed below global data (&grows down). | |
c935d3bd | 90 | *----------------------------------------------------------------------*/ |
6d0f6bcf JCPV |
91 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ |
92 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ | |
93 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) | |
c935d3bd | 94 | |
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
96 | #define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) | |
97 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) | |
98 | #define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET | |
c935d3bd WD |
99 | |
100 | /*------------------------------------------------------------------------ | |
101 | * FLASH (AM29LV065D) | |
102 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 103 | #if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) |
c935d3bd | 104 | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_NIOS_CPU_FLASH_BASE |
106 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_NIOS_CPU_FLASH_SIZE | |
107 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ | |
108 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ | |
109 | #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ | |
110 | #define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ | |
111 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ | |
c935d3bd WD |
112 | |
113 | #else | |
6d0f6bcf | 114 | #error *** CONFIG_SYS_ERROR: you have to setup any Flash memory in NIOS CPU config |
c935d3bd WD |
115 | #endif |
116 | ||
117 | /*------------------------------------------------------------------------ | |
118 | * ENVIRONMENT | |
119 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 120 | #if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) |
c935d3bd | 121 | |
5a1aceb0 | 122 | #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ |
ec4c544b WD |
123 | |
124 | #if defined(CONFIG_NIOS_STANDARD_32) | |
6d0f6bcf | 125 | #define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Mem addr of env */ |
ec4c544b | 126 | #elif defined(CONFIG_NIOS_MTX_LDK_20) |
6d0f6bcf | 127 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
ec4c544b | 128 | #else |
6d0f6bcf | 129 | #error *** CONFIG_SYS_ERROR: you have to setup the environment base address CONFIG_ENV_ADDR |
ec4c544b WD |
130 | #endif |
131 | ||
0e8d1586 | 132 | #define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ |
c935d3bd WD |
133 | #define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ |
134 | ||
135 | #else | |
93f6d725 | 136 | #define CONFIG_ENV_IS_NOWHERE 1 /* NO Environment */ |
c935d3bd WD |
137 | #endif |
138 | ||
139 | /*------------------------------------------------------------------------ | |
140 | * CONSOLE | |
141 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 142 | #if (CONFIG_SYS_NIOS_CPU_UART_NUMS != 0) |
c935d3bd | 143 | |
6d0f6bcf | 144 | #define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_NIOS_CPU_UART0 /* 1st UART is Cons. */ |
b54d32b4 | 145 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
c935d3bd | 146 | |
6d0f6bcf JCPV |
147 | #if (CONFIG_SYS_NIOS_CPU_UART0_BR != 0) |
148 | #define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ | |
149 | #define CONFIG_BAUDRATE CONFIG_SYS_NIOS_CPU_UART0_BR | |
c935d3bd | 150 | #else |
6d0f6bcf | 151 | #undef CONFIG_SYS_NIOS_FIXEDBAUD |
c935d3bd WD |
152 | #define CONFIG_BAUDRATE 115200 |
153 | #endif | |
154 | ||
6d0f6bcf | 155 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
c935d3bd WD |
156 | |
157 | #else | |
6d0f6bcf | 158 | #error *** CONFIG_SYS_ERROR: you have to setup at least one UART in NIOS CPU config |
c935d3bd WD |
159 | #endif |
160 | ||
161 | /*------------------------------------------------------------------------ | |
162 | * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, | |
163 | * so an avalon bus timer is required. | |
164 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 165 | #if (CONFIG_SYS_NIOS_CPU_TIMER_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_TICK_TIMER) |
c935d3bd | 166 | |
6d0f6bcf | 167 | #if (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 0) |
c935d3bd | 168 | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER0 /* TIMER0 as tick */ |
170 | #define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER0_IRQ | |
ec4c544b | 171 | |
6d0f6bcf | 172 | #if (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ |
63e73c9a | 173 | |
6d0f6bcf JCPV |
174 | #if (CONFIG_SYS_NIOS_CPU_TIMER0_PER >= CONFIG_SYS_HZ) |
175 | #define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER0_PER / CONFIG_SYS_HZ) | |
ec4c544b | 176 | #else |
6d0f6bcf | 177 | #error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ |
63e73c9a WD |
178 | #endif |
179 | ||
6d0f6bcf | 180 | #undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ |
63e73c9a | 181 | |
6d0f6bcf | 182 | #elif (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 0) /* variable period */ |
63e73c9a | 183 | |
6d0f6bcf JCPV |
184 | #if (CONFIG_SYS_HZ <= 1000) |
185 | #define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) | |
63e73c9a | 186 | #else |
6d0f6bcf | 187 | #error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 |
63e73c9a WD |
188 | #endif |
189 | ||
6d0f6bcf | 190 | #define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) |
63e73c9a WD |
191 | |
192 | #else | |
6d0f6bcf | 193 | #error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER0_FP correct |
ec4c544b | 194 | #endif |
c935d3bd | 195 | |
6d0f6bcf | 196 | #elif (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 1) |
c935d3bd | 197 | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER1 /* TIMER1 as tick */ |
199 | #define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER1_IRQ | |
c935d3bd | 200 | |
6d0f6bcf | 201 | #if (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ |
63e73c9a | 202 | |
6d0f6bcf JCPV |
203 | #if (CONFIG_SYS_NIOS_CPU_TIMER1_PER >= CONFIG_SYS_HZ) |
204 | #define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER1_PER / CONFIG_SYS_HZ) | |
c935d3bd | 205 | #else |
6d0f6bcf | 206 | #error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ |
63e73c9a WD |
207 | #endif |
208 | ||
6d0f6bcf | 209 | #undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ |
63e73c9a | 210 | |
6d0f6bcf | 211 | #elif (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 0) /* variable period */ |
63e73c9a | 212 | |
6d0f6bcf JCPV |
213 | #if (CONFIG_SYS_HZ <= 1000) |
214 | #define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) | |
63e73c9a | 215 | #else |
6d0f6bcf | 216 | #error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 |
63e73c9a WD |
217 | #endif |
218 | ||
6d0f6bcf | 219 | #define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) |
63e73c9a WD |
220 | |
221 | #else | |
6d0f6bcf | 222 | #error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER1_FP correct |
c935d3bd WD |
223 | #endif |
224 | ||
6d0f6bcf | 225 | #endif /* CONFIG_SYS_NIOS_CPU_TICK_TIMER */ |
c935d3bd WD |
226 | |
227 | #else | |
6d0f6bcf | 228 | #error *** CONFIG_SYS_ERROR: you have to setup at least one TIMER in NIOS CPU config |
c935d3bd WD |
229 | #endif |
230 | ||
231 | /*------------------------------------------------------------------------ | |
232 | * Ethernet -- needs work! | |
233 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 234 | #if (CONFIG_SYS_NIOS_CPU_LAN_NUMS == 1) |
c935d3bd | 235 | |
6d0f6bcf | 236 | #if (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ |
c935d3bd | 237 | |
c935d3bd WD |
238 | #define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ |
239 | #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ | |
6d0f6bcf | 240 | #define CONFIG_SMC91111_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) |
c935d3bd | 241 | |
6d0f6bcf | 242 | #if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) |
c935d3bd WD |
243 | #define CONFIG_SMC_USE_32_BIT 1 |
244 | #else /* no */ | |
245 | #undef CONFIG_SMC_USE_32_BIT | |
246 | #endif | |
247 | ||
6d0f6bcf | 248 | #elif (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ |
c935d3bd WD |
249 | |
250 | /********************************************/ | |
251 | /* !!! CS8900 is __not__ tested on NIOS !!! */ | |
252 | /********************************************/ | |
253 | #define CONFIG_DRIVER_CS8900 /* Using CS8900 */ | |
6d0f6bcf | 254 | #define CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) |
c935d3bd | 255 | |
6d0f6bcf | 256 | #if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) |
c935d3bd WD |
257 | #undef CS8900_BUS16 |
258 | #define CS8900_BUS32 1 | |
259 | #else /* no */ | |
260 | #define CS8900_BUS16 1 | |
261 | #undef CS8900_BUS32 | |
262 | #endif | |
263 | ||
264 | #else | |
6d0f6bcf | 265 | #error *** CONFIG_SYS_ERROR: invalid LAN0 chip type, check your NIOS CPU config |
c935d3bd WD |
266 | #endif |
267 | ||
268 | #define CONFIG_ETHADDR 08:00:3e:26:0a:5b | |
269 | #define CONFIG_NETMASK 255.255.255.0 | |
270 | #define CONFIG_IPADDR 192.168.2.21 | |
271 | #define CONFIG_SERVERIP 192.168.2.16 | |
272 | ||
273 | #else | |
6d0f6bcf | 274 | #error *** CONFIG_SYS_ERROR: you have to setup just one LAN only or expand your config.h |
c935d3bd WD |
275 | #endif |
276 | ||
277 | /*------------------------------------------------------------------------ | |
278 | * STATUS LEDs | |
279 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 280 | #if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_LED_PIO) |
c935d3bd | 281 | |
6d0f6bcf | 282 | #if (CONFIG_SYS_NIOS_CPU_LED_PIO == 0) |
c935d3bd | 283 | |
6d0f6bcf | 284 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO0 not supported, expand your config.h |
c935d3bd | 285 | |
6d0f6bcf | 286 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 1) |
c935d3bd | 287 | |
6d0f6bcf | 288 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO1 not supported, expand your config.h |
c935d3bd | 289 | |
6d0f6bcf | 290 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 2) |
c935d3bd | 291 | |
6d0f6bcf JCPV |
292 | #define STATUS_LED_BASE CONFIG_SYS_NIOS_CPU_PIO2 |
293 | #define STATUS_LED_BITS CONFIG_SYS_NIOS_CPU_PIO2_BITS | |
c935d3bd WD |
294 | #define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ |
295 | ||
6d0f6bcf | 296 | #if (CONFIG_SYS_NIOS_CPU_PIO2_TYPE == 1) |
c935d3bd WD |
297 | #define STATUS_LED_WRONLY 1 |
298 | #else | |
299 | #undef STATUS_LED_WRONLY | |
300 | #endif | |
301 | ||
6d0f6bcf | 302 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 3) |
c935d3bd | 303 | |
6d0f6bcf | 304 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO3 not supported, expand your config.h |
c935d3bd | 305 | |
6d0f6bcf | 306 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 4) |
c935d3bd | 307 | |
6d0f6bcf | 308 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO4 not supported, expand your config.h |
c935d3bd | 309 | |
6d0f6bcf | 310 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 5) |
c935d3bd | 311 | |
6d0f6bcf | 312 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO5 not supported, expand your config.h |
c935d3bd | 313 | |
6d0f6bcf | 314 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 6) |
c935d3bd | 315 | |
6d0f6bcf | 316 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO6 not supported, expand your config.h |
c935d3bd | 317 | |
6d0f6bcf | 318 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 7) |
c935d3bd | 319 | |
6d0f6bcf | 320 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO7 not supported, expand your config.h |
c935d3bd | 321 | |
6d0f6bcf | 322 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 8) |
c935d3bd | 323 | |
6d0f6bcf | 324 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO8 not supported, expand your config.h |
c935d3bd | 325 | |
6d0f6bcf | 326 | #elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 9) |
c935d3bd | 327 | |
6d0f6bcf | 328 | #error *** CONFIG_SYS_ERROR: status LEDs at PIO9 not supported, expand your config.h |
c935d3bd WD |
329 | |
330 | #else | |
6d0f6bcf | 331 | #error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_LED_PIO in right case |
c935d3bd WD |
332 | #endif |
333 | ||
334 | #define CONFIG_STATUS_LED 1 /* enable status led driver */ | |
335 | ||
336 | #define STATUS_LED_BIT (1 << 0) /* LED[0] */ | |
337 | #define STATUS_LED_STATE STATUS_LED_BLINKING | |
338 | #define STATUS_LED_BOOT_STATE STATUS_LED_OFF | |
6d0f6bcf | 339 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ |
c935d3bd WD |
340 | #define STATUS_LED_BOOT 0 /* boot LED */ |
341 | ||
342 | #if (STATUS_LED_BITS > 1) | |
343 | #define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ | |
344 | #define STATUS_LED_STATE1 STATUS_LED_OFF | |
6d0f6bcf | 345 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 50) /* ca. 5 Hz */ |
c935d3bd WD |
346 | #define STATUS_LED_RED 1 /* fail LED */ |
347 | #endif | |
348 | ||
349 | #if (STATUS_LED_BITS > 2) | |
350 | #define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ | |
351 | #define STATUS_LED_STATE2 STATUS_LED_OFF | |
6d0f6bcf | 352 | #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ |
c935d3bd WD |
353 | #define STATUS_LED_YELLOW 2 /* info LED */ |
354 | #endif | |
355 | ||
356 | #if (STATUS_LED_BITS > 3) | |
357 | #define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ | |
358 | #define STATUS_LED_STATE3 STATUS_LED_OFF | |
6d0f6bcf | 359 | #define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ |
c935d3bd WD |
360 | #define STATUS_LED_GREEN 3 /* info LED */ |
361 | #endif | |
362 | ||
363 | #define STATUS_LED_PAR 1 /* makes status_led.h happy */ | |
364 | ||
6d0f6bcf | 365 | #endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ |
c935d3bd WD |
366 | |
367 | /*------------------------------------------------------------------------ | |
368 | * SEVEN SEGMENT LED DISPLAY | |
369 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 370 | #if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO) |
c935d3bd | 371 | |
6d0f6bcf | 372 | #if (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 0) |
c935d3bd | 373 | |
6d0f6bcf | 374 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO0 not supported, expand your config.h |
c935d3bd | 375 | |
6d0f6bcf | 376 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 1) |
c935d3bd | 377 | |
6d0f6bcf | 378 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO1 not supported, expand your config.h |
c935d3bd | 379 | |
6d0f6bcf | 380 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 2) |
c935d3bd | 381 | |
6d0f6bcf | 382 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO2 not supported, expand your config.h |
c935d3bd | 383 | |
6d0f6bcf | 384 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 3) |
c935d3bd | 385 | |
6d0f6bcf JCPV |
386 | #define SEVENSEG_BASE CONFIG_SYS_NIOS_CPU_PIO3 |
387 | #define SEVENSEG_BITS CONFIG_SYS_NIOS_CPU_PIO3_BITS | |
c935d3bd WD |
388 | #define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */ |
389 | ||
6d0f6bcf | 390 | #if (CONFIG_SYS_NIOS_CPU_PIO3_TYPE == 1) |
c935d3bd WD |
391 | #define SEVENSEG_WRONLY 1 |
392 | #else | |
393 | #undef SEVENSEG_WRONLY | |
394 | #endif | |
395 | ||
6d0f6bcf | 396 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 4) |
c935d3bd | 397 | |
6d0f6bcf | 398 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO4 not supported, expand your config.h |
c935d3bd | 399 | |
6d0f6bcf | 400 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 5) |
c935d3bd | 401 | |
6d0f6bcf | 402 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO5 not supported, expand your config.h |
c935d3bd | 403 | |
6d0f6bcf | 404 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 6) |
c935d3bd | 405 | |
6d0f6bcf | 406 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO6 not supported, expand your config.h |
c935d3bd | 407 | |
6d0f6bcf | 408 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 7) |
c935d3bd | 409 | |
6d0f6bcf | 410 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO7 not supported, expand your config.h |
c935d3bd | 411 | |
6d0f6bcf | 412 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 8) |
c935d3bd | 413 | |
6d0f6bcf | 414 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO8 not supported, expand your config.h |
c935d3bd | 415 | |
6d0f6bcf | 416 | #elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 9) |
c935d3bd | 417 | |
6d0f6bcf | 418 | #error *** CONFIG_SYS_ERROR: seven segment display at PIO9 not supported, expand your config.h |
c935d3bd WD |
419 | |
420 | #else | |
6d0f6bcf | 421 | #error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO in right case |
c935d3bd WD |
422 | #endif |
423 | ||
424 | #define CONFIG_SEVENSEG 1 /* enable seven segment led driver */ | |
425 | ||
426 | /* | |
427 | * Dual 7-Segment Display pin assignment -- read more in your | |
428 | * "Nios Development Board Reference Manual" | |
429 | * | |
430 | * | |
431 | * (U8) HI:D[15..8] (U9) LO:D[7..0] | |
432 | * ______ ______ | |
433 | * | D14 | | D6 | | |
434 | * | | | | | |
435 | * D9| |D13 D1| |D5 | |
436 | * |______| |______| ___ | |
437 | * | D8 | | D0 | | A | | |
438 | * | | | | F|___|B | |
439 | * D10| |D12 D2| |D4 | G | | |
440 | * |______| |______| E|___|C | |
441 | * D11 * D3 * D * | |
442 | * D15 D7 DP | |
443 | * | |
444 | */ | |
445 | #define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */ | |
446 | #define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */ | |
447 | #define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */ | |
448 | #define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */ | |
449 | #define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */ | |
450 | #define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */ | |
451 | #define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */ | |
452 | #define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */ | |
453 | #define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */ | |
454 | ||
6d0f6bcf | 455 | #endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ |
c935d3bd | 456 | |
11799434 JL |
457 | /* |
458 | * BOOTP options | |
459 | */ | |
460 | #define CONFIG_BOOTP_BOOTFILESIZE | |
461 | #define CONFIG_BOOTP_BOOTPATH | |
462 | #define CONFIG_BOOTP_GATEWAY | |
463 | #define CONFIG_BOOTP_HOSTNAME | |
464 | ||
465 | ||
3c3227f3 JL |
466 | /* |
467 | * Command line configuration. | |
468 | */ | |
4e620410 JCPV |
469 | #include <config_cmd_default.h> |
470 | ||
471 | #define CONFIG_CMD_CDP | |
472 | #define CONFIG_CMD_DHCP | |
473 | #define CONFIG_CMD_DIAG | |
474 | #define CONFIG_CMD_DISPLAY | |
475 | #define CONFIG_CMD_EXT2 | |
476 | #define CONFIG_CMD_IMMAP | |
477 | #define CONFIG_CMD_IRQ | |
478 | #define CONFIG_CMD_PING | |
479 | #define CONFIG_CMD_PORTIO | |
480 | #define CONFIG_CMD_REGINFO | |
481 | #define CONFIG_CMD_REISER | |
482 | #define CONFIG_CMD_SAVES | |
483 | #define CONFIG_CMD_SDRAM | |
484 | #define CONFIG_CMD_SNTP | |
485 | ||
486 | #undef CONFIG_CMD_NFS | |
487 | #undef CONFIG_CMD_XIMG | |
c935d3bd WD |
488 | |
489 | /*------------------------------------------------------------------------ | |
490 | * KGDB | |
491 | *----------------------------------------------------------------------*/ | |
3c3227f3 | 492 | #if defined(CONFIG_CMD_KGDB) |
c935d3bd WD |
493 | #define CONFIG_KGDB_BAUDRATE 9600 |
494 | #endif | |
495 | ||
496 | /*------------------------------------------------------------------------ | |
497 | * MISC | |
498 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
499 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
500 | #define CONFIG_SYS_PROMPT "DK1S10 > " /* Monitor Command Prompt */ | |
501 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
502 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
503 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ | |
504 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
c935d3bd | 505 | |
ec4c544b | 506 | /* Default load address */ |
6d0f6bcf | 507 | #if (CONFIG_SYS_SRAM_SIZE != 0) |
ec4c544b WD |
508 | |
509 | /* default in SRAM */ | |
6d0f6bcf | 510 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SRAM_BASE |
ec4c544b | 511 | |
6d0f6bcf | 512 | #elif (CONFIG_SYS_SDRAM_SIZE != 0) |
ec4c544b WD |
513 | |
514 | /* default in SDRAM */ | |
6d0f6bcf JCPV |
515 | #if (CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE) |
516 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE) | |
ec4c544b | 517 | #else |
6d0f6bcf | 518 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE |
ec4c544b WD |
519 | #endif |
520 | ||
c935d3bd | 521 | #else |
6d0f6bcf | 522 | #undef CONFIG_SYS_LOAD_ADDR /* force error break */ |
c935d3bd WD |
523 | #endif |
524 | ||
ec4c544b WD |
525 | |
526 | /* MEM test area */ | |
6d0f6bcf | 527 | #if (CONFIG_SYS_SDRAM_SIZE != 0) |
ec4c544b WD |
528 | |
529 | /* SDRAM begin to stack area (1MB stack) */ | |
6d0f6bcf JCPV |
530 | #if (CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE) |
531 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE) | |
532 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) | |
ec4c544b | 533 | #else |
6d0f6bcf JCPV |
534 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
535 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) | |
ec4c544b WD |
536 | #endif |
537 | ||
c935d3bd | 538 | #else |
6d0f6bcf JCPV |
539 | #undef CONFIG_SYS_MEMTEST_START /* force error break */ |
540 | #undef CONFIG_SYS_MEMTEST_END | |
c935d3bd WD |
541 | #endif |
542 | ||
700a0c64 WD |
543 | /* |
544 | * JFFS2 partitions | |
545 | * | |
546 | */ | |
547 | /* No command line, one static partition, whole device */ | |
548 | #undef CONFIG_JFFS2_CMDLINE | |
549 | #define CONFIG_JFFS2_DEV "nor0" | |
550 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
551 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
552 | ||
553 | /* mtdparts command line support */ | |
554 | /* | |
555 | #define CONFIG_JFFS2_CMDLINE | |
556 | #define MTDIDS_DEFAULT "" | |
557 | #define MTDPARTS_DEFAULT "" | |
558 | */ | |
c935d3bd WD |
559 | |
560 | #endif /* __CONFIG_H */ |