[people/ms/u-boot.git] / include / configs / DK1S10.h

/*
 * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
 * Stephan Linz <linz@li-pro.net>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/***********************************************************************
 * Include the whole NIOS CPU configuration.
 *
 * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
 *
 ***********************************************************************/

#if	defined(CONFIG_NIOS_SAFE_32)
#include <configs/DK1S10_safe_32.h>
#elif	defined(CONFIG_NIOS_STANDARD_32)
#include <configs/DK1S10_standard_32.h>
#elif	defined(CONFIG_NIOS_MTX_LDK_20)
#include <configs/DK1S10_mtx_ldk_20.h>
#else
#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
#endif

/*------------------------------------------------------------------------
 * BOARD/CPU -- TOP-LEVEL
 *----------------------------------------------------------------------*/
#define CONFIG_NIOS		1		/* NIOS-32 core		*/
#define	CONFIG_DK1S10		1		/* Stratix DK-1S10 board*/
#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
#define	CFG_HZ			1000		/* 1 msec time tick	*/
#undef  CFG_CLKS_IN_HZ
#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/

/*------------------------------------------------------------------------
 * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)

#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE
#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE

#else
#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
#endif

#if	defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)

#define	CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE
#define	CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE

#else

#undef	CFG_SRAM_BASE
#undef	CFG_SRAM_SIZE

#endif

#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE

/*------------------------------------------------------------------------
 * MEMORY ORGANIZATION - For the most part, you can put things pretty
 * much anywhere. This is pretty flexible for Nios. So here we make some
 * arbitrary choices & assume that the monitor is placed at the end of
 * a memory resource (so you must make sure TEXT_BASE is chosen
 * appropriately).
 *
 * 	-The heap is placed below the monitor.
 * 	-Global data is placed below the heap.
 * 	-The stack is placed below global data (&grows down).
 *----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)

#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET

/*------------------------------------------------------------------------
 * FLASH (AM29LV065D)
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)

#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE
#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE
#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/

#else
#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
#endif

/*------------------------------------------------------------------------
 * ENVIRONMENT
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)

#define	CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */

#if	defined(CONFIG_NIOS_STANDARD_32)
#define CFG_ENV_ADDR		CFG_FLASH_BASE	/* Mem addr of env	*/
#elif	defined(CONFIG_NIOS_MTX_LDK_20)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
#else
#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
#endif

#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
#define CONFIG_ENV_OVERWRITE			/* Serial/eth change Ok */

#else
#define	CFG_ENV_IS_NOWHERE	1		/* NO Environment	*/
#endif

/*------------------------------------------------------------------------
 * CONSOLE
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_UART_NUMS != 0)

#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */

#if	(CFG_NIOS_CPU_UART0_BR != 0)
#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR
#else
#undef	CFG_NIOS_FIXEDBAUD
#define CONFIG_BAUDRATE		115200
#endif

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#else
#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
#endif

/*------------------------------------------------------------------------
 * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
 * so an avalon bus timer is required.
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)

#if	(CFG_NIOS_CPU_TICK_TIMER == 0)

#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ

#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
#else
#error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ
#endif

#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)

#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ

#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
#else
#error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ
#endif

#endif	/* CFG_NIOS_CPU_TICK_TIMER */

#else
#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
#endif

/*------------------------------------------------------------------------
 * Ethernet -- needs work!
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_LAN_NUMS == 1)

#if	(CFG_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/

#define	CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
#define	CONFIG_SMC91111_BASE	(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)

#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
#define	CONFIG_SMC_USE_32_BIT	1
#else	/* no */
#undef	CONFIG_SMC_USE_32_BIT
#endif

#elif	(CFG_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/

	/********************************************/
	/* !!! CS8900 is __not__ tested on NIOS !!! */
	/********************************************/
#define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
#define	CS8900_BASE		(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)

#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
#undef	CS8900_BUS16
#define	CS8900_BUS32		1
#else	/* no */
#define	CS8900_BUS16		1
#undef	CS8900_BUS32
#endif

#else
#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
#endif

#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.2.21
#define CONFIG_SERVERIP		192.168.2.16

#else
#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
#endif

/*------------------------------------------------------------------------
 * STATUS LEDs
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)

#if	(CFG_NIOS_CPU_LED_PIO == 0)

#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 1)

#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 2)

#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO2
#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO2_BITS
#define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */

#if	(CFG_NIOS_CPU_PIO2_TYPE == 1)
#define	STATUS_LED_WRONLY		1
#else
#undef	STATUS_LED_WRONLY
#endif

#elif	(CFG_NIOS_CPU_LED_PIO == 3)

#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 4)

#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 5)

#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 6)

#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 7)

#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 8)

#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_LED_PIO == 9)

#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h

#else
#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
#endif

#define	CONFIG_STATUS_LED		1 /* enable status led driver */

#define	STATUS_LED_BIT			(1 << 0)	/* LED[0] */
#define	STATUS_LED_STATE		STATUS_LED_BLINKING
#define	STATUS_LED_BOOT_STATE		STATUS_LED_OFF
#define	STATUS_LED_PERIOD		(CFG_HZ / 10)	/* ca. 1 Hz */
#define	STATUS_LED_BOOT			0		/* boot LED */

#if	(STATUS_LED_BITS > 1)
#define	STATUS_LED_BIT1			(1 << 1)	/* LED[1] */
#define	STATUS_LED_STATE1		STATUS_LED_OFF
#define	STATUS_LED_PERIOD1		(CFG_HZ / 50)	/* ca. 5 Hz */
#define	STATUS_LED_RED			1		/* fail LED */
#endif

#if	(STATUS_LED_BITS > 2)
#define	STATUS_LED_BIT2			(1 << 2)	/* LED[2] */
#define	STATUS_LED_STATE2		STATUS_LED_OFF
#define	STATUS_LED_PERIOD2		(CFG_HZ / 10)	/* ca. 1 Hz */
#define	STATUS_LED_YELLOW		2		/* info LED */
#endif

#if	(STATUS_LED_BITS > 3)
#define	STATUS_LED_BIT3			(1 << 3)	/* LED[3] */
#define	STATUS_LED_STATE3		STATUS_LED_OFF
#define	STATUS_LED_PERIOD3		(CFG_HZ / 10)	/* ca. 1 Hz */
#define	STATUS_LED_GREEN		3		/* info LED */
#endif

#define	STATUS_LED_PAR			1 /* makes status_led.h happy */

#endif	/* CFG_NIOS_CPU_PIO_NUMS */

/*------------------------------------------------------------------------
 * SEVEN SEGMENT LED DISPLAY
 *----------------------------------------------------------------------*/
#if	(CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_SEVENSEG_PIO)

#if	(CFG_NIOS_CPU_SEVENSEG_PIO == 0)

#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 1)

#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 2)

#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 3)

#define	SEVENSEG_BASE			CFG_NIOS_CPU_PIO3
#define	SEVENSEG_BITS			CFG_NIOS_CPU_PIO3_BITS
#define	SEVENSEG_ACTIVE			0 /* LED on for bit == 1 */

#if	(CFG_NIOS_CPU_PIO3_TYPE == 1)
#define	SEVENSEG_WRONLY			1
#else
#undef	SEVENSEG_WRONLY
#endif

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 4)

#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 5)

#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 6)

#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 7)

#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 8)

#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h

#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 9)

#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h

#else
#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
#endif

#define	CONFIG_SEVENSEG			1 /* enable seven segment led driver */

/*
 * Dual 7-Segment Display pin assignment -- read more in your
 * "Nios Development Board Reference Manual"
 *
 *
 *    (U8) HI:D[15..8]     (U9) LO:D[7..0]
 *         ______               ______
 *        |  D14 |             |  D6  |
 *        |      |             |      |
 *      D9|      |D13        D1|      |D5
 *        |______|             |______|                  ___
 *        |  D8  |             |  D0  |                 | A |
 *        |      |             |      |                F|___|B
 *     D10|      |D12        D2|      |D4               | G |
 *        |______|             |______|                E|___|C
 *           D11  *               D3   *                  D  *
 *                D15                  D7                    DP
 *
 */
#define	SEVENSEG_DIGIT_HI_LO_EQUAL	1	/* high nibble equal low nibble */
#define	SEVENSEG_DIGIT_A		(1 << 6) /* bit 6 is segment A */
#define	SEVENSEG_DIGIT_B		(1 << 5) /* bit 5 is segment B */
#define	SEVENSEG_DIGIT_C		(1 << 4) /* bit 4 is segment C */
#define	SEVENSEG_DIGIT_D		(1 << 3) /* bit 3 is segment D */
#define	SEVENSEG_DIGIT_E		(1 << 2) /* bit 2 is segment E */
#define	SEVENSEG_DIGIT_F		(1 << 1) /* bit 1 is segment F */
#define	SEVENSEG_DIGIT_G		(1 << 0) /* bit 0 is segment G */
#define	SEVENSEG_DIGIT_DP		(1 << 7) /* bit 7 is decimal point */

#endif	/* CFG_NIOS_CPU_PIO_NUMS */

/*------------------------------------------------------------------------
 * COMMANDS
 *----------------------------------------------------------------------*/
#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
				 CFG_CMD_ASKENV | \
				 CFG_CMD_BEDBUG | \
				 CFG_CMD_BMP	| \
				 CFG_CMD_BSP	| \
				 CFG_CMD_CACHE	| \
				 CFG_CMD_DATE	| \
				 CFG_CMD_DOC	| \
				 CFG_CMD_DTT	| \
				 CFG_CMD_EEPROM | \
				 CFG_CMD_ELF    | \
				 CFG_CMD_FAT	| \
				 CFG_CMD_FDC	| \
				 CFG_CMD_FDOS	| \
				 CFG_CMD_HWFLOW	| \
				 CFG_CMD_IDE	| \
				 CFG_CMD_I2C	| \
				 CFG_CMD_JFFS2	| \
				 CFG_CMD_KGDB	| \
				 CFG_CMD_NAND	| \
				 CFG_CMD_MMC	| \
				 CFG_CMD_MII	| \
				 CFG_CMD_PCI	| \
				 CFG_CMD_PCMCIA | \
				 CFG_CMD_SCSI	| \
				 CFG_CMD_SPI	| \
				 CFG_CMD_VFD	| \
				 CFG_CMD_USB	) )


#include <cmd_confdefs.h>

/*------------------------------------------------------------------------
 * KGDB
 *----------------------------------------------------------------------*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	9600
#endif

/*------------------------------------------------------------------------
 * MISC
 *----------------------------------------------------------------------*/
#define	CFG_LONGHELP			    /* undef to save memory	*/
#define	CFG_PROMPT		"DK1S10 > " /* Monitor Command Prompt	*/
#define	CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS		16	    /* max number of command args*/
#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */

/* Default load address	*/
#if	(CFG_SRAM_SIZE != 0)

/* default in SRAM */
#define	CFG_LOAD_ADDR		CFG_SRAM_BASE

#elif	(CFG_SDRAM_SIZE != 0)

/* default in SDRAM */
#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
#define	CFG_LOAD_ADDR		(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
#else
#define	CFG_LOAD_ADDR		CFG_SDRAM_BASE
#endif

#else
#undef	CFG_LOAD_ADDR		/* force error break */
#endif


/* MEM test area */
#if	(CFG_SDRAM_SIZE != 0)

/* SDRAM begin to stack area (1MB stack) */
#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
#define	CFG_MEMTEST_START	(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
#else
#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
#endif

#else
#undef	CFG_MEMTEST_START	/* force error break */
#undef	CFG_MEMTEST_END
#endif


#endif	/* __CONFIG_H */
Commit	Line	Data
c935d3bd WD	1	/*
	2	* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
	3	* Stephan Linz <linz@li-pro.net>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
ec4c544b WD	27	/***********************************************************************
ec4c544b WD	28	* Include the whole NIOS CPU configuration.
c935d3bd	29	*
ec4c544b	30	* !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
c935d3bd	31	*
ec4c544b	32	***********************************************************************/
c935d3bd WD	33
c935d3bd WD	34	#if defined(CONFIG_NIOS_SAFE_32)
ec4c544b	35	#include <configs/DK1S10_safe_32.h>
c935d3bd	36	#elif defined(CONFIG_NIOS_STANDARD_32)
ec4c544b WD	37	#include <configs/DK1S10_standard_32.h>
	38	#elif defined(CONFIG_NIOS_MTX_LDK_20)
	39	#include <configs/DK1S10_mtx_ldk_20.h>
c935d3bd WD	40	#else
	41	#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
	42	#endif
	43
	44	/*------------------------------------------------------------------------
	45	* BOARD/CPU -- TOP-LEVEL
	46	----------------------------------------------------------------------/
	47	#define CONFIG_NIOS 1 /* NIOS-32 core */
	48	#define CONFIG_DK1S10 1 /* Stratix DK-1S10 board*/
	49	#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
	50	#define CFG_HZ 1000 /* 1 msec time tick */
	51	#undef CFG_CLKS_IN_HZ
c837dcb1	52	#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
c935d3bd WD	53
	54	/*------------------------------------------------------------------------
	55	* BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
	56	----------------------------------------------------------------------/
	57	#if (CFG_NIOS_CPU_SDRAM_SIZE != 0)
	58
	59	#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE
	60	#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE
	61
	62	#else
	63	#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
	64	#endif
	65
ec4c544b WD	66	#if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
	67
	68	#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE
	69	#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE
	70
	71	#else
	72
	73	#undef CFG_SRAM_BASE
	74	#undef CFG_SRAM_SIZE
	75
	76	#endif
	77
c935d3bd WD	78	#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE
	79
	80	/*------------------------------------------------------------------------
	81	* MEMORY ORGANIZATION - For the most part, you can put things pretty
	82	* much anywhere. This is pretty flexible for Nios. So here we make some
	83	* arbitrary choices & assume that the monitor is placed at the end of
	84	* a memory resource (so you must make sure TEXT_BASE is chosen
	85	* appropriately).
	86	*
	87	* -The heap is placed below the monitor.
	88	* -Global data is placed below the heap.
	89	* -The stack is placed below global data (&grows down).
	90	----------------------------------------------------------------------/
	91	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
	92	#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
	93	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
	94
	95	#define CFG_MONITOR_BASE TEXT_BASE
	96	#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
	97	#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
	98	#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
	99
	100	/*------------------------------------------------------------------------
	101	* FLASH (AM29LV065D)
	102	----------------------------------------------------------------------/
	103	#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
	104
	105	#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE
	106	#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE
	107	#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
	108	#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
	109	#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
	110	#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
	111	#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */
	112
	113	#else
	114	#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
	115	#endif
	116
	117	/*------------------------------------------------------------------------
	118	* ENVIRONMENT
	119	----------------------------------------------------------------------/
	120	#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
	121
	122	#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
ec4c544b WD	123
ec4c544b WD	124	#if defined(CONFIG_NIOS_STANDARD_32)
c935d3bd	125	#define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */
ec4c544b WD	126	#elif defined(CONFIG_NIOS_MTX_LDK_20)
	127	#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
	128	#else
	129	#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
	130	#endif
	131
c935d3bd WD	132	#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
	133	#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */
	134
	135	#else
	136	#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */
	137	#endif
	138
	139	/*------------------------------------------------------------------------
	140	* CONSOLE
	141	----------------------------------------------------------------------/
	142	#if (CFG_NIOS_CPU_UART_NUMS != 0)
	143
	144	#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
	145
	146	#if (CFG_NIOS_CPU_UART0_BR != 0)
	147	#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
	148	#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR
	149	#else
	150	#undef CFG_NIOS_FIXEDBAUD
	151	#define CONFIG_BAUDRATE 115200
	152	#endif
	153
	154	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	155
	156	#else
	157	#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
	158	#endif
	159
	160	/*------------------------------------------------------------------------
	161	* TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT,
	162	* so an avalon bus timer is required.
	163	----------------------------------------------------------------------/
ec4c544b	164	#if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
c935d3bd WD	165
	166	#if (CFG_NIOS_CPU_TICK_TIMER == 0)
	167
ec4c544b WD	168	#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */
	169	#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ
	170
	171	#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
	172	#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
	173	#else
	174	#error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ
	175	#endif
c935d3bd WD	176
	177	#elif (CFG_NIOS_CPU_TICK_TIMER == 1)
	178
	179	#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
	180	#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
	181
	182	#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
	183	#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
	184	#else
	185	#error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ
	186	#endif
	187
	188	#endif /* CFG_NIOS_CPU_TICK_TIMER */
	189
	190	#else
	191	#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
	192	#endif
	193
	194	/*------------------------------------------------------------------------
	195	* Ethernet -- needs work!
	196	----------------------------------------------------------------------/
	197	#if (CFG_NIOS_CPU_LAN_NUMS == 1)
	198
	199	#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
	200
c935d3bd WD	201	#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
	202	#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
	203	#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
	204
	205	#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
	206	#define CONFIG_SMC_USE_32_BIT 1
	207	#else /* no */
	208	#undef CONFIG_SMC_USE_32_BIT
	209	#endif
	210
	211	#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */
	212
	213	/********************************************/
	214	/* !!! CS8900 is __not__ tested on NIOS !!! */
	215	/********************************************/
	216	#define CONFIG_DRIVER_CS8900 /* Using CS8900 */
	217	#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
	218
	219	#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
	220	#undef CS8900_BUS16
	221	#define CS8900_BUS32 1
	222	#else /* no */
	223	#define CS8900_BUS16 1
	224	#undef CS8900_BUS32
	225	#endif
	226
	227	#else
	228	#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
	229	#endif
	230
	231	#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
	232	#define CONFIG_NETMASK 255.255.255.0
	233	#define CONFIG_IPADDR 192.168.2.21
	234	#define CONFIG_SERVERIP 192.168.2.16
	235
	236	#else
	237	#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
	238	#endif
	239
	240	/*------------------------------------------------------------------------
	241	* STATUS LEDs
	242	----------------------------------------------------------------------/
ec4c544b	243	#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
c935d3bd WD	244
	245	#if (CFG_NIOS_CPU_LED_PIO == 0)
	246
	247	#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
	248
	249	#elif (CFG_NIOS_CPU_LED_PIO == 1)
	250
	251	#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
	252
	253	#elif (CFG_NIOS_CPU_LED_PIO == 2)
	254
	255	#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2
	256	#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS
	257	#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
	258
	259	#if (CFG_NIOS_CPU_PIO2_TYPE == 1)
	260	#define STATUS_LED_WRONLY 1
	261	#else
	262	#undef STATUS_LED_WRONLY
	263	#endif
	264
	265	#elif (CFG_NIOS_CPU_LED_PIO == 3)
	266
	267	#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
	268
	269	#elif (CFG_NIOS_CPU_LED_PIO == 4)
	270
	271	#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
	272
	273	#elif (CFG_NIOS_CPU_LED_PIO == 5)
	274
	275	#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
	276
	277	#elif (CFG_NIOS_CPU_LED_PIO == 6)
	278
	279	#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
	280
	281	#elif (CFG_NIOS_CPU_LED_PIO == 7)
	282
	283	#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
	284
	285	#elif (CFG_NIOS_CPU_LED_PIO == 8)
	286
	287	#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
	288
	289	#elif (CFG_NIOS_CPU_LED_PIO == 9)
	290
	291	#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
	292
	293	#else
	294	#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
	295	#endif
	296
	297	#define CONFIG_STATUS_LED 1 /* enable status led driver */
	298
	299	#define STATUS_LED_BIT (1 << 0) /* LED[0] */
	300	#define STATUS_LED_STATE STATUS_LED_BLINKING
	301	#define STATUS_LED_BOOT_STATE STATUS_LED_OFF
	302	#define STATUS_LED_PERIOD (CFG_HZ / 10) /* ca. 1 Hz */
	303	#define STATUS_LED_BOOT 0 /* boot LED */
	304
	305	#if (STATUS_LED_BITS > 1)
	306	#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */
	307	#define STATUS_LED_STATE1 STATUS_LED_OFF
308	#define STATUS_LED_PERIOD1 (CFG_HZ / 50) /* ca. 5 Hz */
309	#define STATUS_LED_RED 1 /* fail LED */
310	#endif
311
312	#if (STATUS_LED_BITS > 2)
313	#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */
314	#define STATUS_LED_STATE2 STATUS_LED_OFF
315	#define STATUS_LED_PERIOD2 (CFG_HZ / 10) /* ca. 1 Hz */
316	#define STATUS_LED_YELLOW 2 /* info LED */
317	#endif
318
319	#if (STATUS_LED_BITS > 3)
320	#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */
321	#define STATUS_LED_STATE3 STATUS_LED_OFF
322	#define STATUS_LED_PERIOD3 (CFG_HZ / 10) /* ca. 1 Hz */
323	#define STATUS_LED_GREEN 3 /* info LED */
324	#endif
325
326	#define STATUS_LED_PAR 1 /* makes status_led.h happy */
327
328	#endif /* CFG_NIOS_CPU_PIO_NUMS */
329
330	/*------------------------------------------------------------------------
331	* SEVEN SEGMENT LED DISPLAY
332	----------------------------------------------------------------------/
ec4c544b	333	#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_SEVENSEG_PIO)
c935d3bd WD	334
	335	#if (CFG_NIOS_CPU_SEVENSEG_PIO == 0)
	336
ec4c544b	337	#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
c935d3bd WD	338
	339	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1)
	340
ec4c544b	341	#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
c935d3bd WD	342
	343	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2)
	344
ec4c544b	345	#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
c935d3bd WD	346
	347	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3)
	348
	349	#define SEVENSEG_BASE CFG_NIOS_CPU_PIO3
	350	#define SEVENSEG_BITS CFG_NIOS_CPU_PIO3_BITS
	351	#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */
	352
	353	#if (CFG_NIOS_CPU_PIO3_TYPE == 1)
	354	#define SEVENSEG_WRONLY 1
	355	#else
	356	#undef SEVENSEG_WRONLY
	357	#endif
	358
	359	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4)
	360
ec4c544b	361	#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
c935d3bd WD	362
	363	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5)
	364
ec4c544b	365	#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
c935d3bd WD	366
	367	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6)
	368
ec4c544b	369	#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
c935d3bd WD	370
	371	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7)
	372
ec4c544b	373	#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
c935d3bd WD	374
	375	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8)
	376
ec4c544b	377	#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
c935d3bd WD	378
	379	#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9)
	380
ec4c544b	381	#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
c935d3bd WD	382
	383	#else
	384	#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
	385	#endif
	386
	387	#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */
	388
	389	/*
	390	* Dual 7-Segment Display pin assignment -- read more in your
	391	* "Nios Development Board Reference Manual"
	392	*
	393	*
	394	* (U8) HI:D[15..8] (U9) LO:D[7..0]
	395	* ______ ______
	396	* \| D14 \| \| D6 \|
	397	* \| \| \| \|
	398	* D9\| \|D13 D1\| \|D5
	399	* \|______\| \|______\| ___
	400	* \| D8 \| \| D0 \| \| A \|
	401	* \| \| \| \| F\|___\|B
	402	* D10\| \|D12 D2\| \|D4 \| G \|
	403	* \|______\| \|______\| E\|___\|C
	404	* D11 * D3 * D *
	405	* D15 D7 DP
	406	*
	407	*/
	408	#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */
	409	#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */
	410	#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */
	411	#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */
	412	#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */
	413	#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */
	414	#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */
	415	#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */
	416	#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */
	417
	418	#endif /* CFG_NIOS_CPU_PIO_NUMS */
	419
	420	/*------------------------------------------------------------------------
	421	* COMMANDS
	422	----------------------------------------------------------------------/
	423	#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
	424	CFG_CMD_ASKENV \| \
	425	CFG_CMD_BEDBUG \| \
	426	CFG_CMD_BMP \| \
	427	CFG_CMD_BSP \| \
	428	CFG_CMD_CACHE \| \
	429	CFG_CMD_DATE \| \
	430	CFG_CMD_DOC \| \
	431	CFG_CMD_DTT \| \
	432	CFG_CMD_EEPROM \| \
	433	CFG_CMD_ELF \| \
	434	CFG_CMD_FAT \| \
	435	CFG_CMD_FDC \| \
	436	CFG_CMD_FDOS \| \
	437	CFG_CMD_HWFLOW \| \
	438	CFG_CMD_IDE \| \
	439	CFG_CMD_I2C \| \
	440	CFG_CMD_JFFS2 \| \
	441	CFG_CMD_KGDB \| \
	442	CFG_CMD_NAND \| \
	443	CFG_CMD_MMC \| \
	444	CFG_CMD_MII \| \
	445	CFG_CMD_PCI \| \
446	CFG_CMD_PCMCIA \| \
447	CFG_CMD_SCSI \| \
448	CFG_CMD_SPI \| \
449	CFG_CMD_VFD \| \
450	CFG_CMD_USB ) )
451
452
453	#include <cmd_confdefs.h>
454
455	/*------------------------------------------------------------------------
456	* KGDB
457	----------------------------------------------------------------------/
458	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
459	#define CONFIG_KGDB_BAUDRATE 9600
460	#endif
461
462	/*------------------------------------------------------------------------
463	* MISC
464	----------------------------------------------------------------------/
465	#define CFG_LONGHELP /* undef to save memory */
466	#define CFG_PROMPT "DK1S10 > " /* Monitor Command Prompt */
467	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
468	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
469	#define CFG_MAXARGS 16 /* max number of command args*/
470	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
471
ec4c544b	472	/* Default load address */
c935d3bd	473	#if (CFG_SRAM_SIZE != 0)
ec4c544b WD	474
	475	/* default in SRAM */
	476	#define CFG_LOAD_ADDR CFG_SRAM_BASE
	477
	478	#elif (CFG_SDRAM_SIZE != 0)
	479
	480	/* default in SDRAM */
	481	#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
	482	#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
	483	#else
	484	#define CFG_LOAD_ADDR CFG_SDRAM_BASE
	485	#endif
	486
c935d3bd	487	#else
ec4c544b	488	#undef CFG_LOAD_ADDR /* force error break */
c935d3bd WD	489	#endif
c935d3bd WD	490
ec4c544b WD	491
ec4c544b WD	492	/* MEM test area */
c935d3bd	493	#if (CFG_SDRAM_SIZE != 0)
ec4c544b WD	494
	495	/* SDRAM begin to stack area (1MB stack) */
	496	#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
	497	#define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
	498	#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024))
	499	#else
	500	#define CFG_MEMTEST_START CFG_SDRAM_BASE
	501	#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024))
	502	#endif
	503
c935d3bd	504	#else
ec4c544b	505	#undef CFG_MEMTEST_START /* force error break */
c935d3bd WD	506	#undef CFG_MEMTEST_END
	507	#endif
	508
	509
	510	#endif /* __CONFIG_H */