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13fdf8a6 SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
13fdf8a6 SR |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
c837dcb1 WD |
21 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
22 | #define CONFIG_DP405 1 /* ...on a DP405 board */ | |
13fdf8a6 | 23 | |
2ae18241 WD |
24 | #define CONFIG_SYS_TEXT_BASE 0xFFFD0000 |
25 | ||
c837dcb1 WD |
26 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
27 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
13fdf8a6 | 28 | |
a20b27a3 | 29 | #define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ |
13fdf8a6 SR |
30 | |
31 | #define CONFIG_BAUDRATE 9600 | |
32 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
33 | ||
34 | #undef CONFIG_BOOTARGS | |
a20b27a3 SR |
35 | #undef CONFIG_BOOTCOMMAND |
36 | ||
37 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
38 | ||
6d0f6bcf | 39 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
13fdf8a6 | 40 | |
3c3227f3 JL |
41 | /* |
42 | * Command line configuration. | |
43 | */ | |
44 | #include <config_cmd_default.h> | |
45 | ||
46 | #define CONFIG_CMD_BSP | |
3c3227f3 | 47 | #define CONFIG_CMD_ELF |
3c3227f3 JL |
48 | #define CONFIG_CMD_I2C |
49 | #define CONFIG_CMD_EEPROM | |
50 | ||
de47a34d | 51 | #undef CONFIG_CMD_NET |
ee8028b7 | 52 | #undef CONFIG_CMD_NFS |
13fdf8a6 | 53 | |
c837dcb1 | 54 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
13fdf8a6 | 55 | |
c837dcb1 | 56 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
13fdf8a6 | 57 | |
a20b27a3 SR |
58 | #define CONFIG_PRAM 2 /* reserve 2 kB "protected RAM" */ |
59 | ||
13fdf8a6 SR |
60 | /* |
61 | * Miscellaneous configurable options | |
62 | */ | |
6d0f6bcf | 63 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
13fdf8a6 | 64 | |
6d0f6bcf | 65 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
13fdf8a6 | 66 | |
3c3227f3 | 67 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 68 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
13fdf8a6 | 69 | #else |
6d0f6bcf | 70 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
13fdf8a6 | 71 | #endif |
6d0f6bcf JCPV |
72 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
73 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
74 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
13fdf8a6 | 75 | |
6d0f6bcf | 76 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
13fdf8a6 | 77 | |
6d0f6bcf | 78 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
13fdf8a6 | 79 | |
6d0f6bcf JCPV |
80 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
81 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
13fdf8a6 | 82 | |
550650dd SR |
83 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
84 | #define CONFIG_SYS_NS16550 | |
85 | #define CONFIG_SYS_NS16550_SERIAL | |
86 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
87 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
88 | ||
6d0f6bcf | 89 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 90 | #define CONFIG_SYS_BASE_BAUD 691200 |
13fdf8a6 SR |
91 | |
92 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 93 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
13fdf8a6 SR |
94 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
95 | 57600, 115200, 230400, 460800, 921600 } | |
96 | ||
6d0f6bcf JCPV |
97 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
98 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
13fdf8a6 | 99 | |
13fdf8a6 SR |
100 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
101 | ||
c837dcb1 | 102 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
13fdf8a6 | 103 | |
13fdf8a6 SR |
104 | /* |
105 | * For booting Linux, the board info and command line data | |
106 | * have to be in the first 8 MB of memory, since this is | |
107 | * the maximum mapped by the Linux kernel during initialization. | |
108 | */ | |
6d0f6bcf | 109 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
13fdf8a6 SR |
110 | /*----------------------------------------------------------------------- |
111 | * FLASH organization | |
112 | */ | |
113 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ | |
114 | ||
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
116 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
13fdf8a6 | 117 | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
119 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
13fdf8a6 | 120 | |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
122 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
123 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
13fdf8a6 SR |
124 | /* |
125 | * The following defines are added for buggy IOP480 byte interface. | |
126 | * All other boards should use the standard values (CPCI405 etc.) | |
127 | */ | |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
129 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
130 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
13fdf8a6 | 131 | |
6d0f6bcf | 132 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
13fdf8a6 | 133 | |
13fdf8a6 SR |
134 | /*----------------------------------------------------------------------- |
135 | * Start addresses for the final memory configuration | |
136 | * (Set up by the startup code) | |
6d0f6bcf | 137 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
13fdf8a6 | 138 | */ |
6d0f6bcf | 139 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
de47a34d | 140 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE |
14d0a02a WD |
141 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
142 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) | |
de47a34d | 143 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
6d0f6bcf JCPV |
144 | |
145 | #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) | |
146 | # define CONFIG_SYS_RAMBOOT 1 | |
13fdf8a6 | 147 | #else |
6d0f6bcf | 148 | # undef CONFIG_SYS_RAMBOOT |
13fdf8a6 SR |
149 | #endif |
150 | ||
151 | /*----------------------------------------------------------------------- | |
152 | * Environment Variable setup | |
153 | */ | |
bb1f8b4f | 154 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
155 | #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
156 | #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ | |
13fdf8a6 SR |
157 | /* total size of a CAT24WC16 is 2048 bytes */ |
158 | ||
13fdf8a6 SR |
159 | /*----------------------------------------------------------------------- |
160 | * I2C EEPROM (CAT24WC16) for environment | |
161 | */ | |
880540de DE |
162 | #define CONFIG_SYS_I2C |
163 | #define CONFIG_SYS_I2C_PPC4XX | |
164 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
165 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
166 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
13fdf8a6 | 167 | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
169 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
c837dcb1 | 170 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
172 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
13fdf8a6 | 173 | /* 16 byte page write mode using*/ |
c837dcb1 | 174 | /* last 4 bits of the address */ |
6d0f6bcf | 175 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
13fdf8a6 | 176 | |
13fdf8a6 SR |
177 | /*----------------------------------------------------------------------- |
178 | * External Bus Controller (EBC) Setup | |
179 | */ | |
180 | ||
c837dcb1 | 181 | #define CAN_BA 0xF0000000 /* CAN Base Address */ |
13fdf8a6 | 182 | |
c837dcb1 | 183 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
185 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
13fdf8a6 | 186 | |
c837dcb1 | 187 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
189 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
13fdf8a6 SR |
190 | |
191 | /*----------------------------------------------------------------------- | |
192 | * FPGA stuff | |
193 | */ | |
13fdf8a6 | 194 | /* FPGA program pin configuration */ |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ |
196 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ | |
197 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ | |
198 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ | |
199 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ | |
13fdf8a6 SR |
200 | |
201 | /*----------------------------------------------------------------------- | |
202 | * Definitions for initial stack pointer and data area (in data cache) | |
203 | */ | |
204 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 205 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
13fdf8a6 SR |
206 | |
207 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
209 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
210 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 211 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
13fdf8a6 | 212 | |
25ddd1fb | 213 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 214 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
13fdf8a6 SR |
215 | |
216 | /*----------------------------------------------------------------------- | |
217 | * Definitions for GPIO setup (PPC405EP specific) | |
218 | * | |
c837dcb1 WD |
219 | * GPIO0[0] - External Bus Controller BLAST output |
220 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
13fdf8a6 SR |
221 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
222 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
223 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
224 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
225 | * GPIO0[28-29] - UART1 data signal input/output | |
226 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs | |
227 | */ | |
c837dcb1 WD |
228 | /* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ |
229 | /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ | |
230 | /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ | |
13fdf8a6 | 231 | /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ |
afabb498 SR |
232 | #define CONFIG_SYS_GPIO0_OSRL 0x40000540 /* 0 ... 15 */ |
233 | #define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ | |
234 | #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ | |
235 | #define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ | |
236 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ | |
237 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ | |
de47a34d | 238 | #define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */ |
13fdf8a6 | 239 | |
13fdf8a6 SR |
240 | /* |
241 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
242 | * This value will be set if iic boot eprom is disabled. | |
243 | */ | |
c837dcb1 WD |
244 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
245 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
13fdf8a6 SR |
246 | |
247 | #endif /* __CONFIG_H */ |