[people/ms/u-boot.git] / include / configs / DP405.h

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_DP405		1	/* ...on a DP405 board		*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ	33333334 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#define CONFIG_RAMBOOTCOMMAND							\
	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
	"bootm ffc00000 ffca0000"
#define CONFIG_NFSBOOTCOMMAND							\
	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
	"bootm ffc00000"
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/

#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_BSP	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_ELF	| \
				CFG_CMD_DATE	| \
				CFG_CMD_I2C	| \
				CFG_CMD_EEPROM	)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
#define CFG_BASE_BAUD	    691200
#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#if 0 /* test-only */
#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
#endif

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFC0000
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/

#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
# define CFG_RAMBOOT		1
#else
# undef CFG_RAMBOOT
#endif

/*-----------------------------------------------------------------------
 * Environment Variable setup
 */
#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
				   /* total size of a CAT24WC16 is 2048 bytes */

#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
					/* have only 8kB, 16kB is save here	*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
#define RTC_BA		0xF0000500	    /* RTC Base Address			*/

/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
#define CFG_EBC_PB0AP		0x92015480
#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

#if 0 /* test-only */
/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
#define CFG_EBC_PB1AP		0x92015480
#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
#endif

/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/*-----------------------------------------------------------------------
 * FPGA stuff
 */
#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */

/* FPGA program pin configuration */
#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM	  1

/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/

#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup (PPC405EP specific)
 *
 * GPIO0[0]	- External Bus Controller BLAST output
 * GPIO0[1-9]	- Instruction trace outputs -> GPIO
 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 * GPIO0[24-27] - UART0 control signal inputs/outputs
 * GPIO0[28-29] - UART1 data signal input/output
 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 */
/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
#define CFG_GPIO0_OSRH		0x40000540  /*	0 ... 15 */
#define CFG_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
#define CFG_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
#define CFG_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
#define CFG_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
#define CFG_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
#define CFG_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

/*
 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 * This value will be set if iic boot eprom is disabled.
 */
#if 0
#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
#endif
#if 0
#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
#endif
#if 1
#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
13fdf8a6 SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405EP 1 /* This is a PPC405 CPU */
c837dcb1 WD	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	38	#define CONFIG_DP405 1 /* ...on a DP405 board */
13fdf8a6	39
c837dcb1 WD	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c837dcb1 WD	41	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
13fdf8a6	42
c837dcb1	43	#define CONFIG_SYS_CLK_FREQ 33333334 /* external frequency to pll */
13fdf8a6 SR	44
	45	#define CONFIG_BAUDRATE 9600
	46	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	47
	48	#undef CONFIG_BOOTARGS
	49	#define CONFIG_RAMBOOTCOMMAND \
	50	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \
	51	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
	52	"bootm ffc00000 ffca0000"
	53	#define CONFIG_NFSBOOTCOMMAND \
	54	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	55	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
	56	"bootm ffc00000"
	57	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	58
	59	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	60	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	61
	62	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	63	#define CONFIG_PHY_ADDR 0 /* PHY address */
13fdf8a6 SR	64
	65	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
	66	CFG_CMD_BSP \| \
	67	CFG_CMD_DHCP \| \
	68	CFG_CMD_IRQ \| \
	69	CFG_CMD_ELF \| \
	70	CFG_CMD_DATE \| \
	71	CFG_CMD_I2C \| \
c837dcb1	72	CFG_CMD_EEPROM )
13fdf8a6 SR	73
	74	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	75	#include <cmd_confdefs.h>
	76
c837dcb1	77	#undef CONFIG_WATCHDOG /* watchdog disabled */
13fdf8a6	78
c837dcb1 WD	79	#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
c837dcb1 WD	80	#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
13fdf8a6	81
c837dcb1	82	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
13fdf8a6 SR	83
	84	/*
	85	* Miscellaneous configurable options
	86	*/
	87	#define CFG_LONGHELP /* undef to save memory */
	88	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	89
	90	#undef CFG_HUSH_PARSER /* use "hush" command parser */
	91	#ifdef CFG_HUSH_PARSER
c837dcb1	92	#define CFG_PROMPT_HUSH_PS2 "> "
13fdf8a6 SR	93	#endif
	94
	95	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
c837dcb1	96	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
13fdf8a6	97	#else
c837dcb1	98	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
13fdf8a6 SR	99	#endif
	100	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	101	#define CFG_MAXARGS 16 /* max number of command args */
	102	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	103
c837dcb1	104	#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
13fdf8a6	105
c837dcb1	106	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
13fdf8a6 SR	107
	108	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	109	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	110
c837dcb1 WD	111	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	112	#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	113	#define CFG_BASE_BAUD 691200
	114	#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
13fdf8a6 SR	115
13fdf8a6 SR	116	/* The following table includes the supported baudrates */
c837dcb1	117	#define CFG_BAUDRATE_TABLE \
13fdf8a6 SR	118	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	119	57600, 115200, 230400, 460800, 921600 }
	120
	121	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	122	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	123
c837dcb1	124	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
13fdf8a6 SR	125
	126	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	127
c837dcb1	128	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
13fdf8a6	129
c837dcb1	130	#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
13fdf8a6 SR	131
	132	/*-----------------------------------------------------------------------
	133	* PCI stuff
	134	*-----------------------------------------------------------------------
	135	*/
c837dcb1 WD	136	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	137	#define PCI_HOST_FORCE 1 /* configure as pci host */
	138	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	139
	140	#define CONFIG_PCI /* include pci support */
	141	#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
	142	#undef CONFIG_PCI_PNP /* do pci plug-and-play */
	143	/* resource configuration */
	144
	145	#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	146
	147	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	148	#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	149	#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	150	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	151	#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
	152	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	153	#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	154	#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	155	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
13fdf8a6 SR	156
	157	/*
	158	* For booting Linux, the board info and command line data
	159	* have to be in the first 8 MB of memory, since this is
	160	* the maximum mapped by the Linux kernel during initialization.
	161	*/
	162	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	163	/*-----------------------------------------------------------------------
	164	* FLASH organization
	165	*/
	166	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
	167
	168	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	169	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	170
	171	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	172	#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
	173
c837dcb1 WD	174	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	175	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	176	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
13fdf8a6 SR	177	/*
	178	* The following defines are added for buggy IOP480 byte interface.
	179	* All other boards should use the standard values (CPCI405 etc.)
	180	*/
c837dcb1 WD	181	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	182	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	183	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
13fdf8a6	184
c837dcb1	185	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
13fdf8a6 SR	186
13fdf8a6 SR	187	#if 0 /* test-only */
c837dcb1 WD	188	#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
c837dcb1 WD	189	#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
13fdf8a6 SR	190	#endif
	191
	192	/*-----------------------------------------------------------------------
	193	* Start addresses for the final memory configuration
	194	* (Set up by the startup code)
	195	* Please note that CFG_SDRAM_BASE _must_ start at 0
	196	*/
	197	#define CFG_SDRAM_BASE 0x00000000
	198	#define CFG_FLASH_BASE 0xFFFC0000
	199	#define CFG_MONITOR_BASE TEXT_BASE
	200	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	201	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
	202
	203	#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
	204	# define CFG_RAMBOOT 1
	205	#else
	206	# undef CFG_RAMBOOT
	207	#endif
	208
	209	/*-----------------------------------------------------------------------
	210	* Environment Variable setup
	211	*/
c837dcb1 WD	212	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	213	#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
	214	#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
13fdf8a6 SR	215	/* total size of a CAT24WC16 is 2048 bytes */
	216
	217	#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
c837dcb1	218	#define CFG_NVRAM_SIZE 242 /* NVRAM size */
13fdf8a6 SR	219
	220	/*-----------------------------------------------------------------------
	221	* I2C EEPROM (CAT24WC16) for environment
	222	*/
	223	#define CONFIG_HARD_I2C /* I2c with hardware support */
	224	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	225	#define CFG_I2C_SLAVE 0x7F
	226
	227	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
c837dcb1 WD	228	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1 WD	229	/* mask of address bits that overflow into the "EEPROM chip address" */
13fdf8a6 SR	230	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	231	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	232	/* 16 byte page write mode using*/
c837dcb1	233	/* last 4 bits of the address */
13fdf8a6 SR	234	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	235	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	236
	237	/*-----------------------------------------------------------------------
	238	* Cache Configuration
	239	*/
c837dcb1 WD	240	#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
c837dcb1 WD	241	/* have only 8kB, 16kB is save here */
13fdf8a6 SR	242	#define CFG_CACHELINE_SIZE 32 /* ... */
	243	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	244	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	245	#endif
	246
	247	/*-----------------------------------------------------------------------
	248	* External Bus Controller (EBC) Setup
	249	*/
	250
c837dcb1 WD	251	#define CAN_BA 0xF0000000 /* CAN Base Address */
c837dcb1 WD	252	#define RTC_BA 0xF0000500 /* RTC Base Address */
13fdf8a6	253
c837dcb1 WD	254	/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
	255	#define CFG_EBC_PB0AP 0x92015480
	256	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
13fdf8a6 SR	257
13fdf8a6 SR	258	#if 0 /* test-only */
c837dcb1 WD	259	/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
	260	#define CFG_EBC_PB1AP 0x92015480
	261	#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
13fdf8a6 SR	262	#endif
13fdf8a6 SR	263
c837dcb1 WD	264	/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
	265	#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	266	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
13fdf8a6 SR	267
	268	/*-----------------------------------------------------------------------
	269	* FPGA stuff
	270	*/
c837dcb1 WD	271	#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
c837dcb1 WD	272	#define CFG_FPGA_MAX_SIZE 321024 / 32kByte is enough for CPLD */
13fdf8a6 SR	273
13fdf8a6 SR	274	/* FPGA program pin configuration */
c837dcb1 WD	275	#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
	276	#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
	277	#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
	278	#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */
	279	#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
13fdf8a6 SR	280
	281	/*-----------------------------------------------------------------------
	282	* Definitions for initial stack pointer and data area (in data cache)
	283	*/
	284	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
c837dcb1	285	#define CFG_TEMP_STACK_OCM 1
13fdf8a6 SR	286
	287	/* On Chip Memory location */
	288	#define CFG_OCM_DATA_ADDR 0xF8000000
	289	#define CFG_OCM_DATA_SIZE 0x1000
	290	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
	291	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
	292
	293	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	294	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c837dcb1	295	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
13fdf8a6 SR	296
	297	/*-----------------------------------------------------------------------
	298	* Definitions for GPIO setup (PPC405EP specific)
	299	*
c837dcb1 WD	300	* GPIO0[0] - External Bus Controller BLAST output
c837dcb1 WD	301	* GPIO0[1-9] - Instruction trace outputs -> GPIO
13fdf8a6 SR	302	* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
	303	* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
	304	* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
	305	* GPIO0[24-27] - UART0 control signal inputs/outputs
	306	* GPIO0[28-29] - UART1 data signal input/output
	307	* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
	308	*/
c837dcb1 WD	309	/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
	310	/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
	311	/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
13fdf8a6	312	/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
c837dcb1 WD	313	#define CFG_GPIO0_OSRH 0x40000540 /* 0 ... 15 */
	314	#define CFG_GPIO0_OSRL 0x00000110 /* 16 ... 31 */
	315	#define CFG_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */
	316	#define CFG_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
	317	#define CFG_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
	318	#define CFG_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
	319	#define CFG_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
13fdf8a6 SR	320
	321	/*
	322	* Internal Definitions
	323	*
	324	* Boot Flags
	325	*/
	326	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	327	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	328
	329	/*
	330	* Default speed selection (cpu_plb_opb_ebc) in mhz.
	331	* This value will be set if iic boot eprom is disabled.
	332	*/
	333	#if 0
c837dcb1 WD	334	#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
c837dcb1 WD	335	#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
13fdf8a6 SR	336	#endif
13fdf8a6 SR	337	#if 0
c837dcb1 WD	338	#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
c837dcb1 WD	339	#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
13fdf8a6 SR	340	#endif
13fdf8a6 SR	341	#if 1
c837dcb1 WD	342	#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
c837dcb1 WD	343	#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
13fdf8a6 SR	344	#endif
	345
	346	#endif /* __CONFIG_H */