[people/ms/u-boot.git] / include / configs / DU405.h

/*
 * (C) Copyright 2001
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_DU405		1	/* ...on a DU405 board		*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND	"bootm fff00000"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/

#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_PCI	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_IDE	| \
				CFG_CMD_ELF	| \
				CFG_CMD_DATE	| \
				CFG_CMD_EEPROM	)

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_RTC_MC146818		/* BQ3285 is MC146818 compatible*/
#define CFG_RTC_REG_BASE_ADDR	 0xF0000080 /* RTC Base Address		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_EXT_SERIAL_CLOCK	11059200  /* use external serial clock	*/

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CFG_PCI_PTM2LA	0xffe00000	/* point to flash		*/
#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/

#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	0xF0100000
#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFD0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC08) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
				   /* total size of a CAT24WC08 is 1024 bytes */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		8192	/* For IBM 405 CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

#define FLASH0_BA	0xFFC00000	    /* FLASH 0 Base Address		*/
#define FLASH1_BA	0xFF800000	    /* FLASH 1 Base Address		*/
#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
#define DUART_BA	0xF0300000	    /* DUART Base Address		*/
#define CF_BA		0xF0100000	    /* CompactFlash Base Address	*/
#define SRAM_BA		0xF0200000	    /* SRAM Base Address		*/
#define DURAG_IO_BA	0xF0400000	    /* DURAG Bus IO Base Address	*/
#define DURAG_MEM_BA	0xF0500000	    /* DURAG Bus Mem Base Address	*/

#define FPGA_MODE_REG	(DUART_BA+0x80)	    /* FPGA Mode Register		*/

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CFG_EBC_PB0AP	0x92015480
#define CFG_EBC_PB0CR	FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1) initialization					*/
#define CFG_EBC_PB1AP	0x92015480
#define CFG_EBC_PB1CR	FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (CAN0) initialization						*/
#define CFG_EBC_PB2AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (DUART) initialization						*/
#define CFG_EBC_PB3AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR	DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 4 (CompactFlash IDE) initialization				*/
#define CFG_EBC_PB4AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB4CR	CF_BA | 0x1A000	    /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 5 (SRAM) initialization						*/
#define CFG_EBC_PB5AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB5CR	SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 6 (DURAG Bus IO Space) initialization				*/
#define CFG_EBC_PB6AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB6CR	DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/

/* Memory Bank 7 (DURAG Bus Mem Space) initialization				*/
#define CFG_EBC_PB7AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB7CR	DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */

/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM	  1

/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000

#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1 WD	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	38	#define CONFIG_DU405 1 /* ...on a DU405 board */
c609719b	39
c837dcb1	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c609719b	41
c837dcb1	42	#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
c609719b WD	43
	44	#define CONFIG_BAUDRATE 9600
	45	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	46
	47	#undef CONFIG_BOOTARGS
	48	#define CONFIG_BOOTCOMMAND "bootm fff00000"
	49
	50	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	51	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	52
	53	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	54	#define CONFIG_PHY_ADDR 0 /* PHY address */
c609719b WD	55
	56	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
	57	CFG_CMD_PCI \| \
	58	CFG_CMD_IRQ \| \
	59	CFG_CMD_IDE \| \
	60	CFG_CMD_ELF \| \
	61	CFG_CMD_DATE \| \
c837dcb1	62	CFG_CMD_EEPROM )
c609719b WD	63
	64	#define CONFIG_MAC_PARTITION
	65	#define CONFIG_DOS_PARTITION
	66
	67	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	68	#include <cmd_confdefs.h>
	69
	70	#undef CONFIG_WATCHDOG /* watchdog disabled */
	71
c837dcb1 WD	72	#define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/
c837dcb1 WD	73	#define CFG_RTC_REG_BASE_ADDR 0xF0000080 /* RTC Base Address */
c609719b	74
c837dcb1	75	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c609719b WD	76
	77	/*
	78	* Miscellaneous configurable options
	79	*/
	80	#define CFG_LONGHELP /* undef to save memory */
	81	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	82	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
c837dcb1	83	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	84	#else
c837dcb1	85	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
c609719b WD	86	#endif
	87	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	88	#define CFG_MAXARGS 16 /* max number of command args */
	89	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	90
c837dcb1	91	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c609719b WD	92
	93	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	94	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	95
c837dcb1	96	#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */
c609719b WD	97
c609719b WD	98	/* The following table includes the supported baudrates */
c837dcb1	99	#define CFG_BAUDRATE_TABLE \
8bde7f77 WD	100	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	101	57600, 115200, 230400, 460800, 921600 }
c609719b WD	102
	103	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	104	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	105
c837dcb1	106	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b WD	107
	108	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	109
	110	/*-----------------------------------------------------------------------
	111	* PCI stuff
	112	*-----------------------------------------------------------------------
	113	*/
c837dcb1 WD	114	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	115	#define PCI_HOST_FORCE 1 /* configure as pci host */
	116	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
c609719b	117
c837dcb1 WD	118	#define CONFIG_PCI /* include pci support */
	119	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	120	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	121	/* resource configuration */
c609719b	122
c837dcb1	123	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
ad10dd9a	124
c837dcb1	125	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
ad10dd9a	126
c837dcb1 WD	127	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	128	#define CFG_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */
	129	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	130	#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
	131	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	132	#define CFG_PCI_PTM2LA 0xffe00000 /* point to flash */
	133	#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
	134	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
c609719b WD	135
	136	/*-----------------------------------------------------------------------
	137	* IDE/ATA stuff
	138	*-----------------------------------------------------------------------
	139	*/
c837dcb1 WD	140	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	141	#undef CONFIG_IDE_LED /* no led for ide supported */
	142	#undef CONFIG_IDE_RESET /* no reset for ide supported */
c609719b	143
c837dcb1 WD	144	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
c837dcb1 WD	145	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 1 drives per IDE bus */
c609719b	146
c837dcb1 WD	147	#define CFG_ATA_BASE_ADDR 0xF0100000
c837dcb1 WD	148	#define CFG_ATA_IDE0_OFFSET 0x0000
c609719b WD	149
c609719b WD	150	#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
c837dcb1	151	#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
c609719b WD	152	#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
	153
	154	/*-----------------------------------------------------------------------
	155	* Start addresses for the final memory configuration
	156	* (Set up by the startup code)
	157	* Please note that CFG_SDRAM_BASE _must_ start at 0
	158	*/
	159	#define CFG_SDRAM_BASE 0x00000000
	160	#define CFG_FLASH_BASE 0xFFFD0000
	161	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	162	#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
	163	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	164
	165	/*
	166	* For booting Linux, the board info and command line data
	167	* have to be in the first 8 MB of memory, since this is
	168	* the maximum mapped by the Linux kernel during initialization.
	169	*/
	170	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	171	/*-----------------------------------------------------------------------
	172	* FLASH organization
	173	*/
	174	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	175	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	176
	177	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	178	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	179
c837dcb1 WD	180	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	181	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	182	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c609719b WD	183	/*
	184	* The following defines are added for buggy IOP480 byte interface.
	185	* All other boards should use the standard values (CPCI405 etc.)
	186	*/
c837dcb1 WD	187	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	188	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	189	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
c609719b	190
c837dcb1	191	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c609719b WD	192
	193	/*-----------------------------------------------------------------------
	194	* I2C EEPROM (CAT24WC08) for environment
	195	*/
	196	#define CONFIG_HARD_I2C /* I2c with hardware support */
	197	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	198	#define CFG_I2C_SLAVE 0x7F
	199
	200	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
c837dcb1 WD	201	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1 WD	202	/* mask of address bits that overflow into the "EEPROM chip address" */
c609719b WD	203	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	204	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	205	/* 16 byte page write mode using*/
c837dcb1	206	/* last 4 bits of the address */
c609719b WD	207	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	208	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	209
c837dcb1 WD	210	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	211	#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
	212	#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
8bde7f77	213	/* total size of a CAT24WC08 is 1024 bytes */
c609719b WD	214
	215	/*-----------------------------------------------------------------------
	216	* Cache Configuration
	217	*/
	218	#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
	219	#define CFG_CACHELINE_SIZE 32 /* ... */
	220	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	221	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	222	#endif
	223
	224	/*
	225	* Init Memory Controller:
	226	*
	227	* BR0/1 and OR0/1 (FLASH)
	228	*/
	229
	230	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
	231	#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
	232
	233	/*-----------------------------------------------------------------------
	234	* External Bus Controller (EBC) Setup
	235	*/
	236
c837dcb1 WD	237	#define FLASH0_BA 0xFFC00000 /* FLASH 0 Base Address */
	238	#define FLASH1_BA 0xFF800000 /* FLASH 1 Base Address */
	239	#define CAN_BA 0xF0000000 /* CAN Base Address */
	240	#define DUART_BA 0xF0300000 /* DUART Base Address */
	241	#define CF_BA 0xF0100000 /* CompactFlash Base Address */
	242	#define SRAM_BA 0xF0200000 /* SRAM Base Address */
	243	#define DURAG_IO_BA 0xF0400000 /* DURAG Bus IO Base Address */
	244	#define DURAG_MEM_BA 0xF0500000 /* DURAG Bus Mem Base Address */
c609719b	245
c837dcb1	246	#define FPGA_MODE_REG (DUART_BA+0x80) /* FPGA Mode Register */
c609719b	247
c837dcb1 WD	248	/* Memory Bank 0 (Flash Bank 0) initialization */
	249	#define CFG_EBC_PB0AP 0x92015480
	250	#define CFG_EBC_PB0CR FLASH0_BA \| 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c609719b	251
c837dcb1 WD	252	/* Memory Bank 1 (Flash Bank 1) initialization */
	253	#define CFG_EBC_PB1AP 0x92015480
	254	#define CFG_EBC_PB1CR FLASH1_BA \| 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
c609719b	255
c837dcb1 WD	256	/* Memory Bank 2 (CAN0) initialization */
	257	#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	258	#define CFG_EBC_PB2CR CAN_BA \| 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
c609719b	259
c837dcb1 WD	260	/* Memory Bank 3 (DUART) initialization */
	261	#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	262	#define CFG_EBC_PB3CR DUART_BA \| 0x18000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
c609719b	263
c837dcb1 WD	264	/* Memory Bank 4 (CompactFlash IDE) initialization */
	265	#define CFG_EBC_PB4AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	266	#define CFG_EBC_PB4CR CF_BA \| 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
c609719b	267
c837dcb1 WD	268	/* Memory Bank 5 (SRAM) initialization */
	269	#define CFG_EBC_PB5AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	270	#define CFG_EBC_PB5CR SRAM_BA \| 0x1A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
c609719b	271
c837dcb1 WD	272	/* Memory Bank 6 (DURAG Bus IO Space) initialization */
	273	#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	274	#define CFG_EBC_PB6CR DURAG_IO_BA \| 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
c609719b	275
c837dcb1 WD	276	/* Memory Bank 7 (DURAG Bus Mem Space) initialization */
	277	#define CFG_EBC_PB7AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	278	#define CFG_EBC_PB7CR DURAG_MEM_BA \| 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
c609719b WD	279
	280
	281	/*-----------------------------------------------------------------------
	282	* Definitions for initial stack pointer and data area (in DPRAM)
	283	*/
	284
	285	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
c837dcb1	286	#define CFG_TEMP_STACK_OCM 1
c609719b WD	287
	288	/* On Chip Memory location */
	289	#define CFG_OCM_DATA_ADDR 0xF8000000
	290	#define CFG_OCM_DATA_SIZE 0x1000
	291
	292	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
	293	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
	294	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	295	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c837dcb1	296	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
c609719b WD	297
	298
	299	/*
	300	* Internal Definitions
	301	*
	302	* Boot Flags
	303	*/
	304	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	305	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	306
	307	#endif /* __CONFIG_H */