[people/ms/u-boot.git] / include / configs / EB+MCF-EV123.h

/*
 * Configuation settings for the BuS EB+MCF-EV123 boards.
 *
 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _CONFIG_EB_MCF_EV123_H_
#define _CONFIG_EB_MCF_EV123_H_

#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP

/*----------------------------------------------------------------------*
 * High Level Configuration Options (easy to change)                    *
 *----------------------------------------------------------------------*/

#define	CONFIG_MCF52x2			/* define processor family */
#define CONFIG_M5282			/* define processor type */
#define CONFIG_EB_MCF_EV123

#define CONFIG_MISC_INIT_R

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }

#undef	CONFIG_MONITOR_IS_IN_RAM		/* starts uboot direct */

#define CONFIG_BOOTCOMMAND "printenv"

/*----------------------------------------------------------------------*
 * Options								*
 *----------------------------------------------------------------------*/

#define CONFIG_BOOT_RETRY_TIME	-1
#define CONFIG_RESET_TO_RETRY
#define CONFIG_SPLASH_SCREEN

/*----------------------------------------------------------------------*
 * Configuration for environment					*
 * Environment is in the second sector of the first 256k of flash	*
 *----------------------------------------------------------------------*/

#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_ADDR		0xF003C000	/* End of 256K */
#define CONFIG_ENV_SECT_SIZE	0x4000
#define CONFIG_ENV_IS_IN_FLASH	1
#else
#define CONFIG_ENV_ADDR		0xFFE04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#undef CONFIG_CMD_LOADB
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET

#define CONFIG_MCFTMR


#define CONFIG_BOOTDELAY	5
#define CONFIG_HUSH_PARSER
#define CONFIG_SYS_PROMPT	"\nEV123 U-Boot> "
#define	CONFIG_SYS_LONGHELP	1

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE 	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define	CONFIG_SYS_MAXARGS	16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

#define CONFIG_SYS_LOAD_ADDR		0x20000

#define CONFIG_SYS_MEMTEST_START	0x100000
#define CONFIG_SYS_MEMTEST_END		0x400000
/*#define CONFIG_SYS_DRAM_TEST		1 */
#undef CONFIG_SYS_DRAM_TEST

/*----------------------------------------------------------------------*
 * Clock and PLL Configuration						*
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_HZ			10000000
#define	CONFIG_SYS_CLK			58982400       /* 9,8304MHz * 6 */

/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */

#define CONFIG_SYS_MFD		0x01	/* PLL Multiplication Factor Devider */
#define CONFIG_SYS_RFD		0x00	/* PLL Reduce Frecuency Devider */

/*----------------------------------------------------------------------*
 * Network								*
 *----------------------------------------------------------------------*/

#define CONFIG_MCFFEC
#define CONFIG_NET_MULTI		1
#define CONFIG_MII			1
#define CONFIG_MII_INIT			1
#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_RX_ETH_BUFFER	8
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#define CONFIG_SYS_FEC0_PINMUX		0
#define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#define MCFFEC_TOUT_LOOP		50000

#define CONFIG_ETHADDR			00:CF:52:82:EB:01
#define CONFIG_OVERWRITE_ETHADDR_ONCE

/*-------------------------------------------------------------------------
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 *-----------------------------------------------------------------------*/

#define	CONFIG_SYS_MBAR			0x40000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 *-----------------------------------------------------------------------*/

#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_END		0x10000
#define CONFIG_SYS_GBL_DATA_SIZE	64
#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE1		0x00000000
#define	CONFIG_SYS_SDRAM_SIZE1		16	/* SDRAM size in MB */

#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_SDRAM_BASE1
#define	CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_SDRAM_SIZE1


/* If M5282 port is fully implemented the monitor base will be behind
 * the vector table. */
#if (TEXT_BASE !=  CONFIG_SYS_INT_FLASH_BASE)
#define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x400)
#else
#define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define	CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */

#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#define	CONFIG_SYS_INT_FLASH_BASE	0xF0000000
#define CONFIG_SYS_INT_FLASH_ENABLE	0x21

#define	CONFIG_SYS_MAX_FLASH_SECT	35
#define	CONFIG_SYS_MAX_FLASH_BANKS	2
#define	CONFIG_SYS_FLASH_ERASE_TOUT	10000000
#define	CONFIG_SYS_FLASH_PROTECTION

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */

#define CONFIG_SYS_CS0_BASE		0xFFE00000
#define CONFIG_SYS_CS0_CTRL		0x00001980
#define CONFIG_SYS_CS0_MASK		0x001F0001

#define CONFIG_SYS_CS3_BASE		0xE0000000
#define CONFIG_SYS_CS0_CTRL		0x00001980
#define CONFIG_SYS_CS3_MASK		0x000F0001

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
#define CONFIG_SYS_PADDR		0x0000000
#define CONFIG_SYS_PADAT		0x0000000

#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
#define CONFIG_SYS_PBDDR		0x0000000
#define CONFIG_SYS_PBDAT		0x0000000

#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
#define CONFIG_SYS_PCDDR		0x0000000
#define CONFIG_SYS_PCDAT		0x0000000

#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
#define CONFIG_SYS_PCDDR		0x0000000
#define CONFIG_SYS_PCDAT		0x0000000

#define CONFIG_SYS_PEHLPAR		0xC0
#define CONFIG_SYS_PUAPAR		0x0F
#define CONFIG_SYS_DDRUA		0x05
#define CONFIG_SYS_PJPAR		0xFF

/*-----------------------------------------------------------------------
 * VIDEO configuration
 */

#define CONFIG_VIDEO

#ifdef CONFIG_VIDEO
#define	CONFIG_VIDEO_VCXK			1

#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN	2
#define	CONFIG_SYS_VCXK_DOUBLEBUFFERED		1
#define CONFIG_SYS_VCXK_BASE			CONFIG_SYS_CS3_BASE
#define CONFIG_SYS_VCXK_AUTODETECT		1

#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT	MCFGPTB_GPTPORT
#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR		MCFGPTB_GPTDDR
#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN		0x0001

#define CONFIG_SYS_VCXK_ENABLE_PORT		MCFGPTB_GPTPORT
#define CONFIG_SYS_VCXK_ENABLE_DDR		MCFGPTB_GPTDDR
#define CONFIG_SYS_VCXK_ENABLE_PIN		0x0002

#define CONFIG_SYS_VCXK_REQUEST_PORT		MCFGPTB_GPTPORT
#define CONFIG_SYS_VCXK_REQUEST_DDR		MCFGPTB_GPTDDR
#define CONFIG_SYS_VCXK_REQUEST_PIN		0x0004

#define CONFIG_SYS_VCXK_INVERT_PORT		MCFGPIO_PORTE
#define CONFIG_SYS_VCXK_INVERT_DDR		MCFGPIO_DDRE
#define CONFIG_SYS_VCXK_INVERT_PIN		MCFGPIO_PORT2

#endif /* CONFIG_VIDEO */
#endif	/* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/
Commit	Line	Data
9acb626f HS	1	/*
	2	* Configuation settings for the BuS EB+MCF-EV123 boards.
	3	*
35cf3b57	4	* (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
9acb626f HS	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef _CONFIG_EB_MCF_EV123_H_
	26	#define _CONFIG_EB_MCF_EV123_H_
	27
6d0f6bcf	28	#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
b1d71358	29
35cf3b57 JS	30	/----------------------------------------------------------------------
	31	* High Level Configuration Options (easy to change) *
	32	----------------------------------------------------------------------/
9acb626f HS	33
	34	#define CONFIG_MCF52x2 /* define processor family */
	35	#define CONFIG_M5282 /* define processor type */
35cf3b57	36	#define CONFIG_EB_MCF_EV123
9acb626f HS	37
	38	#define CONFIG_MISC_INIT_R
	39
870470db	40	#define CONFIG_MCFUART
6d0f6bcf	41	#define CONFIG_SYS_UART_PORT (0)
9acb626f	42	#define CONFIG_BAUDRATE 9600
6d0f6bcf	43	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
9acb626f	44
35cf3b57	45	#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
9acb626f HS	46
	47	#define CONFIG_BOOTCOMMAND "printenv"
	48
35cf3b57 JS	49	/----------------------------------------------------------------------
	50	* Options *
	51	----------------------------------------------------------------------/
	52
	53	#define CONFIG_BOOT_RETRY_TIME -1
	54	#define CONFIG_RESET_TO_RETRY
	55	#define CONFIG_SPLASH_SCREEN
	56
	57	/----------------------------------------------------------------------
	58	* Configuration for environment *
	59	* Environment is in the second sector of the first 256k of flash *
	60	----------------------------------------------------------------------/
	61
9acb626f	62	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	63	#define CONFIG_ENV_ADDR 0xF003C000 /* End of 256K */
0e8d1586 JCPV	64	#define CONFIG_ENV_SECT_SIZE 0x4000
5a1aceb0	65	#define CONFIG_ENV_IS_IN_FLASH 1
9acb626f	66	#else
0e8d1586 JCPV	67	#define CONFIG_ENV_ADDR 0xFFE04000
0e8d1586 JCPV	68	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	69	#define CONFIG_ENV_IS_IN_FLASH 1
9acb626f HS	70	#endif
9acb626f HS	71
11799434 JL	72	/*
	73	* BOOTP options
	74	*/
	75	#define CONFIG_BOOTP_BOOTFILESIZE
	76	#define CONFIG_BOOTP_BOOTPATH
	77	#define CONFIG_BOOTP_GATEWAY
	78	#define CONFIG_BOOTP_HOSTNAME
	79
dcaa7156 JL	80	/*
	81	* Command line configuration.
	82	*/
	83	#include <config_cmd_default.h>
	84
	85	#undef CONFIG_CMD_LOADB
870470db TL	86	#define CONFIG_CMD_MII
	87	#define CONFIG_CMD_NET
	88
0e0c4357 TL	89	#define CONFIG_MCFTMR
0e0c4357 TL	90
9acb626f HS	91
9acb626f HS	92	#define CONFIG_BOOTDELAY 5
35cf3b57 JS	93	#define CONFIG_HUSH_PARSER
	94	#define CONFIG_SYS_PROMPT "\nEV123 U-Boot> "
	95	#define CONFIG_SYS_LONGHELP 1
9acb626f	96
dcaa7156	97	#if defined(CONFIG_CMD_KGDB)
35cf3b57	98	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
9acb626f	99	#else
35cf3b57	100	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
9acb626f	101	#endif
35cf3b57 JS	102	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	103	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	104	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
9acb626f	105
6d0f6bcf	106	#define CONFIG_SYS_LOAD_ADDR 0x20000
9acb626f	107
6d0f6bcf JCPV	108	#define CONFIG_SYS_MEMTEST_START 0x100000
	109	#define CONFIG_SYS_MEMTEST_END 0x400000
	110	/#define CONFIG_SYS_DRAM_TEST 1 /
	111	#undef CONFIG_SYS_DRAM_TEST
9acb626f	112
35cf3b57 JS	113	/----------------------------------------------------------------------
	114	* Clock and PLL Configuration *
	115	----------------------------------------------------------------------/
6d0f6bcf JCPV	116	#define CONFIG_SYS_HZ 10000000
6d0f6bcf JCPV	117	#define CONFIG_SYS_CLK 58982400 /* 9,8304MHz * 6 */
9acb626f HS	118
	119	/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
	120
35cf3b57 JS	121	#define CONFIG_SYS_MFD 0x01 /* PLL Multiplication Factor Devider */
35cf3b57 JS	122	#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
9acb626f	123
35cf3b57 JS	124	/----------------------------------------------------------------------
	125	* Network *
	126	----------------------------------------------------------------------/
	127
	128	#define CONFIG_MCFFEC
	129	#define CONFIG_NET_MULTI 1
	130	#define CONFIG_MII 1
	131	#define CONFIG_MII_INIT 1
	132	#define CONFIG_SYS_DISCOVER_PHY
	133	#define CONFIG_SYS_RX_ETH_BUFFER 8
	134	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	135
	136	#define CONFIG_SYS_FEC0_PINMUX 0
	137	#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	138	#define MCFFEC_TOUT_LOOP 50000
	139
	140	#define CONFIG_ETHADDR 00:CF:52:82:EB:01
	141	#define CONFIG_OVERWRITE_ETHADDR_ONCE
	142
	143	/*-------------------------------------------------------------------------
9acb626f HS	144	* Low Level Configuration Settings
	145	* (address mappings, register initial values, etc.)
	146	* You should know what you are doing if you make changes here.
35cf3b57 JS	147	-----------------------------------------------------------------------/
	148
	149	#define CONFIG_SYS_MBAR 0x40000000
9acb626f	150
9acb626f HS	151	/*-----------------------------------------------------------------------
9acb626f HS	152	* Definitions for initial stack pointer and data area (in DPRAM)
35cf3b57 JS	153	-----------------------------------------------------------------------/
	154
	155	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
	156	#define CONFIG_SYS_INIT_RAM_END 0x10000
	157	#define CONFIG_SYS_GBL_DATA_SIZE 64
	158	#define CONFIG_SYS_GBL_DATA_OFFSET \
	159	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
6d0f6bcf	160	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
9acb626f HS	161
	162	/*-----------------------------------------------------------------------
	163	* Start addresses for the final memory configuration
	164	* (Set up by the startup code)
6d0f6bcf	165	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
9acb626f	166	*/
6d0f6bcf	167	#define CONFIG_SYS_SDRAM_BASE1 0x00000000
35cf3b57	168	#define CONFIG_SYS_SDRAM_SIZE1 16 /* SDRAM size in MB */
9acb626f	169
6d0f6bcf JCPV	170	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1
6d0f6bcf JCPV	171	#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1
9acb626f	172
9acb626f HS	173
	174	/* If M5282 port is fully implemented the monitor base will be behind
	175	* the vector table. */
6d0f6bcf JCPV	176	#if (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
6d0f6bcf JCPV	177	#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
9acb626f	178	#else
6d0f6bcf	179	#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
9acb626f HS	180	#endif
9acb626f HS	181
6d0f6bcf JCPV	182	#define CONFIG_SYS_MONITOR_LEN 0x20000
	183	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	184	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
9acb626f HS	185
	186	/*
	187	* For booting Linux, the board info and command line data
	188	* have to be in the first 8 MB of memory, since this is
	189	* the maximum mapped by the Linux kernel during initialization ??
	190	*/
35cf3b57	191	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
9acb626f HS	192
	193	/*-----------------------------------------------------------------------
	194	* FLASH organization
	195	*/
35cf3b57 JS	196
	197	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	198	#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
	199	#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
	200
6d0f6bcf JCPV	201	#define CONFIG_SYS_MAX_FLASH_SECT 35
	202	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	203	#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
	204	#define CONFIG_SYS_FLASH_PROTECTION
9acb626f HS	205
	206	/*-----------------------------------------------------------------------
	207	* Cache Configuration
	208	*/
6d0f6bcf	209	#define CONFIG_SYS_CACHELINE_SIZE 16
9acb626f HS	210
	211	/*-----------------------------------------------------------------------
	212	* Memory bank definitions
	213	*/
	214
012522fe TL	215	#define CONFIG_SYS_CS0_BASE 0xFFE00000
	216	#define CONFIG_SYS_CS0_CTRL 0x00001980
	217	#define CONFIG_SYS_CS0_MASK 0x001F0001
9acb626f	218
6d0f6bcf	219	#define CONFIG_SYS_CS3_BASE 0xE0000000
012522fe TL	220	#define CONFIG_SYS_CS0_CTRL 0x00001980
012522fe TL	221	#define CONFIG_SYS_CS3_MASK 0x000F0001
9acb626f HS	222
	223	/*-----------------------------------------------------------------------
	224	* Port configuration
	225	*/
6d0f6bcf JCPV	226	#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
	227	#define CONFIG_SYS_PADDR 0x0000000
	228	#define CONFIG_SYS_PADAT 0x0000000
9acb626f	229
6d0f6bcf JCPV	230	#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
	231	#define CONFIG_SYS_PBDDR 0x0000000
	232	#define CONFIG_SYS_PBDAT 0x0000000
9acb626f	233
6d0f6bcf JCPV	234	#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
	235	#define CONFIG_SYS_PCDDR 0x0000000
	236	#define CONFIG_SYS_PCDAT 0x0000000
9acb626f	237
6d0f6bcf JCPV	238	#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
	239	#define CONFIG_SYS_PCDDR 0x0000000
	240	#define CONFIG_SYS_PCDAT 0x0000000
9acb626f	241
6d0f6bcf	242	#define CONFIG_SYS_PEHLPAR 0xC0
35cf3b57	243	#define CONFIG_SYS_PUAPAR 0x0F
6d0f6bcf JCPV	244	#define CONFIG_SYS_DDRUA 0x05
6d0f6bcf JCPV	245	#define CONFIG_SYS_PJPAR 0xFF
9acb626f HS	246
9acb626f HS	247	/*-----------------------------------------------------------------------
35cf3b57	248	* VIDEO configuration
9acb626f HS	249	*/
9acb626f HS	250
35cf3b57	251	#define CONFIG_VIDEO
9acb626f	252
35cf3b57 JS	253	#ifdef CONFIG_VIDEO
	254	#define CONFIG_VIDEO_VCXK 1
	255
	256	#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
	257	#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
	258	#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS3_BASE
	259	#define CONFIG_SYS_VCXK_AUTODETECT 1
	260
	261	#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
	262	#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
	263	#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
	264
	265	#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
	266	#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
	267	#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
	268
	269	#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
	270	#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
	271	#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
	272
	273	#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
	274	#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
	275	#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
	276
	277	#endif /* CONFIG_VIDEO */
9acb626f HS	278	#endif /* _CONFIG_M5282EVB_H */
9acb626f HS	279	/---------------------------------------------------------------------/