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3bac3513 WD |
1 | /* |
2 | **===================================================================== | |
3 | ** | |
4 | ** Copyright (C) 2000, 2001, 2002, 2003 | |
5 | ** The LEOX team <team@leox.org>, http://www.leox.org | |
6 | ** | |
7 | ** LEOX.org is about the development of free hardware and software resources | |
8 | ** for system on chip. | |
9 | ** | |
10 | ** Description: U-Boot port on the LEOX's ELPT860 CPU board | |
11 | ** ~~~~~~~~~~~ | |
12 | ** | |
13 | **===================================================================== | |
14 | ** | |
1a459660 | 15 | * SPDX-License-Identifier: GPL-2.0+ |
3bac3513 WD |
16 | ** |
17 | **===================================================================== | |
18 | */ | |
19 | ||
20 | /* | |
21 | * board/config.h - configuration options, board specific | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | ||
28 | /* | |
29 | * High Level Configuration Options | |
30 | * (easy to change) | |
31 | */ | |
32 | ||
33 | #define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */ | |
34 | #define CONFIG_MPC860T 1 | |
35 | #define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */ | |
36 | ||
2ae18241 WD |
37 | #define CONFIG_SYS_TEXT_BASE 0x02000000 |
38 | ||
c837dcb1 | 39 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
3bac3513 WD |
40 | #undef CONFIG_8xx_CONS_SMC2 |
41 | #undef CONFIG_8xx_CONS_NONE | |
42 | ||
c837dcb1 WD |
43 | #define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */ |
44 | #define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */ | |
3bac3513 WD |
45 | |
46 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
47 | ||
c837dcb1 | 48 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
004eca0c | 49 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ |
3bac3513 WD |
50 | |
51 | /* BOOT arguments */ | |
c837dcb1 WD |
52 | #define CONFIG_PREBOOT \ |
53 | "echo;" \ | |
54 | "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \ | |
3bac3513 WD |
55 | "echo" |
56 | ||
8bde7f77 | 57 | #undef CONFIG_BOOTARGS |
3bac3513 | 58 | |
c837dcb1 | 59 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
3bac3513 | 60 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b | 61 | "rootargs=setenv rootpath /tftp/${ipaddr}\0" \ |
3bac3513 | 62 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b WD |
63 | "nfsroot=${serverip}:${rootpath}\0" \ |
64 | "addip=setenv bootargs ${bootargs} " \ | |
65 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
66 | ":${hostname}:eth0:off panic=1\0" \ | |
3bac3513 | 67 | "ramboot=tftp 400000 /home/paugaml/pMulti;" \ |
8bde7f77 | 68 | "run ramargs;bootm\0" \ |
3bac3513 | 69 | "nfsboot=tftp 400000 /home/paugaml/uImage;" \ |
8bde7f77 | 70 | "run rootargs;run nfsargs;run addip;bootm\0" \ |
3bac3513 WD |
71 | "" |
72 | #define CONFIG_BOOTCOMMAND "run ramboot" | |
73 | ||
5d2ebe1b JL |
74 | /* |
75 | * BOOTP options | |
76 | */ | |
77 | #define CONFIG_BOOTP_SUBNETMASK | |
78 | #define CONFIG_BOOTP_GATEWAY | |
79 | #define CONFIG_BOOTP_HOSTNAME | |
80 | #define CONFIG_BOOTP_BOOTPATH | |
81 | #define CONFIG_BOOTP_BOOTFILESIZE | |
82 | ||
3bac3513 WD |
83 | |
84 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
85 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
86 | #undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */ | |
c837dcb1 | 87 | #define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */ |
3bac3513 WD |
88 | |
89 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 90 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
3bac3513 | 91 | |
3bac3513 | 92 | |
dcaa7156 JL |
93 | /* |
94 | * Command line configuration. | |
95 | */ | |
96 | #include <config_cmd_default.h> | |
97 | ||
98 | #define CONFIG_CMD_ASKENV | |
99 | #define CONFIG_CMD_DATE | |
100 | ||
3bac3513 WD |
101 | |
102 | /* | |
103 | * Miscellaneous configurable options | |
104 | */ | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
106 | #define CONFIG_SYS_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */ | |
3bac3513 | 107 | |
dcaa7156 | 108 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 109 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
3bac3513 | 110 | #else |
6d0f6bcf | 111 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
3bac3513 WD |
112 | #endif |
113 | ||
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
115 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
116 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
3bac3513 | 117 | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ |
119 | #define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ | |
3bac3513 | 120 | |
6d0f6bcf | 121 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
3bac3513 | 122 | |
6d0f6bcf | 123 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
3bac3513 WD |
124 | |
125 | /* | |
126 | * Environment Variables and Storages | |
127 | */ | |
c837dcb1 | 128 | #define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */ |
3bac3513 | 129 | |
9314cee6 | 130 | #undef CONFIG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */ |
bb1f8b4f | 131 | #undef CONFIG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */ |
5a1aceb0 | 132 | #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */ |
3bac3513 | 133 | |
c837dcb1 | 134 | #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */ |
3bac3513 | 135 | |
c837dcb1 WD |
136 | #define CONFIG_ETHADDR 00:01:77:00:60:40 |
137 | #define CONFIG_IPADDR 192.168.0.30 | |
138 | #define CONFIG_NETMASK 255.255.255.0 | |
3bac3513 | 139 | |
c837dcb1 WD |
140 | #define CONFIG_SERVERIP 192.168.0.1 |
141 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
3bac3513 WD |
142 | |
143 | /* | |
144 | * Low Level Configuration Settings | |
145 | * (address mappings, register initial values, etc.) | |
146 | * You should know what you are doing if you make changes here. | |
147 | */ | |
148 | ||
149 | /*----------------------------------------------------------------------- | |
150 | * Internal Memory Mapped Register | |
151 | */ | |
6d0f6bcf | 152 | #define CONFIG_SYS_IMMR 0xFF000000 |
3bac3513 WD |
153 | |
154 | /*----------------------------------------------------------------------- | |
155 | * Definitions for initial stack pointer and data area (in DPRAM) | |
156 | */ | |
6d0f6bcf | 157 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 158 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 159 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 160 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
3bac3513 WD |
161 | |
162 | /*----------------------------------------------------------------------- | |
163 | * Start addresses for the final memory configuration | |
164 | * (Set up by the startup code) | |
6d0f6bcf | 165 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
3bac3513 | 166 | */ |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
168 | #define CONFIG_SYS_FLASH_BASE 0x02000000 | |
169 | #define CONFIG_SYS_NVRAM_BASE 0x03000000 | |
3bac3513 | 170 | |
5a1aceb0 | 171 | #if defined(CONFIG_ENV_IS_IN_FLASH) |
3bac3513 | 172 | # if defined(DEBUG) |
6d0f6bcf | 173 | # define CONFIG_SYS_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */ |
3bac3513 | 174 | # else |
6d0f6bcf | 175 | # define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
3bac3513 WD |
176 | # endif |
177 | #else | |
178 | # if defined(DEBUG) | |
6d0f6bcf | 179 | # define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
3bac3513 | 180 | # else |
6d0f6bcf | 181 | # define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
3bac3513 WD |
182 | # endif |
183 | #endif | |
184 | ||
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
186 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
3bac3513 WD |
187 | |
188 | /* | |
189 | * For booting Linux, the board info and command line data | |
190 | * have to be in the first 8 MB of memory, since this is | |
191 | * the maximum mapped by the Linux kernel during initialization. | |
192 | */ | |
6d0f6bcf | 193 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
3bac3513 WD |
194 | |
195 | /*----------------------------------------------------------------------- | |
196 | * FLASH organization | |
197 | */ | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
199 | #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ | |
3bac3513 | 200 | |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
202 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
3bac3513 | 203 | |
5a1aceb0 | 204 | #if defined(CONFIG_ENV_IS_IN_FLASH) |
0e8d1586 JCPV |
205 | # define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ |
206 | # define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ | |
3bac3513 WD |
207 | #endif |
208 | ||
209 | /*----------------------------------------------------------------------- | |
210 | * NVRAM organization | |
211 | */ | |
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */ |
213 | #define CONFIG_SYS_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */ | |
8bde7f77 | 214 | /* 8 top NVRAM locations */ |
3bac3513 | 215 | |
9314cee6 | 216 | #if defined(CONFIG_ENV_IS_IN_NVRAM) |
6d0f6bcf | 217 | # define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */ |
0e8d1586 | 218 | # define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
3bac3513 WD |
219 | #endif |
220 | ||
221 | /*----------------------------------------------------------------------- | |
222 | * Cache Configuration | |
223 | */ | |
6d0f6bcf | 224 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
3bac3513 | 225 | |
dcaa7156 | 226 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 227 | # define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
3bac3513 WD |
228 | #endif |
229 | ||
230 | /*----------------------------------------------------------------------- | |
231 | * SYPCR - System Protection Control 11-9 | |
232 | * SYPCR can only be written once after reset! | |
233 | *----------------------------------------------------------------------- | |
234 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
235 | */ | |
236 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 237 | # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
8bde7f77 | 238 | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) |
3bac3513 | 239 | #else |
6d0f6bcf | 240 | # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
8bde7f77 | 241 | SYPCR_SWP) |
3bac3513 WD |
242 | #endif |
243 | ||
244 | /*----------------------------------------------------------------------- | |
245 | * SUMCR - SIU Module Configuration 11-6 | |
246 | *----------------------------------------------------------------------- | |
247 | * PCMCIA config., multi-function pin tri-state | |
248 | */ | |
6d0f6bcf | 249 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11) |
3bac3513 WD |
250 | |
251 | /*----------------------------------------------------------------------- | |
252 | * TBSCR - Time Base Status and Control 11-26 | |
253 | *----------------------------------------------------------------------- | |
254 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
255 | */ | |
6d0f6bcf | 256 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
3bac3513 WD |
257 | |
258 | /*----------------------------------------------------------------------- | |
259 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
260 | *----------------------------------------------------------------------- | |
261 | * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC | |
262 | * enabled | |
263 | */ | |
6d0f6bcf | 264 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
3bac3513 WD |
265 | |
266 | /*----------------------------------------------------------------------- | |
267 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
268 | *----------------------------------------------------------------------- | |
269 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
270 | */ | |
6d0f6bcf | 271 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
3bac3513 WD |
272 | |
273 | /*----------------------------------------------------------------------- | |
274 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
275 | *----------------------------------------------------------------------- | |
276 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
277 | * interrupt status bit - leave PLL multiplication factor unchanged ! | |
278 | */ | |
6d0f6bcf | 279 | #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
3bac3513 WD |
280 | |
281 | /*----------------------------------------------------------------------- | |
282 | * SCCR - System Clock and reset Control Register 15-27 | |
283 | *----------------------------------------------------------------------- | |
284 | * Set clock output, timebase and RTC source and divider, | |
285 | * power management and some other internal clocks | |
286 | */ | |
287 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 288 | #define CONFIG_SYS_SCCR (SCCR_TBS | \ |
3bac3513 WD |
289 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
290 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
291 | SCCR_DFALCD00) | |
292 | ||
293 | /*----------------------------------------------------------------------- | |
294 | * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler | |
295 | *----------------------------------------------------------------------- | |
296 | * | |
297 | */ | |
298 | #ifdef DEBUG | |
6d0f6bcf | 299 | # define CONFIG_SYS_DER 0xFFE7400F /* Debug Enable Register */ |
3bac3513 | 300 | #else |
6d0f6bcf | 301 | # define CONFIG_SYS_DER 0 |
3bac3513 WD |
302 | #endif |
303 | ||
304 | /* | |
305 | * Init Memory Controller: | |
306 | * ~~~~~~~~~~~~~~~~~~~~~~ | |
307 | * | |
308 | * BR0 and OR0 (FLASH) | |
309 | */ | |
310 | ||
6d0f6bcf | 311 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ |
3bac3513 WD |
312 | |
313 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
314 | * restrict access enough to keep SRAM working (if any) | |
315 | * but not too much to meddle with FLASH accesses | |
316 | */ | |
6d0f6bcf | 317 | #define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */ |
3bac3513 WD |
318 | |
319 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */ | |
6d0f6bcf | 320 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK) |
3bac3513 | 321 | |
6d0f6bcf JCPV |
322 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
323 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
3bac3513 WD |
324 | |
325 | /* | |
326 | * BR1 and OR1 (SDRAM) | |
327 | * | |
328 | */ | |
6d0f6bcf | 329 | #define SDRAM_BASE1_PRELIM CONFIG_SYS_SDRAM_BASE /* SDRAM bank #0 */ |
c837dcb1 | 330 | #define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */ |
3bac3513 | 331 | |
c837dcb1 | 332 | /* SDRAM timing: */ |
6d0f6bcf | 333 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000000 |
3bac3513 | 334 | |
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_OR1_PRELIM ((2 * CONFIG_SYS_PRELIM_OR_AM) | CONFIG_SYS_OR_TIMING_SDRAM ) |
336 | #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
3bac3513 WD |
337 | |
338 | /* | |
339 | * BR2 and OR2 (NVRAM) | |
340 | * | |
341 | */ | |
6d0f6bcf | 342 | #define NVRAM_BASE1_PRELIM CONFIG_SYS_NVRAM_BASE /* NVRAM bank #0 */ |
c837dcb1 | 343 | #define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */ |
3bac3513 | 344 | |
6d0f6bcf JCPV |
345 | #define CONFIG_SYS_OR2_PRELIM 0xFFF80160 |
346 | #define CONFIG_SYS_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
3bac3513 WD |
347 | |
348 | /* | |
349 | * Memory Periodic Timer Prescaler | |
350 | */ | |
351 | ||
352 | /* periodic timer for refresh */ | |
6d0f6bcf | 353 | #define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ |
3bac3513 WD |
354 | |
355 | /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ | |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
357 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
3bac3513 | 358 | |
c837dcb1 | 359 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
6d0f6bcf JCPV |
360 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
361 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
3bac3513 WD |
362 | |
363 | /* | |
364 | * MAMR settings for SDRAM | |
365 | */ | |
366 | ||
367 | /* 8 column SDRAM */ | |
6d0f6bcf | 368 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
3bac3513 WD |
369 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
370 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
371 | /* 9 column SDRAM */ | |
6d0f6bcf | 372 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
3bac3513 WD |
373 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
374 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
375 | ||
3bac3513 | 376 | #endif /* __CONFIG_H */ |