[people/ms/u-boot.git] / include / configs / ELPT860.h

/*
**=====================================================================
**
** Copyright (C) 2000, 2001, 2002, 2003
** The LEOX team <team@leox.org>, http://www.leox.org
**
** LEOX.org is about the development of free hardware and software resources
**   for system on chip.
**
** Description: U-Boot port on the LEOX's ELPT860 CPU board
** ~~~~~~~~~~~
**
**=====================================================================
**
** This program is free software; you can redistribute it and/or
** modify it under the terms of the GNU General Public License as
** published by the Free Software Foundation; either version 2 of
** the License, or (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program; if not, write to the Free Software
** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
** MA 02111-1307 USA
**
**=====================================================================
*/

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H


/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* It's a MPC860, in fact a 860T CPU */
#define CONFIG_MPC860T		1
#define CONFIG_ELPT860		1	/* ...on a LEOX's ELPT860 CPU board */

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		    */
#undef	  CONFIG_8xx_CONS_SMC2
#undef	  CONFIG_8xx_CONS_NONE

#define CONFIG_CLOCKS_IN_MHZ	1  /* Clock passed to Linux (<2.4.5) in MHz */
#define CONFIG_8xx_GCLK_FREQ	50000000       /* MPC860T runs at 50MHz */

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/

/* BOOT arguments */
#define CONFIG_PREBOOT							   \
     "echo;"								   \
     "echo Type \"run nfsboot\" to mount root filesystem over NFS;"	   \
     "echo"

#undef	  CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
    "ramargs=setenv bootargs root=/dev/ram rw\0"			\
    "rootargs=setenv rootpath /tftp/${ipaddr}\0"			\
    "nfsargs=setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=${serverip}:${rootpath}\0"				\
    "addip=setenv bootargs ${bootargs} "				\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"		\
	":${hostname}:eth0:off panic=1\0"				\
    "ramboot=tftp 400000 /home/paugaml/pMulti;"				\
	"run ramargs;bootm\0"						\
    "nfsboot=tftp 400000 /home/paugaml/uImage;"				\
	"run rootargs;run nfsargs;run addip;bootm\0"			\
    ""
#define CONFIG_BOOTCOMMAND	"run ramboot"

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#undef	  CONFIG_WATCHDOG		/* watchdog disabled		*/
#undef	  CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
#undef	  CONFIG_RTC_MPC8xx		/* internal RTC MPC8xx unused	*/
#define CONFIG_RTC_DS164x	1	/* RTC is a Dallas DS1646	*/

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	  CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT     "LEOX_elpt860: " /* Monitor Command Prompt	*/

#if defined(CONFIG_CMD_KGDB)
#  define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#  define CFG_CBSIZE	 256		/* Console I/O Buffer Size	*/
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	  16		/* max number of command args	*/
#define CFG_BARGSIZE	  CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x00100000	/* default load address */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

/*
 * Environment Variables and Storages
 */
#define CONFIG_ENV_OVERWRITE	1  /* Allow Overwrite of serial# & ethaddr */

#undef	  CONFIG_ENV_IS_IN_NVRAM	       /* Environment is in NVRAM	*/
#undef	  CONFIG_ENV_IS_IN_EEPROM	       /* Environment is in I2C EEPROM	*/
#define CONFIG_ENV_IS_IN_FLASH	1      /* Environment is in FLASH	*/

#define CONFIG_BAUDRATE		9600   /* console baudrate = 9600 bps	*/
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_ETHADDR		00:01:77:00:60:40
#define CONFIG_IPADDR		192.168.0.30
#define CONFIG_NETMASK		255.255.255.0

#define CONFIG_SERVERIP		192.168.0.1
#define CONFIG_GATEWAYIP	192.168.0.1

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x02000000
#define CFG_NVRAM_BASE		0x03000000

#if defined(CONFIG_ENV_IS_IN_FLASH)
#  if defined(DEBUG)
#    define CFG_MONITOR_LEN	(320 << 10)  /* Reserve 320 kB for Monitor  */
#  else
#    define CFG_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
#  endif
#else
#  if defined(DEBUG)
#    define CFG_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
#  else
#    define CFG_MONITOR_LEN	(192 << 10)  /* Reserve 192 kB for Monitor  */
#  endif
#endif

#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MALLOC_LEN		(128 << 10)  /* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)    /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	     */
#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip */

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)   */
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)   */

#if defined(CONFIG_ENV_IS_IN_FLASH)
#  define CONFIG_ENV_OFFSET	0x10000 /* Offset   of Environment Sector    */
#  define CONFIG_ENV_SIZE		0x10000 /* Total Size of Environment Sector  */
#endif

/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CFG_NVRAM_BASE_ADDR	CFG_NVRAM_BASE /* Base address of NVRAM area */
#define CFG_NVRAM_SIZE		((128*1024)-8) /* clock regs resident in the */
					       /*   8 top NVRAM locations    */

#if defined(CONFIG_ENV_IS_IN_NVRAM)
#  define CONFIG_ENV_ADDR		CFG_NVRAM_BASE /* Base address of NVRAM area */
#  define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector  */
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		     */

#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	 4	/* log base 2 of the above value     */
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI | SYPCR_SWP)
#else
#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
						   SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_DBGC11)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
 *  enabled
 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	 SCCR_EBDF11
#define CFG_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
 *-----------------------------------------------------------------------
 *
 */
#ifdef DEBUG
#  define CFG_DER		0xFFE7400F	/* Debug Enable Register */
#else
#  define CFG_DER		0
#endif

/*
 * Init Memory Controller:
 * ~~~~~~~~~~~~~~~~~~~~~~
 *
 * BR0 and OR0 (FLASH)
 */

#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	  */

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_PRELIM_OR_AM	0xFF000000	/* 16 MB between each CSx */

/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0	  */
#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)

#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * BR1 and OR1 (SDRAM)
 *
 */
#define SDRAM_BASE1_PRELIM	CFG_SDRAM_BASE	/* SDRAM bank #0	*/
#define SDRAM_MAX_SIZE		0x02000000	/* 32 MB MAX for CS1	*/

/* SDRAM timing:							*/
#define CFG_OR_TIMING_SDRAM	0x00000000

#define CFG_OR1_PRELIM	((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM )
#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * BR2 and OR2 (NVRAM)
 *
 */
#define NVRAM_BASE1_PRELIM	CFG_NVRAM_BASE	/* NVRAM bank #0	*/
#define NVRAM_MAX_SIZE		0x00020000	/* 128 KB MAX for CS2	*/

#define CFG_OR2_PRELIM		0xFFF80160
#define CFG_BR2_PRELIM	((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CFG_MAMR_PTA		97     /* start with divider for 100 MHz */

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16	  /* setting for 2 banks */
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32	  /* setting for 1 bank	 */

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit	 */
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8	  /* setting for 2 banks */
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16	  /* setting for 1 bank	 */

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/*-----------------------------------------------------------------------
 * Internal Definitions
 *-----------------------------------------------------------------------
 *
 */

/*
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		 /* Software reboot		     */


#endif	/* __CONFIG_H */
Commit	Line	Data
3bac3513 WD	1	/*
	2	**=====================================================================
	3	**
	4	** Copyright (C) 2000, 2001, 2002, 2003
	5	** The LEOX team <team@leox.org>, http://www.leox.org
	6	**
	7	** LEOX.org is about the development of free hardware and software resources
	8	** for system on chip.
	9	**
	10	** Description: U-Boot port on the LEOX's ELPT860 CPU board
	11	** ~~~~~~~~~~~
	12	**
	13	**=====================================================================
	14	**
	15	** This program is free software; you can redistribute it and/or
	16	** modify it under the terms of the GNU General Public License as
	17	** published by the Free Software Foundation; either version 2 of
	18	** the License, or (at your option) any later version.
	19	**
	20	** This program is distributed in the hope that it will be useful,
	21	** but WITHOUT ANY WARRANTY; without even the implied warranty of
c837dcb1	22	** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3bac3513 WD	23	** GNU General Public License for more details.
	24	**
	25	** You should have received a copy of the GNU General Public License
	26	** along with this program; if not, write to the Free Software
	27	** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	** MA 02111-1307 USA
	29	**
	30	**=====================================================================
	31	*/
	32
	33	/*
	34	* board/config.h - configuration options, board specific
	35	*/
	36
	37	#ifndef __CONFIG_H
	38	#define __CONFIG_H
	39
	40
	41	/*
	42	* High Level Configuration Options
	43	* (easy to change)
	44	*/
	45
	46	#define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */
	47	#define CONFIG_MPC860T 1
	48	#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */
	49
c837dcb1	50	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
3bac3513 WD	51	#undef CONFIG_8xx_CONS_SMC2
	52	#undef CONFIG_8xx_CONS_NONE
	53
c837dcb1 WD	54	#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */
c837dcb1 WD	55	#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */
3bac3513 WD	56
	57	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	58
c837dcb1	59	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
3bac3513 WD	60
3bac3513 WD	61	/* BOOT arguments */
c837dcb1 WD	62	#define CONFIG_PREBOOT \
	63	"echo;" \
	64	"echo Type \"run nfsboot\" to mount root filesystem over NFS;" \
3bac3513 WD	65	"echo"
3bac3513 WD	66
8bde7f77	67	#undef CONFIG_BOOTARGS
3bac3513	68
c837dcb1	69	#define CONFIG_EXTRA_ENV_SETTINGS \
3bac3513	70	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b	71	"rootargs=setenv rootpath /tftp/${ipaddr}\0" \
3bac3513	72	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b WD	73	"nfsroot=${serverip}:${rootpath}\0" \
	74	"addip=setenv bootargs ${bootargs} " \
	75	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	76	":${hostname}:eth0:off panic=1\0" \
3bac3513	77	"ramboot=tftp 400000 /home/paugaml/pMulti;" \
8bde7f77	78	"run ramargs;bootm\0" \
3bac3513	79	"nfsboot=tftp 400000 /home/paugaml/uImage;" \
8bde7f77	80	"run rootargs;run nfsargs;run addip;bootm\0" \
3bac3513 WD	81	""
	82	#define CONFIG_BOOTCOMMAND "run ramboot"
	83
5d2ebe1b JL	84	/*
	85	* BOOTP options
	86	*/
	87	#define CONFIG_BOOTP_SUBNETMASK
	88	#define CONFIG_BOOTP_GATEWAY
	89	#define CONFIG_BOOTP_HOSTNAME
	90	#define CONFIG_BOOTP_BOOTPATH
	91	#define CONFIG_BOOTP_BOOTFILESIZE
	92
3bac3513 WD	93
	94	#undef CONFIG_WATCHDOG /* watchdog disabled */
	95	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	96	#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */
c837dcb1	97	#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */
3bac3513 WD	98
	99	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	100	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	101
3bac3513	102
dcaa7156 JL	103	/*
	104	* Command line configuration.
	105	*/
	106	#include <config_cmd_default.h>
	107
	108	#define CONFIG_CMD_ASKENV
	109	#define CONFIG_CMD_DATE
	110
3bac3513 WD	111
	112	/*
	113	* Miscellaneous configurable options
	114	*/
c837dcb1 WD	115	#define CFG_LONGHELP /* undef to save memory */
c837dcb1 WD	116	#define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */
3bac3513	117
dcaa7156	118	#if defined(CONFIG_CMD_KGDB)
3bac3513 WD	119	# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	120	#else
	121	# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	122	#endif
	123
c837dcb1 WD	124	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
c837dcb1 WD	125	#define CFG_MAXARGS 16 /* max number of command args */
3bac3513 WD	126	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	127
	128	#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
	129	#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
	130
c837dcb1	131	#define CFG_LOAD_ADDR 0x00100000 /* default load address */
3bac3513	132
c837dcb1	133	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
3bac3513 WD	134
	135	/*
	136	* Environment Variables and Storages
	137	*/
c837dcb1	138	#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */
3bac3513	139
9314cee6	140	#undef CONFIG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
bb1f8b4f	141	#undef CONFIG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */
5a1aceb0	142	#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */
3bac3513	143
c837dcb1	144	#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */
3bac3513 WD	145	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
3bac3513 WD	146
c837dcb1 WD	147	#define CONFIG_ETHADDR 00:01:77:00:60:40
	148	#define CONFIG_IPADDR 192.168.0.30
	149	#define CONFIG_NETMASK 255.255.255.0
3bac3513	150
c837dcb1 WD	151	#define CONFIG_SERVERIP 192.168.0.1
c837dcb1 WD	152	#define CONFIG_GATEWAYIP 192.168.0.1
3bac3513 WD	153
	154	/*
	155	* Low Level Configuration Settings
	156	* (address mappings, register initial values, etc.)
	157	* You should know what you are doing if you make changes here.
	158	*/
	159
	160	/*-----------------------------------------------------------------------
	161	* Internal Memory Mapped Register
	162	*/
	163	#define CFG_IMMR 0xFF000000
	164
	165	/*-----------------------------------------------------------------------
	166	* Definitions for initial stack pointer and data area (in DPRAM)
	167	*/
	168	#define CFG_INIT_RAM_ADDR CFG_IMMR
c837dcb1 WD	169	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
c837dcb1 WD	170	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
3bac3513	171	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c837dcb1	172	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
3bac3513 WD	173
	174	/*-----------------------------------------------------------------------
	175	* Start addresses for the final memory configuration
	176	* (Set up by the startup code)
	177	* Please note that CFG_SDRAM_BASE _must_ start at 0
	178	*/
c837dcb1	179	#define CFG_SDRAM_BASE 0x00000000
3bac3513	180	#define CFG_FLASH_BASE 0x02000000
c837dcb1	181	#define CFG_NVRAM_BASE 0x03000000
3bac3513	182
5a1aceb0	183	#if defined(CONFIG_ENV_IS_IN_FLASH)
3bac3513 WD	184	# if defined(DEBUG)
	185	# define CFG_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */
	186	# else
	187	# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	188	# endif
	189	#else
	190	# if defined(DEBUG)
	191	# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	192	# else
	193	# define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	194	# endif
	195	#endif
	196
	197	#define CFG_MONITOR_BASE CFG_FLASH_BASE
c837dcb1	198	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
3bac3513 WD	199
	200	/*
	201	* For booting Linux, the board info and command line data
	202	* have to be in the first 8 MB of memory, since this is
	203	* the maximum mapped by the Linux kernel during initialization.
	204	*/
c837dcb1	205	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
3bac3513 WD	206
	207	/*-----------------------------------------------------------------------
	208	* FLASH organization
	209	*/
c837dcb1	210	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
3bac3513 WD	211	#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
	212
	213	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	214	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	215
5a1aceb0	216	#if defined(CONFIG_ENV_IS_IN_FLASH)
0e8d1586 JCPV	217	# define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
0e8d1586 JCPV	218	# define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
3bac3513 WD	219	#endif
	220
	221	/*-----------------------------------------------------------------------
	222	* NVRAM organization
	223	*/
c837dcb1 WD	224	#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */
c837dcb1 WD	225	#define CFG_NVRAM_SIZE ((1281024)-8) / clock regs resident in the */
8bde7f77	226	/* 8 top NVRAM locations */
3bac3513	227
9314cee6	228	#if defined(CONFIG_ENV_IS_IN_NVRAM)
0e8d1586 JCPV	229	# define CONFIG_ENV_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */
0e8d1586 JCPV	230	# define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
3bac3513 WD	231	#endif
	232
	233	/*-----------------------------------------------------------------------
	234	* Cache Configuration
	235	*/
c837dcb1	236	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
3bac3513	237
dcaa7156	238	#if defined(CONFIG_CMD_KGDB)
c837dcb1	239	# define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
3bac3513 WD	240	#endif
	241
	242	/*-----------------------------------------------------------------------
	243	* SYPCR - System Protection Control 11-9
	244	* SYPCR can only be written once after reset!
	245	*-----------------------------------------------------------------------
	246	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	247	*/
	248	#if defined(CONFIG_WATCHDOG)
c837dcb1	249	# define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
8bde7f77	250	SYPCR_SWE \| SYPCR_SWRI \| SYPCR_SWP)
3bac3513	251	#else
c837dcb1	252	# define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
8bde7f77	253	SYPCR_SWP)
3bac3513 WD	254	#endif
	255
	256	/*-----------------------------------------------------------------------
	257	* SUMCR - SIU Module Configuration 11-6
	258	*-----------------------------------------------------------------------
	259	* PCMCIA config., multi-function pin tri-state
	260	*/
	261	#define CFG_SIUMCR (SIUMCR_DBGC11)
	262
	263	/*-----------------------------------------------------------------------
	264	* TBSCR - Time Base Status and Control 11-26
	265	*-----------------------------------------------------------------------
	266	* Clear Reference Interrupt Status, Timebase freezing enabled
	267	*/
	268	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	269
	270	/*-----------------------------------------------------------------------
	271	* RTCSC - Real-Time Clock Status and Control Register 11-27
	272	*-----------------------------------------------------------------------
	273	* Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
	274	* enabled
	275	*/
	276	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
	277
	278	/*-----------------------------------------------------------------------
	279	* PISCR - Periodic Interrupt Status and Control 11-31
	280	*-----------------------------------------------------------------------
	281	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	282	*/
	283	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	284
	285	/*-----------------------------------------------------------------------
	286	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	287	*-----------------------------------------------------------------------
	288	* Reset PLL lock status sticky bit, timer expired status bit and timer
	289	* interrupt status bit - leave PLL multiplication factor unchanged !
	290	*/
	291	#define CFG_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
	292
	293	/*-----------------------------------------------------------------------
	294	* SCCR - System Clock and reset Control Register 15-27
	295	*-----------------------------------------------------------------------
	296	* Set clock output, timebase and RTC source and divider,
	297	* power management and some other internal clocks
	298	*/
	299	#define SCCR_MASK SCCR_EBDF11
	300	#define CFG_SCCR (SCCR_TBS \| \
	301	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	302	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	303	SCCR_DFALCD00)
	304
	305	/*-----------------------------------------------------------------------
	306	* Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
	307	*-----------------------------------------------------------------------
	308	*
	309	*/
	310	#ifdef DEBUG
	311	# define CFG_DER 0xFFE7400F /* Debug Enable Register */
	312	#else
	313	# define CFG_DER 0
	314	#endif
	315
	316	/*
	317	* Init Memory Controller:
318	* ~~~~~~~~~~~~~~~~~~~~~~
319	*
320	* BR0 and OR0 (FLASH)
321	*/
322
c837dcb1	323	#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
3bac3513 WD	324
	325	/* used to re-map FLASH both when starting from SRAM or FLASH:
	326	* restrict access enough to keep SRAM working (if any)
	327	* but not too much to meddle with FLASH accesses
	328	*/
	329	#define CFG_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */
	330
	331	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */
	332	#define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 \| OR_BI \| OR_SCY_8_CLK)
	333
	334	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
	335	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_8 \| BR_V )
	336
	337	/*
	338	* BR1 and OR1 (SDRAM)
	339	*
	340	*/
c837dcb1 WD	341	#define SDRAM_BASE1_PRELIM CFG_SDRAM_BASE /* SDRAM bank #0 */
c837dcb1 WD	342	#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */
3bac3513	343
c837dcb1	344	/* SDRAM timing: */
3bac3513 WD	345	#define CFG_OR_TIMING_SDRAM 0x00000000
	346
	347	#define CFG_OR1_PRELIM ((2 * CFG_PRELIM_OR_AM) \| CFG_OR_TIMING_SDRAM )
	348	#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
	349
	350	/*
	351	* BR2 and OR2 (NVRAM)
	352	*
	353	*/
c837dcb1 WD	354	#define NVRAM_BASE1_PRELIM CFG_NVRAM_BASE /* NVRAM bank #0 */
c837dcb1 WD	355	#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */
3bac3513	356
c837dcb1	357	#define CFG_OR2_PRELIM 0xFFF80160
3bac3513 WD	358	#define CFG_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) \| BR_PS_8 \| BR_V )
	359
	360	/*
	361	* Memory Periodic Timer Prescaler
	362	*/
	363
	364	/* periodic timer for refresh */
c837dcb1	365	#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
3bac3513 WD	366
	367	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
	368	#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
c837dcb1	369	#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
3bac3513	370
c837dcb1 WD	371	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
	372	#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
	373	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
3bac3513 WD	374
	375	/*
	376	* MAMR settings for SDRAM
	377	*/
	378
	379	/* 8 column SDRAM */
	380	#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	381	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	382	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	383	/* 9 column SDRAM */
	384	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	385	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	386	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	387
	388	/*-----------------------------------------------------------------------
	389	* Internal Definitions
	390	*-----------------------------------------------------------------------
	391	*
	392	*/
	393
	394	/*
	395	* Boot Flags
	396	*/
c837dcb1 WD	397	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
c837dcb1 WD	398	#define BOOTFLAG_WARM 0x02 /* Software reboot */
3bac3513 WD	399
	400
	401	#endif /* __CONFIG_H */