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3bac3513 WD |
1 | /* |
2 | **===================================================================== | |
3 | ** | |
4 | ** Copyright (C) 2000, 2001, 2002, 2003 | |
5 | ** The LEOX team <team@leox.org>, http://www.leox.org | |
6 | ** | |
7 | ** LEOX.org is about the development of free hardware and software resources | |
8 | ** for system on chip. | |
9 | ** | |
10 | ** Description: U-Boot port on the LEOX's ELPT860 CPU board | |
11 | ** ~~~~~~~~~~~ | |
12 | ** | |
13 | **===================================================================== | |
14 | ** | |
15 | ** This program is free software; you can redistribute it and/or | |
16 | ** modify it under the terms of the GNU General Public License as | |
17 | ** published by the Free Software Foundation; either version 2 of | |
18 | ** the License, or (at your option) any later version. | |
19 | ** | |
20 | ** This program is distributed in the hope that it will be useful, | |
21 | ** but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c837dcb1 | 22 | ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
3bac3513 WD |
23 | ** GNU General Public License for more details. |
24 | ** | |
25 | ** You should have received a copy of the GNU General Public License | |
26 | ** along with this program; if not, write to the Free Software | |
27 | ** Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | ** MA 02111-1307 USA | |
29 | ** | |
30 | **===================================================================== | |
31 | */ | |
32 | ||
33 | /* | |
34 | * board/config.h - configuration options, board specific | |
35 | */ | |
36 | ||
37 | #ifndef __CONFIG_H | |
38 | #define __CONFIG_H | |
39 | ||
40 | ||
41 | /* | |
42 | * High Level Configuration Options | |
43 | * (easy to change) | |
44 | */ | |
45 | ||
46 | #define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */ | |
47 | #define CONFIG_MPC860T 1 | |
48 | #define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */ | |
49 | ||
c837dcb1 | 50 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
3bac3513 WD |
51 | #undef CONFIG_8xx_CONS_SMC2 |
52 | #undef CONFIG_8xx_CONS_NONE | |
53 | ||
c837dcb1 WD |
54 | #define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */ |
55 | #define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */ | |
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56 | |
57 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
58 | ||
c837dcb1 | 59 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
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60 | |
61 | /* BOOT arguments */ | |
c837dcb1 WD |
62 | #define CONFIG_PREBOOT \ |
63 | "echo;" \ | |
64 | "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \ | |
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65 | "echo" |
66 | ||
8bde7f77 | 67 | #undef CONFIG_BOOTARGS |
3bac3513 | 68 | |
c837dcb1 | 69 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
3bac3513 WD |
70 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
71 | "rootargs=setenv rootpath /tftp/$(ipaddr)\0" \ | |
72 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
8bde7f77 | 73 | "nfsroot=$(serverip):$(rootpath)\0" \ |
3bac3513 | 74 | "addip=setenv bootargs $(bootargs) " \ |
8bde7f77 WD |
75 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ |
76 | ":$(hostname):eth0:off panic=1\0" \ | |
3bac3513 | 77 | "ramboot=tftp 400000 /home/paugaml/pMulti;" \ |
8bde7f77 | 78 | "run ramargs;bootm\0" \ |
3bac3513 | 79 | "nfsboot=tftp 400000 /home/paugaml/uImage;" \ |
8bde7f77 | 80 | "run rootargs;run nfsargs;run addip;bootm\0" \ |
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81 | "" |
82 | #define CONFIG_BOOTCOMMAND "run ramboot" | |
83 | ||
84 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) | |
85 | ||
86 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
87 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
88 | #undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */ | |
c837dcb1 | 89 | #define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */ |
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90 | |
91 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
92 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
93 | ||
c837dcb1 | 94 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
8bde7f77 | 95 | CFG_CMD_ASKENV | \ |
c837dcb1 | 96 | CFG_CMD_DATE ) |
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97 | |
98 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
99 | #include <cmd_confdefs.h> | |
100 | ||
101 | /* | |
102 | * Miscellaneous configurable options | |
103 | */ | |
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104 | #define CFG_LONGHELP /* undef to save memory */ |
105 | #define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */ | |
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106 | |
107 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
108 | # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
109 | #else | |
110 | # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
111 | #endif | |
112 | ||
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113 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
114 | #define CFG_MAXARGS 16 /* max number of command args */ | |
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115 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
116 | ||
117 | #define CFG_MEMTEST_START 0x00400000 /* memtest works on */ | |
118 | #define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ | |
119 | ||
c837dcb1 | 120 | #define CFG_LOAD_ADDR 0x00100000 /* default load address */ |
3bac3513 | 121 | |
c837dcb1 | 122 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
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123 | |
124 | /* | |
125 | * Environment Variables and Storages | |
126 | */ | |
c837dcb1 | 127 | #define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */ |
3bac3513 | 128 | |
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129 | #undef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */ |
130 | #undef CFG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */ | |
131 | #define CFG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */ | |
3bac3513 | 132 | |
c837dcb1 | 133 | #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */ |
3bac3513 WD |
134 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
135 | ||
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136 | #define CONFIG_ETHADDR 00:01:77:00:60:40 |
137 | #define CONFIG_IPADDR 192.168.0.30 | |
138 | #define CONFIG_NETMASK 255.255.255.0 | |
3bac3513 | 139 | |
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140 | #define CONFIG_SERVERIP 192.168.0.1 |
141 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
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142 | |
143 | /* | |
144 | * Low Level Configuration Settings | |
145 | * (address mappings, register initial values, etc.) | |
146 | * You should know what you are doing if you make changes here. | |
147 | */ | |
148 | ||
149 | /*----------------------------------------------------------------------- | |
150 | * Internal Memory Mapped Register | |
151 | */ | |
152 | #define CFG_IMMR 0xFF000000 | |
153 | ||
154 | /*----------------------------------------------------------------------- | |
155 | * Definitions for initial stack pointer and data area (in DPRAM) | |
156 | */ | |
157 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
c837dcb1 WD |
158 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
159 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
3bac3513 | 160 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
c837dcb1 | 161 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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162 | |
163 | /*----------------------------------------------------------------------- | |
164 | * Start addresses for the final memory configuration | |
165 | * (Set up by the startup code) | |
166 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
167 | */ | |
c837dcb1 | 168 | #define CFG_SDRAM_BASE 0x00000000 |
3bac3513 | 169 | #define CFG_FLASH_BASE 0x02000000 |
c837dcb1 | 170 | #define CFG_NVRAM_BASE 0x03000000 |
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171 | |
172 | #if defined(CFG_ENV_IS_IN_FLASH) | |
173 | # if defined(DEBUG) | |
174 | # define CFG_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */ | |
175 | # else | |
176 | # define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
177 | # endif | |
178 | #else | |
179 | # if defined(DEBUG) | |
180 | # define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
181 | # else | |
182 | # define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ | |
183 | # endif | |
184 | #endif | |
185 | ||
186 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
c837dcb1 | 187 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
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188 | |
189 | /* | |
190 | * For booting Linux, the board info and command line data | |
191 | * have to be in the first 8 MB of memory, since this is | |
192 | * the maximum mapped by the Linux kernel during initialization. | |
193 | */ | |
c837dcb1 | 194 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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195 | |
196 | /*----------------------------------------------------------------------- | |
197 | * FLASH organization | |
198 | */ | |
c837dcb1 | 199 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
3bac3513 WD |
200 | #define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
201 | ||
202 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
203 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
204 | ||
205 | #if defined(CFG_ENV_IS_IN_FLASH) | |
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206 | # define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ |
207 | # define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ | |
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208 | #endif |
209 | ||
210 | /*----------------------------------------------------------------------- | |
211 | * NVRAM organization | |
212 | */ | |
c837dcb1 WD |
213 | #define CFG_NVRAM_BASE_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */ |
214 | #define CFG_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */ | |
8bde7f77 | 215 | /* 8 top NVRAM locations */ |
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216 | |
217 | #if defined(CFG_ENV_IS_IN_NVRAM) | |
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218 | # define CFG_ENV_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */ |
219 | # define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
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220 | #endif |
221 | ||
222 | /*----------------------------------------------------------------------- | |
223 | * Cache Configuration | |
224 | */ | |
c837dcb1 | 225 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
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226 | |
227 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
c837dcb1 | 228 | # define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
3bac3513 WD |
229 | #endif |
230 | ||
231 | /*----------------------------------------------------------------------- | |
232 | * SYPCR - System Protection Control 11-9 | |
233 | * SYPCR can only be written once after reset! | |
234 | *----------------------------------------------------------------------- | |
235 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
236 | */ | |
237 | #if defined(CONFIG_WATCHDOG) | |
c837dcb1 | 238 | # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
8bde7f77 | 239 | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) |
3bac3513 | 240 | #else |
c837dcb1 | 241 | # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
8bde7f77 | 242 | SYPCR_SWP) |
3bac3513 WD |
243 | #endif |
244 | ||
245 | /*----------------------------------------------------------------------- | |
246 | * SUMCR - SIU Module Configuration 11-6 | |
247 | *----------------------------------------------------------------------- | |
248 | * PCMCIA config., multi-function pin tri-state | |
249 | */ | |
250 | #define CFG_SIUMCR (SIUMCR_DBGC11) | |
251 | ||
252 | /*----------------------------------------------------------------------- | |
253 | * TBSCR - Time Base Status and Control 11-26 | |
254 | *----------------------------------------------------------------------- | |
255 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
256 | */ | |
257 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
258 | ||
259 | /*----------------------------------------------------------------------- | |
260 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
261 | *----------------------------------------------------------------------- | |
262 | * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC | |
263 | * enabled | |
264 | */ | |
265 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
266 | ||
267 | /*----------------------------------------------------------------------- | |
268 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
269 | *----------------------------------------------------------------------- | |
270 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
271 | */ | |
272 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
273 | ||
274 | /*----------------------------------------------------------------------- | |
275 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
276 | *----------------------------------------------------------------------- | |
277 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
278 | * interrupt status bit - leave PLL multiplication factor unchanged ! | |
279 | */ | |
280 | #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) | |
281 | ||
282 | /*----------------------------------------------------------------------- | |
283 | * SCCR - System Clock and reset Control Register 15-27 | |
284 | *----------------------------------------------------------------------- | |
285 | * Set clock output, timebase and RTC source and divider, | |
286 | * power management and some other internal clocks | |
287 | */ | |
288 | #define SCCR_MASK SCCR_EBDF11 | |
289 | #define CFG_SCCR (SCCR_TBS | \ | |
290 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
291 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
292 | SCCR_DFALCD00) | |
293 | ||
294 | /*----------------------------------------------------------------------- | |
295 | * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler | |
296 | *----------------------------------------------------------------------- | |
297 | * | |
298 | */ | |
299 | #ifdef DEBUG | |
300 | # define CFG_DER 0xFFE7400F /* Debug Enable Register */ | |
301 | #else | |
302 | # define CFG_DER 0 | |
303 | #endif | |
304 | ||
305 | /* | |
306 | * Init Memory Controller: | |
307 | * ~~~~~~~~~~~~~~~~~~~~~~ | |
308 | * | |
309 | * BR0 and OR0 (FLASH) | |
310 | */ | |
311 | ||
c837dcb1 | 312 | #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ |
3bac3513 WD |
313 | |
314 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
315 | * restrict access enough to keep SRAM working (if any) | |
316 | * but not too much to meddle with FLASH accesses | |
317 | */ | |
318 | #define CFG_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */ | |
319 | ||
320 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */ | |
321 | #define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK) | |
322 | ||
323 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) | |
324 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
325 | ||
326 | /* | |
327 | * BR1 and OR1 (SDRAM) | |
328 | * | |
329 | */ | |
c837dcb1 WD |
330 | #define SDRAM_BASE1_PRELIM CFG_SDRAM_BASE /* SDRAM bank #0 */ |
331 | #define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */ | |
3bac3513 | 332 | |
c837dcb1 | 333 | /* SDRAM timing: */ |
3bac3513 WD |
334 | #define CFG_OR_TIMING_SDRAM 0x00000000 |
335 | ||
336 | #define CFG_OR1_PRELIM ((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM ) | |
337 | #define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
338 | ||
339 | /* | |
340 | * BR2 and OR2 (NVRAM) | |
341 | * | |
342 | */ | |
c837dcb1 WD |
343 | #define NVRAM_BASE1_PRELIM CFG_NVRAM_BASE /* NVRAM bank #0 */ |
344 | #define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */ | |
3bac3513 | 345 | |
c837dcb1 | 346 | #define CFG_OR2_PRELIM 0xFFF80160 |
3bac3513 WD |
347 | #define CFG_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) |
348 | ||
349 | /* | |
350 | * Memory Periodic Timer Prescaler | |
351 | */ | |
352 | ||
353 | /* periodic timer for refresh */ | |
c837dcb1 | 354 | #define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ |
3bac3513 WD |
355 | |
356 | /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ | |
357 | #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ | |
c837dcb1 | 358 | #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
3bac3513 | 359 | |
c837dcb1 WD |
360 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
361 | #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ | |
362 | #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
3bac3513 WD |
363 | |
364 | /* | |
365 | * MAMR settings for SDRAM | |
366 | */ | |
367 | ||
368 | /* 8 column SDRAM */ | |
369 | #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
370 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
371 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
372 | /* 9 column SDRAM */ | |
373 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
374 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
375 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
376 | ||
377 | /*----------------------------------------------------------------------- | |
378 | * Internal Definitions | |
379 | *----------------------------------------------------------------------- | |
380 | * | |
381 | */ | |
382 | ||
383 | /* | |
384 | * Boot Flags | |
385 | */ | |
c837dcb1 WD |
386 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
387 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
3bac3513 WD |
388 | |
389 | ||
390 | #endif /* __CONFIG_H */ |