[people/ms/u-boot.git] / include / configs / EP88x.h

/*
 * Copyright (C) 2005 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 *
 * Support for Embedded Planet EP88x boards.
 * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MPC885

#define CONFIG_EP88X				/* Embedded Planet EP88x board	*/

#define CONFIG_BOARD_EARLY_INIT_F		/* Call board_early_init_f	*/

/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE

#define	CONFIG_8xx_CONS_SMC1	1		/* Console is on SMC1		*/
#define CONFIG_BAUDRATE		38400

#define	CONFIG_ETHER_ON_FEC1			/* Enable Ethernet on FEC1	*/
#define	CONFIG_ETHER_ON_FEC2			/* Enable Ethernet on FEC2	*/
#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
#define CFG_DISCOVER_PHY
#define FEC_ENET
#endif /* CONFIG_FEC_ENET */

#define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT	100000000
#define CFG_8xx_CPUCLK_MIN		40000000
#define CFG_8xx_CPUCLK_MAX		133000000

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING


#define CONFIG_BOOTDELAY	5		/* Autoboot after 5 seconds	*/
#define CONFIG_BOOTCOMMAND	"bootm fe060000"	/* Autoboot command	*/
#define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)"

#define CONFIG_BZIP2		/* Include support for bzip2 compressed images  */
#undef	CONFIG_WATCHDOG		/* Disable platform specific watchdog		*/

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 */
#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#define CFG_LONGHELP				/* #undef to save memory	*/
#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)  /* Print Buffer Size */
#define CFG_MAXARGS		16		/* Max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_LOAD_ADDR		0x400000	/* Default load address		*/

#define CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*-----------------------------------------------------------------------
 * RAM configuration (note that CFG_SDRAM_BASE must be zero)
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_SDRAM_MAX_SIZE	0x08000000	/* Up to 128 Mbyte		*/

#define CFG_MAMR		0x00805000

/*
 * 4096	Up to 4096 SDRAM rows
 * 1000	factor s -> ms
 * 32	PTP (pre-divider from MPTPR)
 * 4	Number of refresh cycles per period
 * 64	Refresh cycle in ms per number of rows
 */
#define CFG_PTA_PER_CLK		((4096 * 32 * 1000) / (4 * 64))

#define CFG_MEMTEST_START	0x00100000	/* memtest works on		*/
#define CFG_MEMTEST_END		0x00500000	/* 1 ... 5 MB in SDRAM		*/

#define CFG_RESET_ADDRESS	0x09900000

/*-----------------------------------------------------------------------
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for Monitor   */
#ifdef CONFIG_BZIP2
#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve ~4 MB for malloc()   */
#else
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
#endif /* CONFIG_BZIP2 */

/*-----------------------------------------------------------------------
 * Flash organisation
 */
#define CFG_FLASH_BASE		0xFC000000
#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
#define CFG_MAX_FLASH_BANKS	1		/* Max number of flash banks	*/
#define CFG_MAX_FLASH_SECT	512		/* Max num of sects on one chip */

/* Environment is in flash */
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x20000 	/* We use one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)

#define CFG_OR0_PRELIM		0xFC000160
#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V)

#define	CFG_DIRECT_FLASH_TFTP

/*-----------------------------------------------------------------------
 * BCSR
 */
#define CFG_OR3_PRELIM		0xFF0005B0
#define CFG_BR3_PRELIM		(0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V)

#define CFG_BCSR		0xFA400000

/*-----------------------------------------------------------------------
 * Internal Memory Map Register
 */
#define CFG_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Configuration registers
 */
#ifdef CONFIG_WATCHDOG
#define CFG_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
				 SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
				 SYPCR_SWP)
#else
#define CFG_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
				 SYPCR_SWF  | SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

#define CFG_SIUMCR		(SIUMCR_MLRC01 | SIUMCR_DBGC11)

/* TBSCR - Time Base Status and Control Register */
#define CFG_TBSCR		(TBSCR_TBF | TBSCR_TBE)

/* PISCR - Periodic Interrupt Status and Control */
#define CFG_PISCR       	PISCR_PS

/* SCCR - System Clock and reset Control Register */
#define SCCR_MASK       	SCCR_EBDF11
#define CFG_SCCR		SCCR_RTSEL

#define CFG_DER         	0

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx chips			*/

/*-----------------------------------------------------------------------
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from flash	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

#endif /* __CONFIG_H */
Commit	Line	Data
84c960ce WD	1	/*
	2	* Copyright (C) 2005 Arabella Software Ltd.
	3	* Yuli Barcohen <yuli@arabellasw.com>
	4	*
	5	* Support for Embedded Planet EP88x boards.
	6	* Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	#define CONFIG_MPC885
	30
	31	#define CONFIG_EP88X /* Embedded Planet EP88x board */
	32
	33	#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
	34
	35	/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
	36	#define CONFIG_ENV_OVERWRITE
	37
	38	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	39	#define CONFIG_BAUDRATE 38400
	40
	41	#define CONFIG_ETHER_ON_FEC1 /* Enable Ethernet on FEC1 */
	42	#define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */
	43	#if defined(CONFIG_ETHER_ON_FEC1) \|\| defined(CONFIG_ETHER_ON_FEC2)
	44	#define CFG_DISCOVER_PHY
	45	#define FEC_ENET
	46	#endif /* CONFIG_FEC_ENET */
	47
	48	#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
	49	#define CONFIG_8xx_CPUCLK_DEFAULT 100000000
	50	#define CFG_8xx_CPUCLK_MIN 40000000
	51	#define CFG_8xx_CPUCLK_MAX 133000000
	52
11799434 JL	53	/*
	54	* BOOTP options
	55	*/
	56	#define CONFIG_BOOTP_BOOTFILESIZE
	57	#define CONFIG_BOOTP_BOOTPATH
	58	#define CONFIG_BOOTP_GATEWAY
	59	#define CONFIG_BOOTP_HOSTNAME
	60
	61
dcaa7156 JL	62	/*
	63	* Command line configuration.
	64	*/
	65	#include <config_cmd_default.h>
	66
	67	#define CONFIG_CMD_DHCP
	68	#define CONFIG_CMD_IMMAP
	69	#define CONFIG_CMD_MII
	70	#define CONFIG_CMD_PING
84c960ce	71
84c960ce WD	72
	73	#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
	74	#define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */
	75	#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)"
	76
	77	#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
	78	#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
	79
	80	/*-----------------------------------------------------------------------
	81	* Miscellaneous configurable options
	82	*/
	83	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	84	#define CFG_HUSH_PARSER
	85	#define CFG_PROMPT_HUSH_PS2 "> "
	86	#define CFG_LONGHELP /* #undef to save memory */
	87	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	88	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
	89	#define CFG_MAXARGS 16 /* Max number of command args */
	90	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	91
	92	#define CFG_LOAD_ADDR 0x400000 /* Default load address */
	93
	94	#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
	95
	96	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	97
	98	/*-----------------------------------------------------------------------
	99	* RAM configuration (note that CFG_SDRAM_BASE must be zero)
	100	*/
	101	#define CFG_SDRAM_BASE 0x00000000
	102	#define CFG_SDRAM_MAX_SIZE 0x08000000 /* Up to 128 Mbyte */
	103
	104	#define CFG_MAMR 0x00805000
	105
	106	/*
	107	* 4096 Up to 4096 SDRAM rows
	108	* 1000 factor s -> ms
	109	* 32 PTP (pre-divider from MPTPR)
	110	* 4 Number of refresh cycles per period
	111	* 64 Refresh cycle in ms per number of rows
	112	*/
	113	#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
	114
	115	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	116	#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
	117
	118	#define CFG_RESET_ADDRESS 0x09900000
	119
	120	/*-----------------------------------------------------------------------
	121	* For booting Linux, the board info and command line data
	122	* have to be in the first 8 MB of memory, since this is
	123	* the maximum mapped by the Linux kernel during initialization.
	124	*/
	125	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	126
	127	#define CFG_MONITOR_BASE TEXT_BASE
	128	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
	129	#ifdef CONFIG_BZIP2
	130	#define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
	131	#else
	132	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
	133	#endif /* CONFIG_BZIP2 */
	134
	135	/*-----------------------------------------------------------------------
136	* Flash organisation
137	*/
138	#define CFG_FLASH_BASE 0xFC000000
139	#define CFG_FLASH_CFI /* The flash is CFI compatible */
140	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
141	#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
142	#define CFG_MAX_FLASH_SECT 512 /* Max num of sects on one chip */
143
144	/* Environment is in flash */
145	#define CFG_ENV_IS_IN_FLASH
146	#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */
147	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
148
149	#define CFG_OR0_PRELIM 0xFC000160
150	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| BR_PS_32 \| BR_MS_GPCM \| BR_V)
151
152	#define CFG_DIRECT_FLASH_TFTP
153
154	/*-----------------------------------------------------------------------
155	* BCSR
156	*/
157	#define CFG_OR3_PRELIM 0xFF0005B0
158	#define CFG_BR3_PRELIM (0xFA000000 \|BR_PS_16 \| BR_MS_GPCM \| BR_V)
159
160	#define CFG_BCSR 0xFA400000
161
162	/*-----------------------------------------------------------------------
163	* Internal Memory Map Register
164	*/
165	#define CFG_IMMR 0xF0000000
166
167	/*-----------------------------------------------------------------------
168	* Definitions for initial stack pointer and data area (in DPRAM)
169	*/
170	#define CFG_INIT_RAM_ADDR CFG_IMMR
171	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
172	#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
173	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
174	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
175
176	/*-----------------------------------------------------------------------
177	* Configuration registers
178	*/
179	#ifdef CONFIG_WATCHDOG
180	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| \
181	SYPCR_SWF \| SYPCR_SWE \| SYPCR_SWRI \| \
182	SYPCR_SWP)
183	#else
184	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| \
185	SYPCR_SWF \| SYPCR_SWP)
186	#endif /* CONFIG_WATCHDOG */
187
188	#define CFG_SIUMCR (SIUMCR_MLRC01 \| SIUMCR_DBGC11)
189
190	/* TBSCR - Time Base Status and Control Register */
191	#define CFG_TBSCR (TBSCR_TBF \| TBSCR_TBE)
192
193	/* PISCR - Periodic Interrupt Status and Control */
194	#define CFG_PISCR PISCR_PS
195
196	/* SCCR - System Clock and reset Control Register */
197	#define SCCR_MASK SCCR_EBDF11
198	#define CFG_SCCR SCCR_RTSEL
199
200	#define CFG_DER 0
201
202	/*-----------------------------------------------------------------------
203	* Cache Configuration
204	*/
205	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */
206
207	/*-----------------------------------------------------------------------
208	* Internal Definitions
209	*
210	* Boot Flags
211	*/
212	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
213	#define BOOTFLAG_WARM 0x02 /* Software reboot */
214
215	#endif /* __CONFIG_H */