[people/ms/u-boot.git] / include / configs / ERIC.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_ERIC		1	/* ...on a ERIC board	*/

#define	CONFIG_BOARD_EARLY_INIT_F 1	/* run board_early_init_f() */

#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/

#if 1
#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
#endif
#if 0
#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#endif
#if 0
#define CONFIG_ENV_IS_IN_EEPROM	1	/* use I2C RTC X1240 for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars */
#endif					/* total size of a X1240 is 2048 bytes */

#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57	/* X1240 has two I2C slave addresses, one for EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* address length for the eeprom */
#define CONFIG_I2C_RTC		1	/* we have a Xicor X1240 RTC */
#define CONFIG_SYS_I2C_RTC_ADDR	0x6F	/*                                and one for RTC */

#ifdef CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_NVRAM
#undef CONFIG_ENV_IS_IN_EEPROM
#else
#ifdef CONFIG_ENV_IS_IN_NVRAM
#undef CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_EEPROM
#else
#ifdef CONFIG_ENV_IS_IN_EEPROM
#undef CONFIG_ENV_IS_IN_NVRAM
#undef CONFIG_ENV_IS_IN_FLASH
#endif
#endif
#endif

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#if 1
#define CONFIG_BOOTCOMMAND	"bootm ffc00000" /* autoboot command	*/
#else
#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
#endif

#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/nfs "	\
				"nfsroot=192.168.1.2:/eric_root_devel "	\
				"ip=192.168.1.22:192.168.1.2"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		1	/* PHY address			*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#undef	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	 CONFIG_SYS_EXT_SERIAL_CLOCK	 14318180

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
#undef  CONFIG_PCI_PNP			/* no pci plug-and-play         */
					/* resource configuration       */

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1743	/* PCI Vendor ID: Peppercon AG	*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: 405GP		*/
#define CONFIG_SYS_PCI_PTM1LA	0xFFFC0000	/* point to flash		*/
#define CONFIG_SYS_PCI_PTM1MS	0xFFFFF001	/* 4kB, enable hard-wired to 1	*/
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * External peripheral base address
 *-----------------------------------------------------------------------
 */
/*	Bank 0 - Flash/SRAM	       0xFF000000 16MB	16 Bit */
/*	Bank 1 - NVRAM/RTC	       0xF0000000  1MB	 8 Bit */
/*	Bank 2 - A/D converter	       0xF0100000  1MB	 8 Bit */
/*	Bank 3 - Ethernet PHY Reset    0xF0200000  1MB	 8 Bit */
/*	Bank 4 - PC-MIP PRSNT1#	       0xF0300000  1MB	 8 Bit */
/*	Bank 5 - PC-MIP PRSNT2#	       0xF0400000  1MB	 8 Bit */
/*	Bank 6 - CPU LED0	       0xF0500000  1MB	 8 Bit */
/*	Bank 7 - CPU LED1	       0xF0600000  1MB	 8 Bit */

/* ----------------------------------------------------------------------- */
/*  Memory Bank 0 (Flash) initialization */
/* ----------------------------------------------------------------------- */
#define CS0_AP	0x9B015480
#define CS0_CR	0xFF87A000 /*  BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */
/* ----------------------------------------------------------------------- */
/*  Memory Bank 1 (NVRAM/RTC) initialization */
/* ----------------------------------------------------------------------- */
#define CS1_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
#define CS1_CR	0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
 /* ----------------------------------------------------------------------- */
 /*  Memory Bank 2 (A/D converter) initialization */
 /* ----------------------------------------------------------------------- */
#define CS2_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
#define CS2_CR	0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
/* ----------------------------------------------------------------------- */
/*  Memory Bank 3 (Ethernet PHY Reset) initialization */
/* ----------------------------------------------------------------------- */
#define CS3_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
#define CS3_CR	0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
/* ----------------------------------------------------------------------- */
/*  Memory Bank 4 (PC-MIP PRSNT1#) initialization */
/* ----------------------------------------------------------------------- */
#define CS4_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
#define CS4_CR	0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
/* ----------------------------------------------------------------------- */
/*  Memory Bank 5 (PC-MIP PRSNT2#) initialization */
/* ----------------------------------------------------------------------- */
#define CS5_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
#define CS5_CR	0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
/* ----------------------------------------------------------------------- */
/*  Memory Bank 6 (CPU LED0) initialization */
/* ----------------------------------------------------------------------- */
#define CS6_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
#define CS6_CR	0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
/* ----------------------------------------------------------------------- */
/*  Memory Bank 7 (CPU LED1) initialization */
/* ----------------------------------------------------------------------- */
#define CS7_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
#define CS7_CR	0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */

#define CONFIG_SYS_NVRAM_REG_BASE_ADDR	 0xF0000000
#define CONFIG_SYS_RTC_REG_BASE_ADDR	 (0xF0000000 + 0x7F8)
#define CONFIG_SYS_ADC_REG_BASE_ADDR	 0xF0100000
#define CONFIG_SYS_PHYRES_REG_BASE_ADDR 0xF0200000
#define CONFIG_SYS_PRSNT1_REG_BASE_ADDR 0xF0300000
#define CONFIG_SYS_PRSNT2_REG_BASE_ADDR 0xF0400000
#define CONFIG_SYS_LED0_REG_BASE_ADDR	 0xF0500000
#define CONFIG_SYS_LED1_REG_BASE_ADDR	 0xF0600000


/*  SDRAM CONFIG */
#define CONFIG_SYS_SDRAM_MANUALLY    1
#define CONFIG_SYS_SDRAM_SINGLE_BANK 1

#ifdef CONFIG_SYS_SDRAM_MANUALLY
/*-----------------------------------------------------------------------
 * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
 *----------------------------------------------------------------------*/
#define MB0CF	0x00062001 /*  32MB @ 0 */
/*-----------------------------------------------------------------------
 * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
 *----------------------------------------------------------------------*/
#ifdef CONFIG_SYS_SDRAM_SINGLE_BANK
#define MB1CF	0x0 /*  0MB @ 32MB */
#else
#define MB1CF	0x02062001 /*  32MB @ 32MB */
#endif
/*-----------------------------------------------------------------------
 * Set MB2CF for bank 2. off
 *----------------------------------------------------------------------*/
#define MB2CF	0x0 /*  0MB */
/*-----------------------------------------------------------------------
 * Set MB3CF for bank 3. off
 *----------------------------------------------------------------------*/
#define MB3CF	0x0 /*  0MB */

#define SDTR_100    0x0086400D
#define RTR_100     0x05F0
#define SDTR_66     0x00854006	/* orig U-Boot-wallnut says 0x00854006 */
#define RTR_66      0x03f8

#endif   /* CONFIG_SYS_SDRAM_MANUALLY */


/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		32
#define CONFIG_SYS_FLASH_BASE		0xFF800000      /* 8 MByte Flash */
#define CONFIG_SYS_MONITOR_BASE	0xFFFE0000      /* last 128kByte within Flash */
/*#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)*/	/* Reserve 196 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
#define CONFIG_SYS_FLASH_16BIT		1	/* Rom 16 bit data bus			*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/* BEG ENVIRONNEMENT FLASH */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE       (128*1024)

#if 0  /* force ENV to be NOT embedded */
#define CONFIG_ENV_ADDR            0xfffa0000
#else  /* force ENV to be embedded */
#define	CONFIG_ENV_SIZE		(2 * 1024) /* Total Size of Environment Sector 2k */
#define CONFIG_ENV_ADDR            (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SIZE - 0x10) /* let space for reset vector */
/* #define CONFIG_ENV_ADDR            (CONFIG_SYS_MONITOR_BASE)*/
#define CONFIG_ENV_OFFSET          (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#endif

#endif
/* END ENVIRONNEMENT FLASH */
/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CONFIG_SYS_NVRAM_BASE_ADDR	CONFIG_SYS_NVRAM_REG_BASE_ADDR	/* NVRAM base address	*/
#define CONFIG_SYS_NVRAM_SIZE		0x7F8		/* NVRAM size 2kByte - 8 Byte for RTC */

#ifdef CONFIG_ENV_IS_IN_NVRAM
#define CONFIG_ENV_SIZE		0x7F8		/* Size of Environment vars	*/
#define CONFIG_ENV_ADDR		\
	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
#endif

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0 8MB	*/
#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/


/* Configuration Port location */
/*  #define CONFIG_PORT_ADDR	0xF0000500 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x00df0000  /* inside of SDRAM		       */
#define CONFIG_SYS_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 */
#define SPD_EEPROM_ADDRESS      0x50

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	38	#define CONFIG_ERIC 1 /* ...on a ERIC board */
	39
c837dcb1	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* run board_early_init_f() */
e2211743 WD	41
	42	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	43
	44	#if 1
5a1aceb0	45	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
e2211743 WD	46	#endif
e2211743 WD	47	#if 0
9314cee6	48	#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
e2211743 WD	49	#endif
e2211743 WD	50	#if 0
bb1f8b4f	51	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use I2C RTC X1240 for environment vars */
0e8d1586 JCPV	52	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	53	#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
e2211743 WD	54	#endif /* total size of a X1240 is 2048 bytes */
	55
	56	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf JCPV	57	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	58	#define CONFIG_SYS_I2C_SLAVE 0x7F
e2211743	59
6d0f6bcf JCPV	60	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* X1240 has two I2C slave addresses, one for EEPROM */
6d0f6bcf JCPV	61	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* address length for the eeprom */
e2211743	62	#define CONFIG_I2C_RTC 1 /* we have a Xicor X1240 RTC */
6d0f6bcf	63	#define CONFIG_SYS_I2C_RTC_ADDR 0x6F /* and one for RTC */
e2211743	64
5a1aceb0	65	#ifdef CONFIG_ENV_IS_IN_FLASH
9314cee6	66	#undef CONFIG_ENV_IS_IN_NVRAM
bb1f8b4f	67	#undef CONFIG_ENV_IS_IN_EEPROM
e2211743	68	#else
9314cee6	69	#ifdef CONFIG_ENV_IS_IN_NVRAM
5a1aceb0	70	#undef CONFIG_ENV_IS_IN_FLASH
bb1f8b4f	71	#undef CONFIG_ENV_IS_IN_EEPROM
e2211743	72	#else
bb1f8b4f	73	#ifdef CONFIG_ENV_IS_IN_EEPROM
9314cee6	74	#undef CONFIG_ENV_IS_IN_NVRAM
5a1aceb0	75	#undef CONFIG_ENV_IS_IN_FLASH
e2211743 WD	76	#endif
	77	#endif
	78	#endif
	79
	80	#define CONFIG_BAUDRATE 115200
	81	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	82
	83	#if 1
	84	#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
	85	#else
	86	#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
	87	#endif
	88
	89	#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs " \
	90	"nfsroot=192.168.1.2:/eric_root_devel " \
	91	"ip=192.168.1.22:192.168.1.2"
	92
	93	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	94	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
e2211743	95
96e21f86	96	#define CONFIG_PPC4xx_EMAC
e2211743 WD	97	#define CONFIG_MII 1 /* MII PHY management */
	98	#define CONFIG_PHY_ADDR 1 /* PHY address */
	99
e2211743	100
11799434 JL	101	/*
	102	* BOOTP options
	103	*/
	104	#define CONFIG_BOOTP_BOOTFILESIZE
	105	#define CONFIG_BOOTP_BOOTPATH
	106	#define CONFIG_BOOTP_GATEWAY
	107	#define CONFIG_BOOTP_HOSTNAME
	108
	109
e2211743	110	/*
dcaa7156	111	* Command line configuration.
e2211743	112	*/
dcaa7156 JL	113	#include <config_cmd_default.h>
	114
	115	#define CONFIG_CMD_PCI
	116	#define CONFIG_CMD_IRQ
	117	#define CONFIG_CMD_ENV
	118	#define CONFIG_CMD_FLASH
e2211743	119
e2211743 WD	120
	121	#undef CONFIG_WATCHDOG /* watchdog disabled */
	122
	123	/*
	124	* Miscellaneous configurable options
	125	*/
6d0f6bcf JCPV	126	#undef CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	127	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
dcaa7156	128	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	129	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e2211743	130	#else
6d0f6bcf	131	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743	132	#endif
6d0f6bcf JCPV	133	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	134	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	135	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
e2211743	136
6d0f6bcf JCPV	137	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	138	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
e2211743	139
6d0f6bcf	140	#define CONFIG_SYS_EXT_SERIAL_CLOCK 14318180
e2211743 WD	141
e2211743 WD	142	/* The following table includes the supported baudrates */
6d0f6bcf	143	#define CONFIG_SYS_BAUDRATE_TABLE \
e2211743 WD	144	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	145	57600, 115200, 230400, 460800, 921600 }
	146
6d0f6bcf JCPV	147	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	148	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
e2211743	149
6d0f6bcf	150	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
e2211743 WD	151
	152	/*-----------------------------------------------------------------------
	153	* PCI stuff
	154	*-----------------------------------------------------------------------
	155	*/
	156	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	157	#define PCI_HOST_FORCE 1 /* configure as pci host */
	158	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	159
	160	#define CONFIG_PCI /* include pci support */
	161	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	162	#undef CONFIG_PCI_PNP /* no pci plug-and-play */
8bde7f77	163	/* resource configuration */
e2211743	164
6d0f6bcf JCPV	165	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1743 /* PCI Vendor ID: Peppercon AG */
	166	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: 405GP */
	167	#define CONFIG_SYS_PCI_PTM1LA 0xFFFC0000 /* point to flash */
	168	#define CONFIG_SYS_PCI_PTM1MS 0xFFFFF001 /* 4kB, enable hard-wired to 1 */
	169	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	170	#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
	171	#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
	172	#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
e2211743 WD	173
	174	/*-----------------------------------------------------------------------
	175	* External peripheral base address
	176	*-----------------------------------------------------------------------
	177	*/
	178	/* Bank 0 - Flash/SRAM 0xFF000000 16MB 16 Bit */
	179	/* Bank 1 - NVRAM/RTC 0xF0000000 1MB 8 Bit */
	180	/* Bank 2 - A/D converter 0xF0100000 1MB 8 Bit */
	181	/* Bank 3 - Ethernet PHY Reset 0xF0200000 1MB 8 Bit */
	182	/* Bank 4 - PC-MIP PRSNT1# 0xF0300000 1MB 8 Bit */
	183	/* Bank 5 - PC-MIP PRSNT2# 0xF0400000 1MB 8 Bit */
	184	/* Bank 6 - CPU LED0 0xF0500000 1MB 8 Bit */
	185	/* Bank 7 - CPU LED1 0xF0600000 1MB 8 Bit */
	186
	187	/* ----------------------------------------------------------------------- */
	188	/* Memory Bank 0 (Flash) initialization */
	189	/* ----------------------------------------------------------------------- */
	190	#define CS0_AP 0x9B015480
	191	#define CS0_CR 0xFF87A000 /* BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */
	192	/* ----------------------------------------------------------------------- */
	193	/* Memory Bank 1 (NVRAM/RTC) initialization */
	194	/* ----------------------------------------------------------------------- */
	195	#define CS1_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
	196	#define CS1_CR 0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
	197	/* ----------------------------------------------------------------------- */
	198	/* Memory Bank 2 (A/D converter) initialization */
	199	/* ----------------------------------------------------------------------- */
	200	#define CS2_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
	201	#define CS2_CR 0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
	202	/* ----------------------------------------------------------------------- */
	203	/* Memory Bank 3 (Ethernet PHY Reset) initialization */
	204	/* ----------------------------------------------------------------------- */
	205	#define CS3_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
	206	#define CS3_CR 0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
	207	/* ----------------------------------------------------------------------- */
	208	/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
	209	/* ----------------------------------------------------------------------- */
	210	#define CS4_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
	211	#define CS4_CR 0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
	212	/* ----------------------------------------------------------------------- */
	213	/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
	214	/* ----------------------------------------------------------------------- */
	215	#define CS5_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
	216	#define CS5_CR 0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
	217	/* ----------------------------------------------------------------------- */
	218	/* Memory Bank 6 (CPU LED0) initialization */
	219	/* ----------------------------------------------------------------------- */
	220	#define CS6_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
	221	#define CS6_CR 0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
	222	/* ----------------------------------------------------------------------- */
	223	/* Memory Bank 7 (CPU LED1) initialization */
	224	/* ----------------------------------------------------------------------- */
	225	#define CS7_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
	226	#define CS7_CR 0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
	227
6d0f6bcf JCPV	228	#define CONFIG_SYS_NVRAM_REG_BASE_ADDR 0xF0000000
	229	#define CONFIG_SYS_RTC_REG_BASE_ADDR (0xF0000000 + 0x7F8)
	230	#define CONFIG_SYS_ADC_REG_BASE_ADDR 0xF0100000
	231	#define CONFIG_SYS_PHYRES_REG_BASE_ADDR 0xF0200000
	232	#define CONFIG_SYS_PRSNT1_REG_BASE_ADDR 0xF0300000
	233	#define CONFIG_SYS_PRSNT2_REG_BASE_ADDR 0xF0400000
	234	#define CONFIG_SYS_LED0_REG_BASE_ADDR 0xF0500000
	235	#define CONFIG_SYS_LED1_REG_BASE_ADDR 0xF0600000
e2211743 WD	236
	237
	238	/* SDRAM CONFIG */
6d0f6bcf JCPV	239	#define CONFIG_SYS_SDRAM_MANUALLY 1
6d0f6bcf JCPV	240	#define CONFIG_SYS_SDRAM_SINGLE_BANK 1
e2211743	241
6d0f6bcf	242	#ifdef CONFIG_SYS_SDRAM_MANUALLY
e2211743 WD	243	/*-----------------------------------------------------------------------
	244	* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
	245	----------------------------------------------------------------------/
	246	#define MB0CF 0x00062001 /* 32MB @ 0 */
	247	/*-----------------------------------------------------------------------
	248	* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
	249	----------------------------------------------------------------------/
6d0f6bcf	250	#ifdef CONFIG_SYS_SDRAM_SINGLE_BANK
e2211743 WD	251	#define MB1CF 0x0 /* 0MB @ 32MB */
	252	#else
	253	#define MB1CF 0x02062001 /* 32MB @ 32MB */
	254	#endif
	255	/*-----------------------------------------------------------------------
	256	* Set MB2CF for bank 2. off
	257	----------------------------------------------------------------------/
	258	#define MB2CF 0x0 /* 0MB */
	259	/*-----------------------------------------------------------------------
	260	* Set MB3CF for bank 3. off
	261	----------------------------------------------------------------------/
	262	#define MB3CF 0x0 /* 0MB */
	263
	264	#define SDTR_100 0x0086400D
	265	#define RTR_100 0x05F0
	266	#define SDTR_66 0x00854006 /* orig U-Boot-wallnut says 0x00854006 */
	267	#define RTR_66 0x03f8
	268
6d0f6bcf	269	#endif /* CONFIG_SYS_SDRAM_MANUALLY */
e2211743 WD	270
	271
	272	/*-----------------------------------------------------------------------
	273	* Start addresses for the final memory configuration
	274	* (Set up by the startup code)
6d0f6bcf	275	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
e2211743	276	*/
6d0f6bcf JCPV	277	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	278	#define CONFIG_SYS_SDRAM_SIZE 32
	279	#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* 8 MByte Flash */
	280	#define CONFIG_SYS_MONITOR_BASE 0xFFFE0000 /* last 128kByte within Flash */
	281	/#define CONFIG_SYS_MONITOR_LEN (192 1024)/ / Reserve 196 kB for Monitor */
	282	#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */
	283	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
e2211743 WD	284
	285	/*
	286	* For booting Linux, the board info and command line data
	287	* have to be in the first 8 MB of memory, since this is
	288	* the maximum mapped by the Linux kernel during initialization.
	289	*/
6d0f6bcf	290	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743 WD	291	/*-----------------------------------------------------------------------
	292	* FLASH organization
	293	*/
6d0f6bcf JCPV	294	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	295	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
	296	#define CONFIG_SYS_FLASH_16BIT 1 /* Rom 16 bit data bus */
e2211743	297
6d0f6bcf JCPV	298	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	299	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
e2211743 WD	300
e2211743 WD	301	/* BEG ENVIRONNEMENT FLASH */
5a1aceb0	302	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	303	#define CONFIG_ENV_SECT_SIZE (128*1024)
e2211743 WD	304
e2211743 WD	305	#if 0 /* force ENV to be NOT embedded */
0e8d1586	306	#define CONFIG_ENV_ADDR 0xfffa0000
e2211743	307	#else /* force ENV to be embedded */
0e8d1586	308	#define CONFIG_ENV_SIZE (2 * 1024) /* Total Size of Environment Sector 2k */
6d0f6bcf JCPV	309	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SIZE - 0x10) /* let space for reset vector */
	310	/* #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE)*/
	311	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
e2211743 WD	312	#endif
	313
	314	#endif
	315	/* END ENVIRONNEMENT FLASH */
	316	/*-----------------------------------------------------------------------
	317	* NVRAM organization
	318	*/
6d0f6bcf JCPV	319	#define CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_REG_BASE_ADDR /* NVRAM base address */
6d0f6bcf JCPV	320	#define CONFIG_SYS_NVRAM_SIZE 0x7F8 /* NVRAM size 2kByte - 8 Byte for RTC */
e2211743	321
9314cee6	322	#ifdef CONFIG_ENV_IS_IN_NVRAM
0e8d1586 JCPV	323	#define CONFIG_ENV_SIZE 0x7F8 /* Size of Environment vars */
0e8d1586 JCPV	324	#define CONFIG_ENV_ADDR \
6d0f6bcf	325	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
e2211743	326	#endif
e2211743 WD	327
	328	/*
	329	* Init Memory Controller:
	330	*
	331	* BR0/1 and OR0/1 (FLASH)
	332	*/
	333
53677ef1	334	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */
e2211743 WD	335	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
	336
	337
	338	/* Configuration Port location */
	339	/* #define CONFIG_PORT_ADDR 0xF0000500 */
	340
	341	/*-----------------------------------------------------------------------
	342	* Definitions for initial stack pointer and data area (in DPRAM)
	343	*/
6d0f6bcf JCPV	344	#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
	345	#define CONFIG_SYS_INIT_RAM_END 0x0f00 /* End of used area in RAM */
	346	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	347	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	348	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e2211743 WD	349
	350	/*-----------------------------------------------------------------------
	351	* Definitions for Serial Presence Detect EEPROM address
	352	* (to get SDRAM settings)
	353	*/
	354	#define SPD_EEPROM_ADDRESS 0x50
	355
	356	/*
	357	* Internal Definitions
	358	*
	359	* Boot Flags
	360	*/
	361	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	362	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	363
dcaa7156	364	#if defined(CONFIG_CMD_KGDB)
e2211743 WD	365	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	366	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	367	#endif
	368	#endif /* __CONFIG_H */