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e2211743 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
38 | #define CONFIG_ERIC 1 /* ...on a ERIC board */ | |
39 | ||
40 | #define CONFIG_BOARD_PRE_INIT 1 /* run board_pre_init() */ | |
41 | ||
42 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
43 | ||
44 | #if 1 | |
45 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ | |
46 | #endif | |
47 | #if 0 | |
48 | #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ | |
49 | #endif | |
50 | #if 0 | |
51 | #define CFG_ENV_IS_IN_EEPROM 1 /* use I2C RTC X1240 for environment vars */ | |
52 | #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ | |
53 | #define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */ | |
54 | #endif /* total size of a X1240 is 2048 bytes */ | |
55 | ||
56 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
57 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
58 | #define CFG_I2C_SLAVE 0x7F | |
59 | ||
60 | #define CFG_I2C_EEPROM_ADDR 0x57 /* X1240 has two I2C slave addresses, one for EEPROM */ | |
61 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* address length for the eeprom */ | |
62 | #define CONFIG_I2C_RTC 1 /* we have a Xicor X1240 RTC */ | |
63 | #define CFG_I2C_RTC_ADDR 0x6F /* and one for RTC */ | |
64 | ||
65 | #ifdef CFG_ENV_IS_IN_FLASH | |
66 | #undef CFG_ENV_IS_IN_NVRAM | |
67 | #undef CFG_ENV_IS_IN_EEPROM | |
68 | #else | |
69 | #ifdef CFG_ENV_IS_IN_NVRAM | |
70 | #undef CFG_ENV_IS_IN_FLASH | |
71 | #undef CFG_ENV_IS_IN_EEPROM | |
72 | #else | |
73 | #ifdef CFG_ENV_IS_IN_EEPROM | |
74 | #undef CFG_ENV_IS_IN_NVRAM | |
75 | #undef CFG_ENV_IS_IN_FLASH | |
76 | #endif | |
77 | #endif | |
78 | #endif | |
79 | ||
80 | #define CONFIG_BAUDRATE 115200 | |
81 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
82 | ||
83 | #if 1 | |
84 | #define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ | |
85 | #else | |
86 | #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ | |
87 | #endif | |
88 | ||
89 | #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs " \ | |
90 | "nfsroot=192.168.1.2:/eric_root_devel " \ | |
91 | "ip=192.168.1.22:192.168.1.2" | |
92 | ||
93 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
94 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
95 | ||
96 | #define CONFIG_MII 1 /* MII PHY management */ | |
97 | #define CONFIG_PHY_ADDR 1 /* PHY address */ | |
98 | ||
99 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ | |
100 | CFG_CMD_PCI | \ | |
101 | CFG_CMD_IRQ | \ | |
102 | CFG_CMD_ENV | \ | |
103 | CFG_CMD_FLASH) | |
104 | ||
105 | /* | |
106 | * #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | \ | |
107 | * CFG_CMD_KGDB | CFG_CMD_I2C | CFG_CMD_EEPROM | \ | |
108 | * CFG_CMD_ENV | CFG_CMD_FLASH) | |
109 | */ | |
110 | ||
111 | /* CFG_CMD_ENV est definie */ | |
112 | /* ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_KGDB) & ~(CFG_CMD_ENV)) | |
113 | */ | |
114 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
115 | #include <cmd_confdefs.h> | |
116 | ||
117 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
118 | ||
119 | /* | |
120 | * Miscellaneous configurable options | |
121 | */ | |
122 | #undef CFG_LONGHELP /* undef to save memory */ | |
123 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
124 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
125 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
126 | #else | |
127 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
128 | #endif | |
129 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
130 | #define CFG_MAXARGS 16 /* max number of command args */ | |
131 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
132 | ||
133 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
134 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
135 | ||
136 | #define CFG_EXT_SERIAL_CLOCK 14318180 | |
137 | ||
138 | /* The following table includes the supported baudrates */ | |
139 | #define CFG_BAUDRATE_TABLE \ | |
140 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ | |
141 | 57600, 115200, 230400, 460800, 921600 } | |
142 | ||
143 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
144 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
145 | ||
146 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
147 | ||
148 | /*----------------------------------------------------------------------- | |
149 | * PCI stuff | |
150 | *----------------------------------------------------------------------- | |
151 | */ | |
152 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ | |
153 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
154 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
155 | ||
156 | #define CONFIG_PCI /* include pci support */ | |
157 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
158 | #undef CONFIG_PCI_PNP /* no pci plug-and-play */ | |
8bde7f77 | 159 | /* resource configuration */ |
e2211743 WD |
160 | |
161 | #define CFG_PCI_SUBSYS_VENDORID 0x1743 /* PCI Vendor ID: Peppercon AG */ | |
162 | #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: 405GP */ | |
163 | #define CFG_PCI_PTM1LA 0xFFFC0000 /* point to flash */ | |
164 | #define CFG_PCI_PTM1MS 0xFFFFF001 /* 4kB, enable hard-wired to 1 */ | |
165 | #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
166 | #define CFG_PCI_PTM2LA 0x00000000 /* disabled */ | |
167 | #define CFG_PCI_PTM2MS 0x00000000 /* disabled */ | |
168 | #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
169 | ||
170 | /*----------------------------------------------------------------------- | |
171 | * External peripheral base address | |
172 | *----------------------------------------------------------------------- | |
173 | */ | |
174 | /* Bank 0 - Flash/SRAM 0xFF000000 16MB 16 Bit */ | |
175 | /* Bank 1 - NVRAM/RTC 0xF0000000 1MB 8 Bit */ | |
176 | /* Bank 2 - A/D converter 0xF0100000 1MB 8 Bit */ | |
177 | /* Bank 3 - Ethernet PHY Reset 0xF0200000 1MB 8 Bit */ | |
178 | /* Bank 4 - PC-MIP PRSNT1# 0xF0300000 1MB 8 Bit */ | |
179 | /* Bank 5 - PC-MIP PRSNT2# 0xF0400000 1MB 8 Bit */ | |
180 | /* Bank 6 - CPU LED0 0xF0500000 1MB 8 Bit */ | |
181 | /* Bank 7 - CPU LED1 0xF0600000 1MB 8 Bit */ | |
182 | ||
183 | /* ----------------------------------------------------------------------- */ | |
184 | /* Memory Bank 0 (Flash) initialization */ | |
185 | /* ----------------------------------------------------------------------- */ | |
186 | #define CS0_AP 0x9B015480 | |
187 | #define CS0_CR 0xFF87A000 /* BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */ | |
188 | /* ----------------------------------------------------------------------- */ | |
189 | /* Memory Bank 1 (NVRAM/RTC) initialization */ | |
190 | /* ----------------------------------------------------------------------- */ | |
191 | #define CS1_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ | |
192 | #define CS1_CR 0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ | |
193 | /* ----------------------------------------------------------------------- */ | |
194 | /* Memory Bank 2 (A/D converter) initialization */ | |
195 | /* ----------------------------------------------------------------------- */ | |
196 | #define CS2_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ | |
197 | #define CS2_CR 0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ | |
198 | /* ----------------------------------------------------------------------- */ | |
199 | /* Memory Bank 3 (Ethernet PHY Reset) initialization */ | |
200 | /* ----------------------------------------------------------------------- */ | |
201 | #define CS3_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ | |
202 | #define CS3_CR 0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ | |
203 | /* ----------------------------------------------------------------------- */ | |
204 | /* Memory Bank 4 (PC-MIP PRSNT1#) initialization */ | |
205 | /* ----------------------------------------------------------------------- */ | |
206 | #define CS4_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ | |
207 | #define CS4_CR 0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ | |
208 | /* ----------------------------------------------------------------------- */ | |
209 | /* Memory Bank 5 (PC-MIP PRSNT2#) initialization */ | |
210 | /* ----------------------------------------------------------------------- */ | |
211 | #define CS5_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ | |
212 | #define CS5_CR 0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ | |
213 | /* ----------------------------------------------------------------------- */ | |
214 | /* Memory Bank 6 (CPU LED0) initialization */ | |
215 | /* ----------------------------------------------------------------------- */ | |
216 | #define CS6_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ | |
217 | #define CS6_CR 0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ | |
218 | /* ----------------------------------------------------------------------- */ | |
219 | /* Memory Bank 7 (CPU LED1) initialization */ | |
220 | /* ----------------------------------------------------------------------- */ | |
221 | #define CS7_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ | |
222 | #define CS7_CR 0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ | |
223 | ||
224 | #define CFG_NVRAM_REG_BASE_ADDR 0xF0000000 | |
225 | #define CFG_RTC_REG_BASE_ADDR (0xF0000000 + 0x7F8) | |
226 | #define CFG_ADC_REG_BASE_ADDR 0xF0100000 | |
227 | #define CFG_PHYRES_REG_BASE_ADDR 0xF0200000 | |
228 | #define CFG_PRSNT1_REG_BASE_ADDR 0xF0300000 | |
229 | #define CFG_PRSNT2_REG_BASE_ADDR 0xF0400000 | |
230 | #define CFG_LED0_REG_BASE_ADDR 0xF0500000 | |
231 | #define CFG_LED1_REG_BASE_ADDR 0xF0600000 | |
232 | ||
233 | ||
234 | /* SDRAM CONFIG */ | |
235 | #define CFG_SDRAM_MANUALLY 1 | |
236 | #define CFG_SDRAM_SINGLE_BANK 1 | |
237 | ||
238 | #ifdef CFG_SDRAM_MANUALLY | |
239 | /*----------------------------------------------------------------------- | |
240 | * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) | |
241 | *----------------------------------------------------------------------*/ | |
242 | #define MB0CF 0x00062001 /* 32MB @ 0 */ | |
243 | /*----------------------------------------------------------------------- | |
244 | * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) | |
245 | *----------------------------------------------------------------------*/ | |
246 | #ifdef CFG_SDRAM_SINGLE_BANK | |
247 | #define MB1CF 0x0 /* 0MB @ 32MB */ | |
248 | #else | |
249 | #define MB1CF 0x02062001 /* 32MB @ 32MB */ | |
250 | #endif | |
251 | /*----------------------------------------------------------------------- | |
252 | * Set MB2CF for bank 2. off | |
253 | *----------------------------------------------------------------------*/ | |
254 | #define MB2CF 0x0 /* 0MB */ | |
255 | /*----------------------------------------------------------------------- | |
256 | * Set MB3CF for bank 3. off | |
257 | *----------------------------------------------------------------------*/ | |
258 | #define MB3CF 0x0 /* 0MB */ | |
259 | ||
260 | #define SDTR_100 0x0086400D | |
261 | #define RTR_100 0x05F0 | |
262 | #define SDTR_66 0x00854006 /* orig U-Boot-wallnut says 0x00854006 */ | |
263 | #define RTR_66 0x03f8 | |
264 | ||
265 | #endif /* CFG_SDRAM_MANUALLY */ | |
266 | ||
267 | ||
268 | /*----------------------------------------------------------------------- | |
269 | * Start addresses for the final memory configuration | |
270 | * (Set up by the startup code) | |
271 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
272 | */ | |
273 | #define CFG_SDRAM_BASE 0x00000000 | |
274 | #define CFG_SDRAM_SIZE 32 | |
275 | #define CFG_FLASH_BASE 0xFF800000 /* 8 MByte Flash */ | |
276 | #define CFG_MONITOR_BASE 0xFFFE0000 /* last 128kByte within Flash */ | |
277 | /*#define CFG_MONITOR_LEN (192 * 1024)*/ /* Reserve 196 kB for Monitor */ | |
278 | #define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */ | |
279 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
280 | ||
281 | /* | |
282 | * For booting Linux, the board info and command line data | |
283 | * have to be in the first 8 MB of memory, since this is | |
284 | * the maximum mapped by the Linux kernel during initialization. | |
285 | */ | |
286 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
287 | /*----------------------------------------------------------------------- | |
288 | * FLASH organization | |
289 | */ | |
290 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
291 | #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ | |
292 | #define CFG_FLASH_16BIT 1 /* Rom 16 bit data bus */ | |
293 | ||
294 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
295 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
296 | ||
297 | /* BEG ENVIRONNEMENT FLASH */ | |
298 | #ifdef CFG_ENV_IS_IN_FLASH | |
299 | #define CFG_ENV_SECT_SIZE (128*1024) | |
300 | ||
301 | #if 0 /* force ENV to be NOT embedded */ | |
302 | #define CFG_ENV_ADDR 0xfffa0000 | |
303 | #else /* force ENV to be embedded */ | |
304 | #define CFG_ENV_SIZE (2 * 1024) /* Total Size of Environment Sector 2k */ | |
305 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN - CFG_ENV_SIZE - 0x10) /* let space for reset vector */ | |
306 | /* #define CFG_ENV_ADDR (CFG_MONITOR_BASE)*/ | |
307 | #define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) | |
308 | #endif | |
309 | ||
310 | #endif | |
311 | /* END ENVIRONNEMENT FLASH */ | |
312 | /*----------------------------------------------------------------------- | |
313 | * NVRAM organization | |
314 | */ | |
315 | #define CFG_NVRAM_BASE_ADDR CFG_NVRAM_REG_BASE_ADDR /* NVRAM base address */ | |
316 | #define CFG_NVRAM_SIZE 0x7F8 /* NVRAM size 2kByte - 8 Byte for RTC */ | |
317 | ||
318 | #ifdef CFG_ENV_IS_IN_NVRAM | |
319 | #define CFG_ENV_SIZE 0x7F8 /* Size of Environment vars */ | |
320 | #define CFG_ENV_ADDR \ | |
321 | (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ | |
322 | #endif | |
323 | /*----------------------------------------------------------------------- | |
324 | * Cache Configuration | |
325 | */ | |
326 | #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ | |
327 | #define CFG_CACHELINE_SIZE 32 /* ... */ | |
328 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
329 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
330 | #endif | |
331 | ||
332 | /* | |
333 | * Init Memory Controller: | |
334 | * | |
335 | * BR0/1 and OR0/1 (FLASH) | |
336 | */ | |
337 | ||
338 | #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */ | |
339 | #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ | |
340 | ||
341 | ||
342 | /* Configuration Port location */ | |
343 | /* #define CONFIG_PORT_ADDR 0xF0000500 */ | |
344 | ||
345 | /*----------------------------------------------------------------------- | |
346 | * Definitions for initial stack pointer and data area (in DPRAM) | |
347 | */ | |
348 | #define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ | |
349 | #define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ | |
350 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
351 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
352 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
353 | ||
354 | /*----------------------------------------------------------------------- | |
355 | * Definitions for Serial Presence Detect EEPROM address | |
356 | * (to get SDRAM settings) | |
357 | */ | |
358 | #define SPD_EEPROM_ADDRESS 0x50 | |
359 | ||
360 | /* | |
361 | * Internal Definitions | |
362 | * | |
363 | * Boot Flags | |
364 | */ | |
365 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
366 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
367 | ||
368 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
369 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
370 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
371 | #endif | |
372 | #endif /* __CONFIG_H */ |