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0f8c9768 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ | |
37 | #define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */ | |
38 | ||
39 | #define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */ | |
40 | ||
41 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
42 | #undef CONFIG_8xx_CONS_SMC2 | |
43 | #undef CONFIG_8xx_CONS_NONE | |
44 | ||
45 | #define MPC8XX_FACT 10 /* Multiply by 10 */ | |
46 | #define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */ | |
6d0f6bcf | 47 | #define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20) |
0f8c9768 WD |
48 | #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */ |
49 | ||
50 | #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ | |
51 | ||
52 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
53 | ||
54 | #define CONFIG_BAUDRATE 9600 | |
55 | #if 0 | |
56 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
57 | #else | |
58 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
59 | #endif | |
60 | #define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */ | |
61 | ||
62 | #define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \ | |
63 | "ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 " | |
64 | /* | |
65 | * Miscellaneous configurable options | |
66 | */ | |
67 | ||
68 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 69 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
0f8c9768 WD |
70 | |
71 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
72 | ||
5d2ebe1b JL |
73 | /* |
74 | * BOOTP options | |
75 | */ | |
76 | #define CONFIG_BOOTP_SUBNETMASK | |
77 | #define CONFIG_BOOTP_GATEWAY | |
78 | #define CONFIG_BOOTP_HOSTNAME | |
79 | #define CONFIG_BOOTP_BOOTPATH | |
80 | #define CONFIG_BOOTP_BOOTFILESIZE | |
81 | ||
0f8c9768 | 82 | |
dcaa7156 JL |
83 | /* |
84 | * Command line configuration. | |
85 | */ | |
86 | #include <config_cmd_default.h> | |
87 | ||
0f8c9768 | 88 | |
6d0f6bcf JCPV |
89 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
90 | #define CONFIG_SYS_PROMPT "BOOT: " /* Monitor Command Prompt */ | |
91 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
92 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
93 | #define CONFIG_SYS_MAXARGS 8 /* max number of command args */ | |
94 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
0f8c9768 | 95 | |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
97 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
0f8c9768 | 98 | |
6d0f6bcf | 99 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
0f8c9768 | 100 | |
6d0f6bcf | 101 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
0f8c9768 WD |
102 | |
103 | ||
6d0f6bcf | 104 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
0f8c9768 WD |
105 | |
106 | ||
107 | /* | |
108 | * Low Level Configuration Settings | |
109 | * (address mappings, register initial values, etc.) | |
110 | * You should know what you are doing if you make changes here. | |
111 | */ | |
112 | /*----------------------------------------------------------------------- | |
113 | * Internal Memory Mapped Register | |
114 | */ | |
6d0f6bcf | 115 | #define CONFIG_SYS_IMMR 0xFF000000 |
0f8c9768 WD |
116 | |
117 | /*----------------------------------------------------------------------- | |
118 | * Definitions for initial stack pointer and data area (in DPRAM) | |
119 | */ | |
6d0f6bcf JCPV |
120 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
121 | #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
122 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
123 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
124 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
0f8c9768 WD |
125 | |
126 | ||
0f8c9768 WD |
127 | /*----------------------------------------------------------------------- |
128 | * Start addresses for the final memory configuration | |
129 | * (Set up by the startup code) | |
6d0f6bcf | 130 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
0f8c9768 | 131 | */ |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
133 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
0f8c9768 | 134 | #ifdef DEBUG |
6d0f6bcf | 135 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
0f8c9768 | 136 | #else |
6d0f6bcf | 137 | #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
0f8c9768 | 138 | #endif |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
140 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
0f8c9768 WD |
141 | |
142 | /* | |
143 | * For booting Linux, the board info and command line data | |
144 | * have to be in the first 8 MB of memory, since this is | |
145 | * the maximum mapped by the Linux kernel during initialization. | |
146 | */ | |
6d0f6bcf | 147 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
0f8c9768 WD |
148 | /*----------------------------------------------------------------------- |
149 | * FLASH organization | |
150 | */ | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
152 | #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ | |
0f8c9768 | 153 | |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
155 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
0f8c9768 | 156 | |
5a1aceb0 | 157 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
158 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
159 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
0f8c9768 WD |
160 | /*----------------------------------------------------------------------- |
161 | * Cache Configuration | |
162 | */ | |
6d0f6bcf | 163 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
0f8c9768 WD |
164 | |
165 | /*----------------------------------------------------------------------- | |
166 | * SYPCR - System Protection Control 11-9 | |
167 | * SYPCR can only be written once after reset! | |
168 | *----------------------------------------------------------------------- | |
169 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
170 | */ | |
6d0f6bcf | 171 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
0f8c9768 WD |
172 | |
173 | /*----------------------------------------------------------------------- | |
174 | * SUMCR - SIU Module Configuration 11-6 | |
175 | *----------------------------------------------------------------------- | |
176 | * PCMCIA config., multi-function pin tri-state | |
177 | */ | |
6d0f6bcf | 178 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */ |
0f8c9768 WD |
179 | |
180 | /*----------------------------------------------------------------------- | |
181 | * TBSCR - Time Base Status and Control 11-26 | |
182 | *----------------------------------------------------------------------- | |
183 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
184 | */ | |
6d0f6bcf | 185 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) |
0f8c9768 WD |
186 | |
187 | /* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */ | |
188 | ||
189 | ||
190 | /*----------------------------------------------------------------------- | |
191 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
192 | *----------------------------------------------------------------------- | |
193 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
194 | */ | |
6d0f6bcf | 195 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
0f8c9768 WD |
196 | |
197 | /*----------------------------------------------------------------------- | |
198 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
199 | *----------------------------------------------------------------------- | |
200 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
201 | * interrupt status bit - leave PLL multiplication factor unchanged ! | |
202 | */ | |
6d0f6bcf | 203 | #define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
0f8c9768 WD |
204 | |
205 | /*----------------------------------------------------------------------- | |
206 | * SCCR - System Clock and reset Control Register 15-27 | |
207 | *----------------------------------------------------------------------- | |
208 | * Set clock output, timebase and RTC source and divider, | |
209 | * power management and some other internal clocks | |
210 | */ | |
211 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 212 | #define CONFIG_SYS_SCCR (SCCR_TBS | \ |
0f8c9768 WD |
213 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
214 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
215 | SCCR_DFALCD00) | |
216 | ||
217 | /*----------------------------------------------------------------------- | |
218 | * PCMCIA stuff | |
219 | *----------------------------------------------------------------------- | |
220 | * | |
221 | */ | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
223 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
224 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
225 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
226 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
227 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
228 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
229 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
0f8c9768 | 230 | |
6d0f6bcf | 231 | #define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6 |
0f8c9768 WD |
232 | |
233 | /*----------------------------------------------------------------------- | |
234 | * | |
235 | *----------------------------------------------------------------------- | |
236 | * | |
237 | */ | |
6d0f6bcf JCPV |
238 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
239 | #define CONFIG_SYS_DER 0 | |
240 | /*#define CONFIG_SYS_DER 0x02002000 */ | |
0f8c9768 WD |
241 | |
242 | ||
243 | /* | |
244 | * Init Memory Controller: | |
245 | * | |
246 | * BR0/1 and OR0/1 (FLASH) | |
247 | */ | |
248 | ||
249 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
250 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
251 | ||
252 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
253 | * restrict access enough to keep SRAM working (if any) | |
254 | * but not too much to meddle with FLASH accesses | |
255 | */ | |
6d0f6bcf JCPV |
256 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
257 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
0f8c9768 WD |
258 | |
259 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
6d0f6bcf | 260 | #define CONFIG_SYS_OR_TIMING_FLASH 0x00000160 |
0f8c9768 WD |
261 | /*(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ |
262 | OR_SCY_5_CLK | OR_EHTR) */ | |
263 | ||
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_OR0_REMAP 0x80000160 /*(CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)*/ |
265 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
266 | #define CONFIG_SYS_BR0_PRELIM ( FLASH_BASE0_PRELIM | 0x00000801 ) | |
0f8c9768 | 267 | |
6d0f6bcf JCPV |
268 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
269 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
270 | #define CONFIG_SYS_BR1_PRELIM ( FLASH_BASE1_PRELIM | 0x00000801 ) | |
0f8c9768 WD |
271 | |
272 | /* | |
273 | * BR2/3 and OR2/3 (SDRAM) | |
274 | * | |
275 | */ | |
276 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
277 | #define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */ | |
278 | #define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */ | |
279 | ||
280 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 281 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
0f8c9768 | 282 | |
6d0f6bcf JCPV |
283 | #define CONFIG_SYS_OR2_PRELIM 0xFC000E00 |
284 | #define CONFIG_SYS_BR2_PRELIM (SDRAM_BASE2_PRELIM | 0x00000081) | |
0f8c9768 | 285 | |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
287 | #define CONFIG_SYS_BR3_PRELIM (SDRAM_BASE3_PRELIM | 0x00000081) | |
0f8c9768 WD |
288 | |
289 | ||
290 | /* | |
291 | * Memory Periodic Timer Prescaler | |
292 | */ | |
293 | ||
294 | /* periodic timer for refresh */ | |
6d0f6bcf | 295 | #define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ |
0f8c9768 WD |
296 | |
297 | /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ | |
6d0f6bcf JCPV |
298 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
299 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
0f8c9768 WD |
300 | |
301 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
303 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
0f8c9768 WD |
304 | |
305 | /* | |
306 | * MAMR settings for SDRAM | |
307 | */ | |
308 | ||
309 | /* 8 column SDRAM */ | |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_MAMR_8COL 0x18803112 |
311 | #define CONFIG_SYS_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/ | |
0f8c9768 WD |
312 | |
313 | ||
0f8c9768 WD |
314 | /* |
315 | * Internal Definitions | |
316 | * | |
317 | * Boot Flags | |
318 | */ | |
319 | ||
320 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
321 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
322 | ||
323 | /* | |
324 | * Internal Definitions | |
325 | * | |
326 | * Boot Flags | |
327 | */ | |
328 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
329 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
330 | ||
331 | #endif /* __CONFIG_H */ |