[people/ms/u-boot.git] / include / configs / ESTEEM192E.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
#define CONFIG_ESTEEM192E	1	/* ...on a EST ESTEEM192E	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define CONFIG_FLASH_16BIT	1	/* Rom 16 bit data bus		*/

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef  CONFIG_8xx_CONS_NONE

#define MPC8XX_FACT	10		/* Multiply by 10		*/
#define MPC8XX_XIN	4915200	/* 4.915200 MHz in	- ??? - XXX	*/
#define CONFIG_SYS_PLPRCR_MF	((MPC8XX_FACT-1) << 20)
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz	*/

#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ	/* Force it - dont measure it */

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_BAUDRATE		9600
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_BOOTCOMMAND	"bootm 40030000" /* autoboot command	*/

#define CONFIG_BOOTARGS		"root=/dev/ram rw ramdisk=8192 "			\
				"ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
/*
 * Miscellaneous configurable options
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"BOOT: "	/* Monitor Command Prompt	*/
#define	CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size	*/
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	8			/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000

  /*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET


/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#ifdef	DEBUG
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)

/*-----------------------------------------------------------------------
 * SUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)

/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */


/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CONFIG_SYS_PLPRCR	(CONFIG_SYS_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

#define CONFIG_SYS_PCMCIA_INTERRUPT	SIU_LEVEL6

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER	0x2002000F*/
#define CONFIG_SYS_DER	0
/*#define CONFIG_SYS_DER	0x02002000 */


/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
#define CONFIG_SYS_OR_TIMING_FLASH	0x00000160
				/*(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
				 OR_SCY_5_CLK | OR_EHTR) */

#define CONFIG_SYS_OR0_REMAP	0x80000160     /*(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)*/
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	( FLASH_BASE0_PRELIM | 0x00000801 )

#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
#define CONFIG_SYS_BR1_PRELIM	( FLASH_BASE1_PRELIM | 0x00000801 )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x04000000	/* SDRAM bank #1	*/
#define	SDRAM_MAX_SIZE		0x02000000	/* max 32 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	0xFC000E00
#define CONFIG_SYS_BR2_PRELIM	(SDRAM_BASE2_PRELIM | 0x00000081)

#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
#define CONFIG_SYS_BR3_PRELIM	(SDRAM_BASE3_PRELIM | 0x00000081)


/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	0x18803112
#define CONFIG_SYS_MAMR_9COL	0x18803112	/* same as 8 column because its just easier to port with*/

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
0f8c9768 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
	21	#define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */
	22
2ae18241 WD	23	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	24
0f8c9768 WD	25	#define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */
	26
	27	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	28	#undef CONFIG_8xx_CONS_SMC2
	29	#undef CONFIG_8xx_CONS_NONE
	30
	31	#define MPC8XX_FACT 10 /* Multiply by 10 */
	32	#define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */
6d0f6bcf	33	#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20)
0f8c9768 WD	34	#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */
	35
	36	#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
	37
	38	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	39
	40	#define CONFIG_BAUDRATE 9600
	41	#if 0
	42	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	43	#else
	44	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	45	#endif
	46	#define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */
	47
	48	#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \
	49	"ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
	50	/*
	51	* Miscellaneous configurable options
	52	*/
	53
	54	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	55	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
0f8c9768 WD	56
	57	#undef CONFIG_WATCHDOG /* watchdog disabled */
	58
5d2ebe1b JL	59	/*
	60	* BOOTP options
	61	*/
	62	#define CONFIG_BOOTP_SUBNETMASK
	63	#define CONFIG_BOOTP_GATEWAY
	64	#define CONFIG_BOOTP_HOSTNAME
	65	#define CONFIG_BOOTP_BOOTPATH
	66	#define CONFIG_BOOTP_BOOTFILESIZE
	67
0f8c9768	68
dcaa7156 JL	69	/*
	70	* Command line configuration.
	71	*/
	72	#include <config_cmd_default.h>
	73
0f8c9768	74
6d0f6bcf JCPV	75	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	76	#define CONFIG_SYS_PROMPT "BOOT: " /* Monitor Command Prompt */
	77	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	78	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	79	#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
	80	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0f8c9768	81
6d0f6bcf JCPV	82	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	83	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
0f8c9768	84
6d0f6bcf	85	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
0f8c9768	86
6d0f6bcf	87	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
0f8c9768	88
0f8c9768 WD	89	/*
	90	* Low Level Configuration Settings
	91	* (address mappings, register initial values, etc.)
	92	* You should know what you are doing if you make changes here.
	93	*/
	94	/*-----------------------------------------------------------------------
	95	* Internal Memory Mapped Register
	96	*/
6d0f6bcf	97	#define CONFIG_SYS_IMMR 0xFF000000
0f8c9768 WD	98
	99	/*-----------------------------------------------------------------------
	100	* Definitions for initial stack pointer and data area (in DPRAM)
	101	*/
6d0f6bcf	102	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	103	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	104	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	105	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0f8c9768 WD	106
0f8c9768 WD	107
0f8c9768 WD	108	/*-----------------------------------------------------------------------
	109	* Start addresses for the final memory configuration
	110	* (Set up by the startup code)
6d0f6bcf	111	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0f8c9768	112	*/
6d0f6bcf JCPV	113	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	114	#define CONFIG_SYS_FLASH_BASE 0x40000000
0f8c9768	115	#ifdef DEBUG
6d0f6bcf	116	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
0f8c9768	117	#else
6d0f6bcf	118	#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
0f8c9768	119	#endif
6d0f6bcf JCPV	120	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	121	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
0f8c9768 WD	122
	123	/*
	124	* For booting Linux, the board info and command line data
	125	* have to be in the first 8 MB of memory, since this is
	126	* the maximum mapped by the Linux kernel during initialization.
	127	*/
6d0f6bcf	128	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0f8c9768 WD	129	/*-----------------------------------------------------------------------
	130	* FLASH organization
	131	*/
6d0f6bcf JCPV	132	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	133	#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
0f8c9768	134
6d0f6bcf JCPV	135	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	136	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
0f8c9768	137
5a1aceb0	138	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	139	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586 JCPV	140	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
0f8c9768 WD	141	/*-----------------------------------------------------------------------
	142	* Cache Configuration
	143	*/
6d0f6bcf	144	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
0f8c9768 WD	145
	146	/*-----------------------------------------------------------------------
	147	* SYPCR - System Protection Control 11-9
	148	* SYPCR can only be written once after reset!
	149	*-----------------------------------------------------------------------
	150	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	151	*/
6d0f6bcf	152	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
0f8c9768 WD	153
	154	/*-----------------------------------------------------------------------
	155	* SUMCR - SIU Module Configuration 11-6
	156	*-----------------------------------------------------------------------
	157	* PCMCIA config., multi-function pin tri-state
	158	*/
6d0f6bcf	159	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01) /* DBGC00 */
0f8c9768 WD	160
	161	/*-----------------------------------------------------------------------
	162	* TBSCR - Time Base Status and Control 11-26
	163	*-----------------------------------------------------------------------
	164	* Clear Reference Interrupt Status, Timebase freezing enabled
	165	*/
6d0f6bcf	166	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF \| TBSCR_TBE)
0f8c9768 WD	167
	168	/* (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF) */
	169
	170
	171	/*-----------------------------------------------------------------------
	172	* PISCR - Periodic Interrupt Status and Control 11-31
	173	*-----------------------------------------------------------------------
	174	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	175	*/
6d0f6bcf	176	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
0f8c9768 WD	177
	178	/*-----------------------------------------------------------------------
	179	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	180	*-----------------------------------------------------------------------
	181	* Reset PLL lock status sticky bit, timer expired status bit and timer
	182	* interrupt status bit - leave PLL multiplication factor unchanged !
	183	*/
6d0f6bcf	184	#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF \| PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
0f8c9768 WD	185
	186	/*-----------------------------------------------------------------------
	187	* SCCR - System Clock and reset Control Register 15-27
	188	*-----------------------------------------------------------------------
	189	* Set clock output, timebase and RTC source and divider,
	190	* power management and some other internal clocks
	191	*/
	192	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	193	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
0f8c9768 WD	194	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	195	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	196	SCCR_DFALCD00)
	197
	198	/*-----------------------------------------------------------------------
	199	* PCMCIA stuff
	200	*-----------------------------------------------------------------------
	201	*
	202	*/
6d0f6bcf JCPV	203	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	204	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	205	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	206	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	207	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	208	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	209	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	210	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
0f8c9768	211
6d0f6bcf	212	#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6
0f8c9768 WD	213
	214	/*-----------------------------------------------------------------------
	215	*
	216	*-----------------------------------------------------------------------
	217	*
	218	*/
6d0f6bcf JCPV	219	/#define CONFIG_SYS_DER 0x2002000F/
	220	#define CONFIG_SYS_DER 0
	221	/#define CONFIG_SYS_DER 0x02002000 /
0f8c9768 WD	222
	223
	224	/*
	225	* Init Memory Controller:
	226	*
	227	* BR0/1 and OR0/1 (FLASH)
	228	*/
	229
	230	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	231	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	232
	233	/* used to re-map FLASH both when starting from SRAM or FLASH:
	234	* restrict access enough to keep SRAM working (if any)
	235	* but not too much to meddle with FLASH accesses
	236	*/
6d0f6bcf JCPV	237	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	238	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
0f8c9768 WD	239
0f8c9768 WD	240	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
6d0f6bcf	241	#define CONFIG_SYS_OR_TIMING_FLASH 0x00000160
0f8c9768 WD	242	/*(OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| \
	243	OR_SCY_5_CLK \| OR_EHTR) */
	244
6d0f6bcf JCPV	245	#define CONFIG_SYS_OR0_REMAP 0x80000160 /(CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)/
	246	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	247	#define CONFIG_SYS_BR0_PRELIM ( FLASH_BASE0_PRELIM \| 0x00000801 )
0f8c9768	248
6d0f6bcf JCPV	249	#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
	250	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	251	#define CONFIG_SYS_BR1_PRELIM ( FLASH_BASE1_PRELIM \| 0x00000801 )
0f8c9768 WD	252
	253	/*
	254	* BR2/3 and OR2/3 (SDRAM)
	255	*
	256	*/
	257	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	258	#define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */
	259	#define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */
	260
	261	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	262	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
0f8c9768	263
6d0f6bcf JCPV	264	#define CONFIG_SYS_OR2_PRELIM 0xFC000E00
6d0f6bcf JCPV	265	#define CONFIG_SYS_BR2_PRELIM (SDRAM_BASE2_PRELIM \| 0x00000081)
0f8c9768	266
6d0f6bcf JCPV	267	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
6d0f6bcf JCPV	268	#define CONFIG_SYS_BR3_PRELIM (SDRAM_BASE3_PRELIM \| 0x00000081)
0f8c9768 WD	269
	270
	271	/*
	272	* Memory Periodic Timer Prescaler
	273	*/
	274
	275	/* periodic timer for refresh */
6d0f6bcf	276	#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
0f8c9768 WD	277
0f8c9768 WD	278	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
6d0f6bcf JCPV	279	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	280	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
0f8c9768 WD	281
0f8c9768 WD	282	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	283	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	284	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
0f8c9768 WD	285
	286	/*
	287	* MAMR settings for SDRAM
	288	*/
	289
	290	/* 8 column SDRAM */
6d0f6bcf JCPV	291	#define CONFIG_SYS_MAMR_8COL 0x18803112
6d0f6bcf JCPV	292	#define CONFIG_SYS_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/
0f8c9768	293
0f8c9768	294	#endif /* __CONFIG_H */