[people/ms/u-boot.git] / include / configs / ETX094.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
#define CONFIG_ETX094		1	/* ...on a ETX_094 board	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define	CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		57600
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define	CONFIG_FLASH_16BIT		/* for board with 16bit wide flash	*/
#undef	SB_ETX094			/* only for SB-Board with 16MB SDRAM	*/
#define	CONFIG_BOOTP_RANDOM_DELAY	/* graceful BOOTP recovery mode		*/

#define CONFIG_ETHADDR 08:00:06:00:00:00

#ifdef	CONFIG_ETHADDR
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1	/* default MAC can be overwritten once	*/
#endif

#undef	CONFIG_BOOTARGS
#define CONFIG_RAMBOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/ram rw ramdisk_size=4690 "			\
	"U-Boot_version=U-Boot-1.0.x-Date "					\
	"panic=1 "								\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"
#define CONFIG_NFSBOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/

#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#ifdef	DEBUG
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#ifdef CONFIG_FLASH_16BIT
#define CONFIG_ENV_OFFSET		0x8000	/* Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x8000	/* Total Size of Environment Sector	*/
#else
#define CONFIG_ENV_OFFSET		0x8000	/* Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
#endif

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif	/* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0	*/
#define CONFIG_SYS_OR_TIMING_FLASH    (OR_ACS_DIV2 | OR_BI | \
			       OR_SCY_2_CLK | OR_TRLX )

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)

#ifdef CONFIG_FLASH_16BIT	/* 16 bit data port */
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
#else				/* 32 bit data port */
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
#endif	/* CONFIG_FLASH_16BIT */

#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	23		/* start with divider for 100 MHz	*/

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_1X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_1X)

#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
	37	#define CONFIG_ETX094 1 /* ...on a ETX_094 board */
	38
2ae18241 WD	39	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	40
e2211743 WD	41	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	42	#undef CONFIG_8xx_CONS_SMC2
	43	#undef CONFIG_8xx_CONS_NONE
	44	#define CONFIG_BAUDRATE 57600
	45	#if 0
	46	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	47	#else
	48	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	49	#endif
	50
	51	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	52
	53	#define CONFIG_BOARD_TYPES 1 /* support board types */
	54
	55	#define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */
53677ef1	56	#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */
e2211743 WD	57	#define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */
	58
	59	#define CONFIG_ETHADDR 08:00:06:00:00:00
	60
	61	#ifdef CONFIG_ETHADDR
	62	#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 /* default MAC can be overwritten once */
	63	#endif
	64
	65	#undef CONFIG_BOOTARGS
	66	#define CONFIG_RAMBOOTCOMMAND \
	67	"bootp; " \
	68	"setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \
	69	"U-Boot_version=U-Boot-1.0.x-Date " \
	70	"panic=1 " \
fe126d8b	71	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
e2211743 WD	72	"bootm"
	73	#define CONFIG_NFSBOOTCOMMAND \
	74	"bootp; " \
fe126d8b WD	75	"setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} " \
fe126d8b WD	76	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
e2211743 WD	77	"bootm"
	78	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	79
	80	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	81	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
e2211743 WD	82
	83	#define CONFIG_WATCHDOG 1 /* watchdog enabled */
	84
	85	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	86
5d2ebe1b JL	87
	88	/*
	89	* BOOTP options
	90	*/
	91	#define CONFIG_BOOTP_SUBNETMASK
	92	#define CONFIG_BOOTP_GATEWAY
	93	#define CONFIG_BOOTP_HOSTNAME
	94	#define CONFIG_BOOTP_BOOTPATH
	95	#define CONFIG_BOOTP_BOOTFILESIZE
e2211743	96
dcaa7156 JL	97
	98	/*
	99	* Command line configuration.
	100	*/
	101	#include <config_cmd_default.h>
	102
e2211743 WD	103
	104	/*
	105	* Miscellaneous configurable options
	106	*/
6d0f6bcf JCPV	107	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	108	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
dcaa7156	109	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	110	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e2211743	111	#else
6d0f6bcf	112	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743	113	#endif
6d0f6bcf JCPV	114	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	115	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	116	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
e2211743	117
6d0f6bcf JCPV	118	#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
6d0f6bcf JCPV	119	#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
e2211743	120
6d0f6bcf	121	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
e2211743	122
6d0f6bcf	123	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
e2211743	124
e2211743 WD	125	/*
	126	* Low Level Configuration Settings
	127	* (address mappings, register initial values, etc.)
	128	* You should know what you are doing if you make changes here.
	129	*/
	130	/*-----------------------------------------------------------------------
	131	* Internal Memory Mapped Register
	132	*/
6d0f6bcf	133	#define CONFIG_SYS_IMMR 0xFFF00000
e2211743 WD	134
	135	/*-----------------------------------------------------------------------
	136	* Definitions for initial stack pointer and data area (in DPRAM)
	137	*/
6d0f6bcf	138	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	139	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	140	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	141	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e2211743 WD	142
	143	/*-----------------------------------------------------------------------
	144	* Start addresses for the final memory configuration
	145	* (Set up by the startup code)
6d0f6bcf	146	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
e2211743	147	*/
6d0f6bcf JCPV	148	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	149	#define CONFIG_SYS_FLASH_BASE 0x40000000
e2211743	150	#ifdef DEBUG
6d0f6bcf	151	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
e2211743	152	#else
6d0f6bcf	153	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
e2211743	154	#endif
6d0f6bcf JCPV	155	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	156	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
e2211743 WD	157
	158	/*
	159	* For booting Linux, the board info and command line data
	160	* have to be in the first 8 MB of memory, since this is
	161	* the maximum mapped by the Linux kernel during initialization.
	162	*/
6d0f6bcf	163	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743 WD	164	/*-----------------------------------------------------------------------
	165	* FLASH organization
	166	*/
6d0f6bcf JCPV	167	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	168	#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
e2211743	169
6d0f6bcf JCPV	170	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	171	#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
e2211743	172
5a1aceb0	173	#define CONFIG_ENV_IS_IN_FLASH 1
e2211743	174	#ifdef CONFIG_FLASH_16BIT
0e8d1586 JCPV	175	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586 JCPV	176	#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
e2211743	177	#else
0e8d1586 JCPV	178	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586 JCPV	179	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
e2211743 WD	180	#endif
	181
	182	/*-----------------------------------------------------------------------
	183	* Hardware Information Block
	184	*/
6d0f6bcf JCPV	185	#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
	186	#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
	187	#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
e2211743 WD	188
	189	/*-----------------------------------------------------------------------
	190	* Cache Configuration
	191	*/
6d0f6bcf	192	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
dcaa7156	193	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	194	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
e2211743 WD	195	#endif
	196
	197	/*-----------------------------------------------------------------------
	198	* SYPCR - System Protection Control 11-9
	199	* SYPCR can only be written once after reset!
	200	*-----------------------------------------------------------------------
	201	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	202	*/
	203	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	204	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
e2211743 WD	205	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
e2211743 WD	206	#else
6d0f6bcf	207	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
e2211743 WD	208	#endif /* CONFIG_WATCHDOG */
	209
	210	/*-----------------------------------------------------------------------
	211	* SIUMCR - SIU Module Configuration 11-6
	212	*-----------------------------------------------------------------------
	213	* PCMCIA config., multi-function pin tri-state
	214	*/
6d0f6bcf	215	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
e2211743 WD	216
	217	/*-----------------------------------------------------------------------
	218	* TBSCR - Time Base Status and Control 11-26
	219	*-----------------------------------------------------------------------
	220	* Clear Reference Interrupt Status, Timebase freezing enabled
	221	*/
6d0f6bcf	222	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
e2211743 WD	223
	224	/*-----------------------------------------------------------------------
	225	* RTCSC - Real-Time Clock Status and Control Register 11-27
	226	*-----------------------------------------------------------------------
	227	*/
6d0f6bcf	228	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
e2211743 WD	229
	230	/*-----------------------------------------------------------------------
	231	* PISCR - Periodic Interrupt Status and Control 11-31
	232	*-----------------------------------------------------------------------
	233	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	234	*/
6d0f6bcf	235	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
e2211743 WD	236
	237	/*-----------------------------------------------------------------------
	238	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	239	*-----------------------------------------------------------------------
	240	* Reset PLL lock status sticky bit, timer expired status bit and timer
	241	* interrupt status bit - leave PLL multiplication factor unchanged !
	242	*/
6d0f6bcf	243	#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
e2211743 WD	244
	245	/*-----------------------------------------------------------------------
	246	* SCCR - System Clock and reset Control Register 15-27
	247	*-----------------------------------------------------------------------
	248	* Set clock output, timebase and RTC source and divider,
	249	* power management and some other internal clocks
	250	*/
	251	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	252	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
e2211743 WD	253	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	254	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	255	SCCR_DFALCD00)
	256
	257	/*-----------------------------------------------------------------------
	258	* PCMCIA stuff
	259	*-----------------------------------------------------------------------
	260	*
	261	*/
6d0f6bcf JCPV	262	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	263	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	264	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	265	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	266	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	267	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	268	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	269	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
e2211743 WD	270
	271	/*-----------------------------------------------------------------------
	272	*
	273	*-----------------------------------------------------------------------
	274	*
	275	*/
6d0f6bcf	276	#define CONFIG_SYS_DER 0
e2211743 WD	277
	278	/*
	279	* Init Memory Controller:
	280	*
	281	* BR0/1 and OR0/1 (FLASH)
	282	*/
	283
	284	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	285	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	286
	287	/* used to re-map FLASH both when starting from SRAM or FLASH:
	288	* restrict access enough to keep SRAM working (if any)
	289	* but not too much to meddle with FLASH accesses
	290	*/
6d0f6bcf JCPV	291	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	292	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
e2211743 WD	293
e2211743 WD	294	/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */
6d0f6bcf	295	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 \| OR_BI \| \
8bde7f77	296	OR_SCY_2_CLK \| OR_TRLX )
e2211743	297
6d0f6bcf JCPV	298	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	299	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
e2211743 WD	300
e2211743 WD	301	#ifdef CONFIG_FLASH_16BIT /* 16 bit data port */
6d0f6bcf JCPV	302	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V \| BR_PS_16)
6d0f6bcf JCPV	303	#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V \| BR_PS_16)
e2211743	304	#else /* 32 bit data port */
6d0f6bcf JCPV	305	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V \| BR_PS_32)
6d0f6bcf JCPV	306	#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V \| BR_PS_32)
e2211743 WD	307	#endif /* CONFIG_FLASH_16BIT */
e2211743 WD	308
6d0f6bcf JCPV	309	#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
6d0f6bcf JCPV	310	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
e2211743 WD	311
	312	/*
	313	* BR2/3 and OR2/3 (SDRAM)
	314	*
	315	*/
	316	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	317	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
	318	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	319
	320	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	321	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
e2211743	322
6d0f6bcf JCPV	323	#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	324	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
e2211743	325
6d0f6bcf JCPV	326	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
6d0f6bcf JCPV	327	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
e2211743 WD	328
	329	/*
	330	* Memory Periodic Timer Prescaler
	331	*/
	332
	333	/* periodic timer for refresh */
6d0f6bcf	334	#define CONFIG_SYS_MAMR_PTA 23 /* start with divider for 100 MHz */
e2211743 WD	335
e2211743 WD	336	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
6d0f6bcf JCPV	337	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	338	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
e2211743 WD	339
e2211743 WD	340	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	341	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	342	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
e2211743 WD	343
	344	/*
	345	* MAMR settings for SDRAM
	346	*/
	347
	348	/* 8 column SDRAM */
6d0f6bcf	349	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
e2211743 WD	350	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	351	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_1X)
	352	/* 9 column SDRAM */
6d0f6bcf	353	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
e2211743 WD	354	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	355	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_1X)
	356
e2211743	357	#endif /* __CONFIG_H */