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e2211743 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ | |
37 | #define CONFIG_ETX094 1 /* ...on a ETX_094 board */ | |
38 | ||
2ae18241 WD |
39 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
40 | ||
e2211743 WD |
41 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
42 | #undef CONFIG_8xx_CONS_SMC2 | |
43 | #undef CONFIG_8xx_CONS_NONE | |
44 | #define CONFIG_BAUDRATE 57600 | |
45 | #if 0 | |
46 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
47 | #else | |
48 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
49 | #endif | |
50 | ||
51 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
52 | ||
53 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
54 | ||
55 | #define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */ | |
53677ef1 | 56 | #undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ |
e2211743 WD |
57 | #define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */ |
58 | ||
59 | #define CONFIG_ETHADDR 08:00:06:00:00:00 | |
60 | ||
61 | #ifdef CONFIG_ETHADDR | |
62 | #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 /* default MAC can be overwritten once */ | |
63 | #endif | |
64 | ||
65 | #undef CONFIG_BOOTARGS | |
66 | #define CONFIG_RAMBOOTCOMMAND \ | |
67 | "bootp; " \ | |
68 | "setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \ | |
69 | "U-Boot_version=U-Boot-1.0.x-Date " \ | |
70 | "panic=1 " \ | |
fe126d8b | 71 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ |
e2211743 WD |
72 | "bootm" |
73 | #define CONFIG_NFSBOOTCOMMAND \ | |
74 | "bootp; " \ | |
fe126d8b WD |
75 | "setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} " \ |
76 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
e2211743 WD |
77 | "bootm" |
78 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
79 | ||
80 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 81 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
e2211743 WD |
82 | |
83 | #define CONFIG_WATCHDOG 1 /* watchdog enabled */ | |
84 | ||
85 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
86 | ||
5d2ebe1b JL |
87 | |
88 | /* | |
89 | * BOOTP options | |
90 | */ | |
91 | #define CONFIG_BOOTP_SUBNETMASK | |
92 | #define CONFIG_BOOTP_GATEWAY | |
93 | #define CONFIG_BOOTP_HOSTNAME | |
94 | #define CONFIG_BOOTP_BOOTPATH | |
95 | #define CONFIG_BOOTP_BOOTFILESIZE | |
e2211743 | 96 | |
dcaa7156 JL |
97 | |
98 | /* | |
99 | * Command line configuration. | |
100 | */ | |
101 | #include <config_cmd_default.h> | |
102 | ||
e2211743 WD |
103 | |
104 | /* | |
105 | * Miscellaneous configurable options | |
106 | */ | |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
108 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
dcaa7156 | 109 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 110 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
e2211743 | 111 | #else |
6d0f6bcf | 112 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
e2211743 | 113 | #endif |
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
115 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
116 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
e2211743 | 117 | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ |
119 | #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ | |
e2211743 | 120 | |
6d0f6bcf | 121 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
e2211743 | 122 | |
6d0f6bcf | 123 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
e2211743 | 124 | |
6d0f6bcf | 125 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
e2211743 WD |
126 | |
127 | /* | |
128 | * Low Level Configuration Settings | |
129 | * (address mappings, register initial values, etc.) | |
130 | * You should know what you are doing if you make changes here. | |
131 | */ | |
132 | /*----------------------------------------------------------------------- | |
133 | * Internal Memory Mapped Register | |
134 | */ | |
6d0f6bcf | 135 | #define CONFIG_SYS_IMMR 0xFFF00000 |
e2211743 WD |
136 | |
137 | /*----------------------------------------------------------------------- | |
138 | * Definitions for initial stack pointer and data area (in DPRAM) | |
139 | */ | |
6d0f6bcf | 140 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 141 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
6d0f6bcf | 142 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
553f0982 | 143 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) |
6d0f6bcf | 144 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
e2211743 WD |
145 | |
146 | /*----------------------------------------------------------------------- | |
147 | * Start addresses for the final memory configuration | |
148 | * (Set up by the startup code) | |
6d0f6bcf | 149 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
e2211743 | 150 | */ |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
152 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
e2211743 | 153 | #ifdef DEBUG |
6d0f6bcf | 154 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
e2211743 | 155 | #else |
6d0f6bcf | 156 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
e2211743 | 157 | #endif |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
159 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
e2211743 WD |
160 | |
161 | /* | |
162 | * For booting Linux, the board info and command line data | |
163 | * have to be in the first 8 MB of memory, since this is | |
164 | * the maximum mapped by the Linux kernel during initialization. | |
165 | */ | |
6d0f6bcf | 166 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
e2211743 WD |
167 | /*----------------------------------------------------------------------- |
168 | * FLASH organization | |
169 | */ | |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
171 | #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ | |
e2211743 | 172 | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
174 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
e2211743 | 175 | |
5a1aceb0 | 176 | #define CONFIG_ENV_IS_IN_FLASH 1 |
e2211743 | 177 | #ifdef CONFIG_FLASH_16BIT |
0e8d1586 JCPV |
178 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
179 | #define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ | |
e2211743 | 180 | #else |
0e8d1586 JCPV |
181 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
182 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
e2211743 WD |
183 | #endif |
184 | ||
185 | /*----------------------------------------------------------------------- | |
186 | * Hardware Information Block | |
187 | */ | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
189 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
190 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
e2211743 WD |
191 | |
192 | /*----------------------------------------------------------------------- | |
193 | * Cache Configuration | |
194 | */ | |
6d0f6bcf | 195 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
dcaa7156 | 196 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 197 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
e2211743 WD |
198 | #endif |
199 | ||
200 | /*----------------------------------------------------------------------- | |
201 | * SYPCR - System Protection Control 11-9 | |
202 | * SYPCR can only be written once after reset! | |
203 | *----------------------------------------------------------------------- | |
204 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
205 | */ | |
206 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 207 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
e2211743 WD |
208 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
209 | #else | |
6d0f6bcf | 210 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
e2211743 WD |
211 | #endif /* CONFIG_WATCHDOG */ |
212 | ||
213 | /*----------------------------------------------------------------------- | |
214 | * SIUMCR - SIU Module Configuration 11-6 | |
215 | *----------------------------------------------------------------------- | |
216 | * PCMCIA config., multi-function pin tri-state | |
217 | */ | |
6d0f6bcf | 218 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
e2211743 WD |
219 | |
220 | /*----------------------------------------------------------------------- | |
221 | * TBSCR - Time Base Status and Control 11-26 | |
222 | *----------------------------------------------------------------------- | |
223 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
224 | */ | |
6d0f6bcf | 225 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
e2211743 WD |
226 | |
227 | /*----------------------------------------------------------------------- | |
228 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
229 | *----------------------------------------------------------------------- | |
230 | */ | |
6d0f6bcf | 231 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
e2211743 WD |
232 | |
233 | /*----------------------------------------------------------------------- | |
234 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
235 | *----------------------------------------------------------------------- | |
236 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
237 | */ | |
6d0f6bcf | 238 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
e2211743 WD |
239 | |
240 | /*----------------------------------------------------------------------- | |
241 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
242 | *----------------------------------------------------------------------- | |
243 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
244 | * interrupt status bit - leave PLL multiplication factor unchanged ! | |
245 | */ | |
6d0f6bcf | 246 | #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
e2211743 WD |
247 | |
248 | /*----------------------------------------------------------------------- | |
249 | * SCCR - System Clock and reset Control Register 15-27 | |
250 | *----------------------------------------------------------------------- | |
251 | * Set clock output, timebase and RTC source and divider, | |
252 | * power management and some other internal clocks | |
253 | */ | |
254 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 255 | #define CONFIG_SYS_SCCR (SCCR_TBS | \ |
e2211743 WD |
256 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
257 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
258 | SCCR_DFALCD00) | |
259 | ||
260 | /*----------------------------------------------------------------------- | |
261 | * PCMCIA stuff | |
262 | *----------------------------------------------------------------------- | |
263 | * | |
264 | */ | |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
266 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
267 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
268 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
269 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
270 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
271 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
272 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
e2211743 WD |
273 | |
274 | /*----------------------------------------------------------------------- | |
275 | * | |
276 | *----------------------------------------------------------------------- | |
277 | * | |
278 | */ | |
6d0f6bcf | 279 | #define CONFIG_SYS_DER 0 |
e2211743 WD |
280 | |
281 | /* | |
282 | * Init Memory Controller: | |
283 | * | |
284 | * BR0/1 and OR0/1 (FLASH) | |
285 | */ | |
286 | ||
287 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
288 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
289 | ||
290 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
291 | * restrict access enough to keep SRAM working (if any) | |
292 | * but not too much to meddle with FLASH accesses | |
293 | */ | |
6d0f6bcf JCPV |
294 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
295 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
e2211743 WD |
296 | |
297 | /* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */ | |
6d0f6bcf | 298 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | \ |
8bde7f77 | 299 | OR_SCY_2_CLK | OR_TRLX ) |
e2211743 | 300 | |
6d0f6bcf JCPV |
301 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
302 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
e2211743 WD |
303 | |
304 | #ifdef CONFIG_FLASH_16BIT /* 16 bit data port */ | |
6d0f6bcf JCPV |
305 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) |
306 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) | |
e2211743 | 307 | #else /* 32 bit data port */ |
6d0f6bcf JCPV |
308 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) |
309 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) | |
e2211743 WD |
310 | #endif /* CONFIG_FLASH_16BIT */ |
311 | ||
6d0f6bcf JCPV |
312 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
313 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
e2211743 WD |
314 | |
315 | /* | |
316 | * BR2/3 and OR2/3 (SDRAM) | |
317 | * | |
318 | */ | |
319 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
320 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
321 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
322 | ||
323 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 324 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
e2211743 | 325 | |
6d0f6bcf JCPV |
326 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
327 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
e2211743 | 328 | |
6d0f6bcf JCPV |
329 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
330 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
e2211743 WD |
331 | |
332 | /* | |
333 | * Memory Periodic Timer Prescaler | |
334 | */ | |
335 | ||
336 | /* periodic timer for refresh */ | |
6d0f6bcf | 337 | #define CONFIG_SYS_MAMR_PTA 23 /* start with divider for 100 MHz */ |
e2211743 WD |
338 | |
339 | /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ | |
6d0f6bcf JCPV |
340 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
341 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
e2211743 WD |
342 | |
343 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf JCPV |
344 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
345 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
e2211743 WD |
346 | |
347 | /* | |
348 | * MAMR settings for SDRAM | |
349 | */ | |
350 | ||
351 | /* 8 column SDRAM */ | |
6d0f6bcf | 352 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
e2211743 WD |
353 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
354 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) | |
355 | /* 9 column SDRAM */ | |
6d0f6bcf | 356 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
e2211743 WD |
357 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
358 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) | |
359 | ||
e2211743 | 360 | #endif /* __CONFIG_H */ |