[people/ms/u-boot.git] / include / configs / EVB64260.h

/*
 * (C) Copyright 2001
 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifndef __ASSEMBLY__
#include <galileo/core.h>
#endif

#include "../board/evb64260/local.h"

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_EVB64260		1	/* this is an EVB64260 board	*/
#define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */

#define	CONFIG_SYS_TEXT_BASE	0xfff00000
#define	CONFIG_SYS_LDSCRIPT	"board/evb64260/u-boot.lds"

#define CONFIG_BAUDRATE		38400	/* console baudrate = 38400	*/

#undef	CONFIG_ECC			/* enable ECC support */
/* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */

/* which initialization functions to call for this board */
#define CONFIG_MISC_INIT_R	1
#define CONFIG_BOARD_EARLY_INIT_F 1

#ifndef CONFIG_EVB64260_750CX
#define CONFIG_SYS_BOARD_NAME		"EVB64260"
#else
#define CONFIG_SYS_BOARD_NAME         "EVB64260-750CX"
#endif

#define CONFIG_SYS_HUSH_PARSER

/*
 * The following defines let you select what serial you want to use
 * for your console driver.
 *
 * what to do:
 * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
 * to 0 below.
 *
 * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
 */
#define	CONFIG_MPSC
#define CONFIG_MPSC_PORT	0


/* define this if you want to enable GT MAC filtering */
#define CONFIG_GT_USE_MAC_HASH_TABLE

#undef CONFIG_ETHER_PORT_MII	/* use RMII */

#if 1
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_ZERO_BOOTDELAY_CHECK

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND						     \
	"bootp && "						     \
	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
	"ip=$ipaddr:$serverip:$gatewayip:" \
	"$netmask:$hostname:eth0:none; && " \
	"bootm"

#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
#define	CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
#undef	CONFIG_ALTIVEC                  /* undef to disable             */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV


/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address	*/

#define	CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks	*/
#define CONFIG_SYS_BUS_CLK		100000000	/* 100 MHz		*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#ifdef CONFIG_EVB64260_750CX
#define CONFIG_750CX
#define CONFIG_SYS_BROKEN_CL2
#endif

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
#define	CONFIG_SYS_INIT_RAM_SIZE	0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_RAM_LOCK


/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xfff00000
#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */

/* areas to map different things with the GT in physical space */
#define CONFIG_SYS_DRAM_BANKS		4
#define CONFIG_SYS_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */

/* What to put in the bats. */
#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000

/* Peripheral Device section */
#define CONFIG_SYS_GT_REGS		0xf8000000
#define CONFIG_SYS_DEV_BASE		0xfc000000

#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE
#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)

#define CONFIG_SYS_DEV0_SIZE		 _8M /* evb64260 sram  @ 0xfc00.0000 */
#define CONFIG_SYS_DEV1_SIZE		 _8M /* evb64260 rtc   @ 0xfc80.0000 */
#define CONFIG_SYS_DEV2_SIZE		_16M /* evb64260 duart @ 0xfd00.0000 */
#define CONFIG_SYS_DEV3_SIZE		_16M /* evb64260 flash @ 0xfe00.0000 */

#define CONFIG_SYS_DEV0_PAR		0x20205093
#define CONFIG_SYS_DEV1_PAR		0xcfcfffff
#define CONFIG_SYS_DEV2_PAR		0xc0059bd4
#define CONFIG_SYS_8BIT_BOOT_PAR	0xc00b5e7c
#define CONFIG_SYS_32BIT_BOOT_PAR	0xc4a8241c
	/*   c    4    a      8     2     4    1      c		*/
	/* 33 22|2222|22 22|111 1|11 11|1 1  |    |		*/
	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/

#if 0 /* Wrong?? NTL */
#define CONFIG_SYS_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
						/* DMAAck[1:0] GNT0[1:0] */
#else
#define CONFIG_SYS_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
						/* REQ0[1:0] GNT0[1:0] */
#endif
#define CONFIG_SYS_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
						/* DMAReq[4] DMAAck[4] WDNMI WDE */
#if 0 /* Wrong?? NTL */
#define CONFIG_SYS_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
						/* DMAAck[1:0] GNT1[1:0] */
#else
#define CONFIG_SYS_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
						/* GPP[22] (RS232IntB or PCI1Int) */
						/* GPP[21] (RS323IntA) */
						/* BClkIn */
						/* REQ1[1:0] GNT1[1:0] */
#endif

#if 0 /* Wrong?? NTL */
# define CONFIG_SYS_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
						/* GPP[27:26] Int[1:0] */
#else
# define CONFIG_SYS_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
						/* GPP[29]    (PCI1Int) */
						/* BClkOut0 */
						/* GPP[27]    (PCI0Int) */
						/* GPP[26]    (RtcInt or PCI1Int) */
						/* CPUInt[25:24] */
#endif

# define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102	/* 0=hiZ  1=MPSC0 2=ETH 0 and 2 RMII */

#if 0 /* Wrong?? - NTL */
# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x000002c6
#else
# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
						/* gpp[29] */
						/* gpp[27:26] */
						/* gpp[22:21] */

# define CONFIG_SYS_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
				/* idmas use buffer 1,1
				   comm use buffer 0
				   pci use buffer 1,1
				   cpu use buffer 0
				   normal load (see also ifdef HVL)
				   standard SDRAM (see also ifdef REG)
				   non staggered refresh */
				/* 31:26  25 23  20 19 18 16 */
				/* 110110 00 111 0  0  00 1 */
				/* refresh_count=0x200
				   phisical interleaving disable
				   virtual interleaving enable */
				/* 15 14 13:0 */
				/* 1  0  0x200 */
#endif

#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
#define CONFIG_SYS_INIT_CHAN1
#define CONFIG_SYS_INIT_CHAN2

#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
#define SRAM_SIZE		0x00100000		/* 1 MB of sram */


/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */

#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI                      /* include pci support          */
#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */

/* PCI MEMORY MAP section */
#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
#define CONFIG_SYS_PCI1_MEM_SIZE	_128M

#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)


/* PCI I/O MAP section */
#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
#define CONFIG_SYS_PCI0_IO_SIZE	_16M
#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
#define CONFIG_SYS_PCI1_IO_SIZE	_16M

#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550

#define CONFIG_SYS_NS16550_REG_SIZE	-4

#define CONFIG_SYS_NS16550_CLK		3686400

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_DUART_IO + 0)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_DUART_IO + 0x20)

/*----------------------------------------------------------------------
 * Initial BAT mappings
 */

/* NOTES:
 * 1) GUARDED and WRITE_THRU not allowed in IBATS
 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 */

/* SDRAM */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U

/* init ram */
#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U

/* PCI0, PCI1 in one BAT */
#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* GT regs, bootrom, all the devices, PCI I/O */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U

/* I2C speed and slave address (for compatability) defaults */
#define CONFIG_SYS_I2C_SPEED	400000
#define CONFIG_SYS_I2C_SLAVE	0x7F

/* I2C addresses for the two DIMM SPD chips */
#ifndef CONFIG_EVB64260_750CX
#define DIMM0_I2C_ADDR	0x56
#define DIMM1_I2C_ADDR	0x54
#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
#define DIMM0_I2C_ADDR  0x54
#define DIMM1_I2C_ADDR	0x54
#endif

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */

#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE3	/* extra flash at device 3 */
#define CONFIG_SYS_EXTRA_FLASH_WIDTH	4	/* 32 bit */

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_CFI		1

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_ADDR    (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * L2CR setup -- make sure this is right for your board!
 * look in include/74xx_7xx.h for the defines used here
 */

#define CONFIG_SYS_L2

#ifdef CONFIG_750CX
#define L2_INIT		0
#else
#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
			 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
#endif

#define L2_ENABLE	(L2_INIT | L2CR_L2E)

#define CONFIG_SYS_BOARD_ASM_INIT      1


#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
c609719b WD	15	#ifndef __ASSEMBLY__
	16	#include <galileo/core.h>
	17	#endif
	18
	19	#include "../board/evb64260/local.h"
	20
	21	/*
	22	* High Level Configuration Options
	23	* (easy to change)
	24	*/
	25
	26	#define CONFIG_EVB64260 1 /* this is an EVB64260 board */
6d0f6bcf	27	#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
c609719b	28
2ae18241	29	#define CONFIG_SYS_TEXT_BASE 0xfff00000
e2c2a95e	30	#define CONFIG_SYS_LDSCRIPT "board/evb64260/u-boot.lds"
2ae18241	31
53677ef1	32	#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
c609719b WD	33
	34	#undef CONFIG_ECC /* enable ECC support */
	35	/* #define CONFIG_EVB64260_750CX 1 / / Support the EVB-64260-750CX Board */
	36
	37	/* which initialization functions to call for this board */
	38	#define CONFIG_MISC_INIT_R 1
c837dcb1	39	#define CONFIG_BOARD_EARLY_INIT_F 1
c609719b WD	40
c609719b WD	41	#ifndef CONFIG_EVB64260_750CX
6d0f6bcf	42	#define CONFIG_SYS_BOARD_NAME "EVB64260"
c609719b	43	#else
6d0f6bcf	44	#define CONFIG_SYS_BOARD_NAME "EVB64260-750CX"
c609719b WD	45	#endif
c609719b WD	46
6d0f6bcf	47	#define CONFIG_SYS_HUSH_PARSER
c609719b WD	48
	49	/*
	50	* The following defines let you select what serial you want to use
	51	* for your console driver.
	52	*
	53	* what to do:
	54	* to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
6d0f6bcf	55	* cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
c609719b WD	56	* to 0 below.
	57	*
	58	* to use the MPSC, #define CONFIG_MPSC. If you have wired up another
	59	* mpsc channel, change CONFIG_MPSC_PORT to the desired value.
	60	*/
	61	#define CONFIG_MPSC
	62	#define CONFIG_MPSC_PORT 0
	63
c609719b WD	64
	65	/* define this if you want to enable GT MAC filtering */
	66	#define CONFIG_GT_USE_MAC_HASH_TABLE
	67
	68	#undef CONFIG_ETHER_PORT_MII /* use RMII */
	69
	70	#if 1
	71	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	72	#else
	73	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	74	#endif
	75	#define CONFIG_ZERO_BOOTDELAY_CHECK
	76
	77	#undef CONFIG_BOOTARGS
	78	#define CONFIG_BOOTCOMMAND \
53677ef1	79	"bootp && " \
c609719b WD	80	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
	81	"ip=$ipaddr:$serverip:$gatewayip:" \
	82	"$netmask:$hostname:eth0:none; && " \
	83	"bootm"
	84
	85	#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
6d0f6bcf	86	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
c609719b WD	87
	88	#undef CONFIG_WATCHDOG /* watchdog disabled */
	89	#undef CONFIG_ALTIVEC /* undef to disable */
	90
5d2ebe1b JL	91	/*
	92	* BOOTP options
	93	*/
	94	#define CONFIG_BOOTP_SUBNETMASK
	95	#define CONFIG_BOOTP_GATEWAY
	96	#define CONFIG_BOOTP_HOSTNAME
	97	#define CONFIG_BOOTP_BOOTPATH
	98	#define CONFIG_BOOTP_BOOTFILESIZE
c609719b WD	99
c609719b WD	100
dcaa7156 JL	101	/*
	102	* Command line configuration.
	103	*/
	104	#include <config_cmd_default.h>
	105
	106	#define CONFIG_CMD_ASKENV
c609719b	107
c609719b WD	108
	109	/*
	110	* Miscellaneous configurable options
	111	*/
6d0f6bcf JCPV	112	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	113	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
dcaa7156	114	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	115	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	116	#else
6d0f6bcf	117	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b	118	#endif
6d0f6bcf JCPV	119	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	120	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	121	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c609719b	122
6d0f6bcf JCPV	123	#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
6d0f6bcf JCPV	124	#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
c609719b	125
6d0f6bcf	126	#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
c609719b	127
6d0f6bcf	128	#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
ee80fa7b	129	#define CONFIG_SYS_BUS_CLK 100000000 /* 100 MHz */
c609719b	130
6d0f6bcf	131	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
c609719b WD	132
	133	#ifdef CONFIG_EVB64260_750CX
	134	#define CONFIG_750CX
6d0f6bcf	135	#define CONFIG_SYS_BROKEN_CL2
c609719b WD	136	#endif
	137
	138	/*
	139	* Low Level Configuration Settings
	140	* (address mappings, register initial values, etc.)
	141	* You should know what you are doing if you make changes here.
	142	*/
	143
	144	/*-----------------------------------------------------------------------
	145	* Definitions for initial stack pointer and data area
	146	*/
6d0f6bcf	147	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982	148	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	149	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	150	#define CONFIG_SYS_INIT_RAM_LOCK
c609719b WD	151
	152
	153	/*-----------------------------------------------------------------------
	154	* Start addresses for the final memory configuration
	155	* (Set up by the startup code)
6d0f6bcf	156	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	157	*/
6d0f6bcf JCPV	158	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	159	#define CONFIG_SYS_FLASH_BASE 0xfff00000
	160	#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
	161	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	162	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	163	#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
c609719b WD	164
c609719b WD	165	/* areas to map different things with the GT in physical space */
6d0f6bcf JCPV	166	#define CONFIG_SYS_DRAM_BANKS 4
6d0f6bcf JCPV	167	#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
c609719b WD	168
c609719b WD	169	/* What to put in the bats. */
6d0f6bcf	170	#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
c609719b WD	171
c609719b WD	172	/* Peripheral Device section */
6d0f6bcf JCPV	173	#define CONFIG_SYS_GT_REGS 0xf8000000
	174	#define CONFIG_SYS_DEV_BASE 0xfc000000
	175
	176	#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
	177	#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
	178	#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
	179	#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
	180
	181	#define CONFIG_SYS_DEV0_SIZE _8M /* evb64260 sram @ 0xfc00.0000 */
	182	#define CONFIG_SYS_DEV1_SIZE _8M /* evb64260 rtc @ 0xfc80.0000 */
	183	#define CONFIG_SYS_DEV2_SIZE _16M /* evb64260 duart @ 0xfd00.0000 */
	184	#define CONFIG_SYS_DEV3_SIZE _16M /* evb64260 flash @ 0xfe00.0000 */
	185
	186	#define CONFIG_SYS_DEV0_PAR 0x20205093
	187	#define CONFIG_SYS_DEV1_PAR 0xcfcfffff
	188	#define CONFIG_SYS_DEV2_PAR 0xc0059bd4
	189	#define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c
	190	#define CONFIG_SYS_32BIT_BOOT_PAR 0xc4a8241c
8bde7f77 WD	191	/* c 4 a 8 2 4 1 c */
	192	/* 33 22\|2222\|22 22\|111 1\|11 11\|1 1 \| \| */
	193	/* 10 98\|7654\|32 10\|987 6\|54 32\|1 098\|7 654\|3 210 */
	194	/* 11\|00\|0100\|10 10\|100\|0 00\|10 0\|100 0\|001 1\|100 */
	195	/* 3\| 0\|.... ..\| 2\| 4 \| 0 \| 4 \| 8 \| 3 \| 4 */
c609719b WD	196
c609719b WD	197	#if 0 /* Wrong?? NTL */
6d0f6bcf	198	#define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
c609719b WD	199	/* DMAAck[1:0] GNT0[1:0] */
c609719b WD	200	#else
6d0f6bcf	201	#define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
c609719b WD	202	/* REQ0[1:0] GNT0[1:0] */
c609719b WD	203	#endif
6d0f6bcf	204	#define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
c609719b WD	205	/* DMAReq[4] DMAAck[4] WDNMI WDE */
c609719b WD	206	#if 0 /* Wrong?? NTL */
6d0f6bcf	207	#define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
c609719b WD	208	/* DMAAck[1:0] GNT1[1:0] */
c609719b WD	209	#else
6d0f6bcf	210	#define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
c609719b WD	211	/* GPP[22] (RS232IntB or PCI1Int) */
	212	/* GPP[21] (RS323IntA) */
	213	/* BClkIn */
	214	/* REQ1[1:0] GNT1[1:0] */
	215	#endif
	216
	217	#if 0 /* Wrong?? NTL */
6d0f6bcf	218	# define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
c609719b WD	219	/* GPP[27:26] Int[1:0] */
c609719b WD	220	#else
6d0f6bcf	221	# define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
8bde7f77 WD	222	/* GPP[29] (PCI1Int) */
	223	/* BClkOut0 */
	224	/* GPP[27] (PCI0Int) */
	225	/* GPP[26] (RtcInt or PCI1Int) */
	226	/* CPUInt[25:24] */
c609719b WD	227	#endif
c609719b WD	228
6d0f6bcf	229	# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 /* 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
c609719b WD	230
c609719b WD	231	#if 0 /* Wrong?? - NTL */
6d0f6bcf	232	# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6
c609719b	233	#else
6d0f6bcf	234	# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
8bde7f77	235	/* gpp[29] */
c609719b	236	/* gpp[27:26] */
8bde7f77	237	/* gpp[22:21] */
c609719b	238
6d0f6bcf	239	# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
c609719b WD	240	/* idmas use buffer 1,1
	241	comm use buffer 0
	242	pci use buffer 1,1
	243	cpu use buffer 0
	244	normal load (see also ifdef HVL)
	245	standard SDRAM (see also ifdef REG)
	246	non staggered refresh */
	247	/* 31:26 25 23 20 19 18 16 */
	248	/* 110110 00 111 0 0 00 1 */
	249	/* refresh_count=0x200
	250	phisical interleaving disable
	251	virtual interleaving enable */
	252	/* 15 14 13:0 */
	253	/* 1 0 0x200 */
	254	#endif
	255
6d0f6bcf JCPV	256	#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
	257	#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
	258	#define CONFIG_SYS_INIT_CHAN1
	259	#define CONFIG_SYS_INIT_CHAN2
c609719b	260
6d0f6bcf	261	#define SRAM_BASE CONFIG_SYS_DEV0_SPACE
c609719b WD	262	#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
	263
	264
	265	/*-----------------------------------------------------------------------
	266	* PCI stuff
	267	*-----------------------------------------------------------------------
	268	*/
	269
	270	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	271	#define PCI_HOST_FORCE 1 /* configure as pci host */
	272	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	273
	274	#define CONFIG_PCI /* include pci support */
	275	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	276	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	277
	278	/* PCI MEMORY MAP section */
6d0f6bcf JCPV	279	#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
	280	#define CONFIG_SYS_PCI0_MEM_SIZE _128M
	281	#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
	282	#define CONFIG_SYS_PCI1_MEM_SIZE _128M
c609719b	283
6d0f6bcf JCPV	284	#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
6d0f6bcf JCPV	285	#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
c609719b WD	286
c609719b WD	287
c609719b	288	/* PCI I/O MAP section */
6d0f6bcf JCPV	289	#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
	290	#define CONFIG_SYS_PCI0_IO_SIZE _16M
	291	#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
	292	#define CONFIG_SYS_PCI1_IO_SIZE _16M
c609719b	293
6d0f6bcf JCPV	294	#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
	295	#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
	296	#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
	297	#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
c609719b WD	298
	299	/*
	300	* NS16550 Configuration
	301	*/
6d0f6bcf	302	#define CONFIG_SYS_NS16550
c609719b	303
6d0f6bcf	304	#define CONFIG_SYS_NS16550_REG_SIZE -4
c609719b	305
6d0f6bcf	306	#define CONFIG_SYS_NS16550_CLK 3686400
c609719b	307
6d0f6bcf JCPV	308	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_DUART_IO + 0)
6d0f6bcf JCPV	309	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_DUART_IO + 0x20)
c609719b WD	310
	311	/*----------------------------------------------------------------------
	312	* Initial BAT mappings
	313	*/
	314
	315	/* NOTES:
	316	* 1) GUARDED and WRITE_THRU not allowed in IBATS
	317	* 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
	318	*/
	319
	320	/* SDRAM */
6d0f6bcf JCPV	321	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| BATL_CACHEINHIBIT)
	322	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	323	#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	324	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
c609719b WD	325
c609719b WD	326	/* init ram */
6d0f6bcf JCPV	327	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW \| BATL_MEMCOHERENCE)
	328	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	329	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	330	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
c609719b WD	331
c609719b WD	332	/* PCI0, PCI1 in one BAT */
6d0f6bcf JCPV	333	#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
	334	#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
	335	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE \| BATL_CACHEINHIBIT \| BATL_PP_RW \| BATL_GUARDEDSTORAGE)
	336	#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b WD	337
c609719b WD	338	/* GT regs, bootrom, all the devices, PCI I/O */
6d0f6bcf JCPV	339	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE \| BATL_CACHEINHIBIT \| BATL_PP_RW)
	340	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE \| BATU_VS \| BATU_VP \| BATU_BL_256M)
	341	#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE \| BATL_CACHEINHIBIT \| BATL_PP_RW \| BATL_GUARDEDSTORAGE)
	342	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
c609719b WD	343
c609719b WD	344	/* I2C speed and slave address (for compatability) defaults */
6d0f6bcf JCPV	345	#define CONFIG_SYS_I2C_SPEED 400000
6d0f6bcf JCPV	346	#define CONFIG_SYS_I2C_SLAVE 0x7F
c609719b WD	347
	348	/* I2C addresses for the two DIMM SPD chips */
	349	#ifndef CONFIG_EVB64260_750CX
	350	#define DIMM0_I2C_ADDR 0x56
	351	#define DIMM1_I2C_ADDR 0x54
	352	#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
	353	#define DIMM0_I2C_ADDR 0x54
	354	#define DIMM1_I2C_ADDR 0x54
	355	#endif
	356
	357	/*
	358	* For booting Linux, the board info and command line data
	359	* have to be in the first 8 MB of memory, since this is
	360	* the maximum mapped by the Linux kernel during initialization.
	361	*/
6d0f6bcf	362	#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
c609719b WD	363
	364	/*-----------------------------------------------------------------------
	365	* FLASH organization
	366	*/
6d0f6bcf JCPV	367	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	368	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
c609719b	369
6d0f6bcf JCPV	370	#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
6d0f6bcf JCPV	371	#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */
c609719b	372
6d0f6bcf JCPV	373	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	374	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	375	#define CONFIG_SYS_FLASH_CFI 1
c609719b	376
5a1aceb0	377	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	378	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
0e8d1586 JCPV	379	#define CONFIG_ENV_SECT_SIZE 0x10000
6d0f6bcf	380	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
c609719b WD	381
	382	/*-----------------------------------------------------------------------
	383	* Cache Configuration
	384	*/
6d0f6bcf	385	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
dcaa7156	386	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	387	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
c609719b WD	388	#endif
	389
	390	/*-----------------------------------------------------------------------
	391	* L2CR setup -- make sure this is right for your board!
1d0350ed	392	* look in include/74xx_7xx.h for the defines used here
c609719b WD	393	*/
c609719b WD	394
6d0f6bcf	395	#define CONFIG_SYS_L2
c609719b WD	396
c609719b WD	397	#ifdef CONFIG_750CX
53677ef1	398	#define L2_INIT 0
c609719b	399	#else
53677ef1 WD	400	#define L2_INIT (L2CR_L2SIZ_2M \| L2CR_L2CLK_3 \| L2CR_L2RAM_BURST \| \
53677ef1 WD	401	L2CR_L2OH_5 \| L2CR_L2CTL \| L2CR_L2WT)
c609719b WD	402	#endif
	403
	404	#define L2_ENABLE (L2_INIT \| L2CR_L2E)
	405
6d0f6bcf	406	#define CONFIG_SYS_BOARD_ASM_INIT 1
c609719b WD	407
	408
	409	#endif /* __CONFIG_H */