projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c609719b WD |
1 | /* |
| 2 | * (C) Copyright 2001 | |
| 3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 31 | #include <asm/processor.h> | |
| 32 | ||
| 33 | #ifndef __ASSEMBLY__ | |
| 34 | #include <galileo/core.h> | |
| 35 | #endif | |
| 36 | ||
| 37 | #include "../board/evb64260/local.h" | |
| 38 | ||
| 39 | /* | |
| 40 | * High Level Configuration Options | |
| 41 | * (easy to change) | |
| 42 | */ | |
| 43 | ||
| 44 | #define CONFIG_EVB64260 1 /* this is an EVB64260 board */ | |
| 45 | #define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ | |
| 46 | ||
| 47 | #define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ | |
| 48 | ||
| 49 | #undef CONFIG_ECC /* enable ECC support */ | |
| 50 | /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ | |
| 51 | ||
| 52 | /* which initialization functions to call for this board */ | |
| 53 | #define CONFIG_MISC_INIT_R 1 | |
| 54 | #define CONFIG_BOARD_PRE_INIT 1 | |
| 55 | ||
| 56 | #ifndef CONFIG_EVB64260_750CX | |
| 57 | #define CFG_BOARD_NAME "EVB64260" | |
| 58 | #else | |
| 59 | #define CFG_BOARD_NAME "EVB64260-750CX" | |
| 60 | #endif | |
| 61 | ||
| 62 | #define CFG_HUSH_PARSER | |
| 63 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| 64 | ||
| 65 | /* | |
| 66 | * The following defines let you select what serial you want to use | |
| 67 | * for your console driver. | |
| 68 | * | |
| 69 | * what to do: | |
| 70 | * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial | |
| 71 | * cable onto the second DUART channel, change the CFG_DUART port from 1 | |
| 72 | * to 0 below. | |
| 73 | * | |
| 74 | * to use the MPSC, #define CONFIG_MPSC. If you have wired up another | |
| 75 | * mpsc channel, change CONFIG_MPSC_PORT to the desired value. | |
| 76 | */ | |
| 77 | #define CONFIG_MPSC | |
| 78 | #define CONFIG_MPSC_PORT 0 | |
| 79 | ||
| 80 | #define CONFIG_NET_MULTI /* attempt all available adapters */ | |
| 81 | ||
| 82 | /* define this if you want to enable GT MAC filtering */ | |
| 83 | #define CONFIG_GT_USE_MAC_HASH_TABLE | |
| 84 | ||
| 85 | #undef CONFIG_ETHER_PORT_MII /* use RMII */ | |
| 86 | ||
| 87 | #if 1 | |
| 88 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
| 89 | #else | |
| 90 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 91 | #endif | |
| 92 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
| 93 | ||
| 94 | #undef CONFIG_BOOTARGS | |
| 95 | #define CONFIG_BOOTCOMMAND \ | |
| 96 | "bootp && " \ | |
| 97 | "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ | |
| 98 | "ip=$ipaddr:$serverip:$gatewayip:" \ | |
| 99 | "$netmask:$hostname:eth0:none; && " \ | |
| 100 | "bootm" | |
| 101 | ||
| 102 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ | |
| 103 | #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ | |
| 104 | ||
| 105 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 106 | #undef CONFIG_ALTIVEC /* undef to disable */ | |
| 107 | ||
| 108 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ | |
| 109 | CONFIG_BOOTP_BOOTFILESIZE) | |
| 110 | ||
| 111 | ||
| 112 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV) | |
| 113 | ||
| 114 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
| 115 | #include <cmd_confdefs.h> | |
| 116 | ||
| 117 | /* | |
| 118 | * Miscellaneous configurable options | |
| 119 | */ | |
| 120 | #define CFG_LONGHELP /* undef to save memory */ | |
| 121 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 122 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 123 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 124 | #else | |
| 125 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 126 | #endif | |
| 127 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 128 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 129 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 130 | ||
| 131 | #define CFG_MEMTEST_START 0x00400000 /* memtest works on */ | |
| 132 | #define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ | |
| 133 | ||
| 134 | #define CFG_LOAD_ADDR 0x00300000 /* default load address */ | |
| 135 | ||
| 136 | #define CFG_HZ 1000 /* decr freq: 1ms ticks */ | |
| 137 | #define CFG_BUS_HZ 100000000 /* 100 MHz */ | |
| 138 | #define CFG_BUS_CLK CFG_BUS_HZ | |
| 139 | ||
| 140 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
| 141 | ||
| 142 | #ifdef CONFIG_EVB64260_750CX | |
| 143 | #define CONFIG_750CX | |
| 144 | #define CFG_BROKEN_CL2 | |
| 145 | #endif | |
| 146 | ||
| 147 | /* | |
| 148 | * Low Level Configuration Settings | |
| 149 | * (address mappings, register initial values, etc.) | |
| 150 | * You should know what you are doing if you make changes here. | |
| 151 | */ | |
| 152 | ||
| 153 | /*----------------------------------------------------------------------- | |
| 154 | * Definitions for initial stack pointer and data area | |
| 155 | */ | |
| 156 | #define CFG_INIT_RAM_ADDR 0x40000000 | |
| 157 | #define CFG_INIT_RAM_END 0x1000 | |
| 158 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ | |
| 159 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 160 | #define CFG_INIT_RAM_LOCK | |
| 161 | ||
| 162 | ||
| 163 | /*----------------------------------------------------------------------- | |
| 164 | * Start addresses for the final memory configuration | |
| 165 | * (Set up by the startup code) | |
| 166 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 167 | */ | |
| 168 | #define CFG_SDRAM_BASE 0x00000000 | |
| 169 | #define CFG_FLASH_BASE 0xfff00000 | |
| 170 | #define CFG_RESET_ADDRESS 0xfff00100 | |
| 171 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 172 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
| 173 | #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ | |
| 174 | ||
| 175 | /* areas to map different things with the GT in physical space */ | |
| 176 | #define CFG_DRAM_BANKS 4 | |
| 177 | #define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ | |
| 178 | ||
| 179 | /* What to put in the bats. */ | |
| 180 | #define CFG_MISC_REGION_BASE 0xf0000000 | |
| 181 | ||
| 182 | /* Peripheral Device section */ | |
| 183 | #define CFG_GT_REGS 0xf8000000 | |
| 184 | #define CFG_DEV_BASE 0xfc000000 | |
| 185 | ||
| 186 | #define CFG_DEV0_SPACE CFG_DEV_BASE | |
| 187 | #define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) | |
| 188 | #define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) | |
| 189 | #define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) | |
| 190 | ||
| 191 | #define CFG_DEV0_SIZE _8M /* evb64260 sram @ 0xfc00.0000 */ | |
| 192 | #define CFG_DEV1_SIZE _8M /* evb64260 rtc @ 0xfc80.0000 */ | |
| 193 | #define CFG_DEV2_SIZE _16M /* evb64260 duart @ 0xfd00.0000 */ | |
| 194 | #define CFG_DEV3_SIZE _16M /* evb64260 flash @ 0xfe00.0000 */ | |
| 195 | ||
| 196 | #define CFG_DEV0_PAR 0x20205093 | |
| 197 | #define CFG_DEV1_PAR 0xcfcfffff | |
| 198 | #define CFG_DEV2_PAR 0xc0059bd4 | |
| 199 | #define CFG_8BIT_BOOT_PAR 0xc00b5e7c | |
| 200 | #define CFG_32BIT_BOOT_PAR 0xc4a8241c | |
| 8bde7f77 WD |
201 | /* c 4 a 8 2 4 1 c */ |
| 202 | /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ | |
| 203 | /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ | |
| 204 | /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ | |
| 205 | /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ | |
| c609719b WD |
206 | |
| 207 | #if 0 /* Wrong?? NTL */ | |
| 208 | #define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ | |
| 209 | /* DMAAck[1:0] GNT0[1:0] */ | |
| 210 | #else | |
| 211 | #define CFG_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ | |
| 212 | /* REQ0[1:0] GNT0[1:0] */ | |
| 213 | #endif | |
| 214 | #define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ | |
| 215 | /* DMAReq[4] DMAAck[4] WDNMI WDE */ | |
| 216 | #if 0 /* Wrong?? NTL */ | |
| 217 | #define CFG_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ | |
| 218 | /* DMAAck[1:0] GNT1[1:0] */ | |
| 219 | #else | |
| 220 | #define CFG_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ | |
| 221 | /* GPP[22] (RS232IntB or PCI1Int) */ | |
| 222 | /* GPP[21] (RS323IntA) */ | |
| 223 | /* BClkIn */ | |
| 224 | /* REQ1[1:0] GNT1[1:0] */ | |
| 225 | #endif | |
| 226 | ||
| 227 | #if 0 /* Wrong?? NTL */ | |
| 228 | # define CFG_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ | |
| 229 | /* GPP[27:26] Int[1:0] */ | |
| 230 | #else | |
| 231 | # define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ | |
| 8bde7f77 WD |
232 | /* GPP[29] (PCI1Int) */ |
| 233 | /* BClkOut0 */ | |
| 234 | /* GPP[27] (PCI0Int) */ | |
| 235 | /* GPP[26] (RtcInt or PCI1Int) */ | |
| 236 | /* CPUInt[25:24] */ | |
| c609719b WD |
237 | #endif |
| 238 | ||
| 239 | # define CFG_SERIAL_PORT_MUX 0x00000102 /* 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ | |
| 240 | ||
| 241 | #if 0 /* Wrong?? - NTL */ | |
| 242 | # define CFG_GPP_LEVEL_CONTROL 0x000002c6 | |
| 243 | #else | |
| 244 | # define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ | |
| 8bde7f77 | 245 | /* gpp[29] */ |
| c609719b | 246 | /* gpp[27:26] */ |
| 8bde7f77 | 247 | /* gpp[22:21] */ |
| c609719b WD |
248 | |
| 249 | # define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ | |
| 250 | /* idmas use buffer 1,1 | |
| 251 | comm use buffer 0 | |
| 252 | pci use buffer 1,1 | |
| 253 | cpu use buffer 0 | |
| 254 | normal load (see also ifdef HVL) | |
| 255 | standard SDRAM (see also ifdef REG) | |
| 256 | non staggered refresh */ | |
| 257 | /* 31:26 25 23 20 19 18 16 */ | |
| 258 | /* 110110 00 111 0 0 00 1 */ | |
| 259 | /* refresh_count=0x200 | |
| 260 | phisical interleaving disable | |
| 261 | virtual interleaving enable */ | |
| 262 | /* 15 14 13:0 */ | |
| 263 | /* 1 0 0x200 */ | |
| 264 | #endif | |
| 265 | ||
| 266 | #define CFG_DUART_IO CFG_DEV2_SPACE | |
| 267 | #define CFG_DUART_CHAN 1 /* channel to use for console */ | |
| 268 | #define CFG_INIT_CHAN1 | |
| 269 | #define CFG_INIT_CHAN2 | |
| 270 | ||
| 271 | #define SRAM_BASE CFG_DEV0_SPACE | |
| 272 | #define SRAM_SIZE 0x00100000 /* 1 MB of sram */ | |
| 273 | ||
| 274 | ||
| 275 | /*----------------------------------------------------------------------- | |
| 276 | * PCI stuff | |
| 277 | *----------------------------------------------------------------------- | |
| 278 | */ | |
| 279 | ||
| 280 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ | |
| 281 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
| 282 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
| 283 | ||
| 284 | #define CONFIG_PCI /* include pci support */ | |
| 285 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
| 286 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 287 | ||
| 288 | /* PCI MEMORY MAP section */ | |
| 289 | #define CFG_PCI0_MEM_BASE 0x80000000 | |
| 290 | #define CFG_PCI0_MEM_SIZE _128M | |
| 291 | #define CFG_PCI1_MEM_BASE 0x88000000 | |
| 292 | #define CFG_PCI1_MEM_SIZE _128M | |
| 293 | ||
| 294 | #define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) | |
| 295 | #define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) | |
| 296 | ||
| 297 | ||
| c609719b WD |
298 | /* PCI I/O MAP section */ |
| 299 | #define CFG_PCI0_IO_BASE 0xfa000000 | |
| 300 | #define CFG_PCI0_IO_SIZE _16M | |
| 301 | #define CFG_PCI1_IO_BASE 0xfb000000 | |
| 302 | #define CFG_PCI1_IO_SIZE _16M | |
| 303 | ||
| 304 | #define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) | |
| 305 | #define CFG_PCI0_IO_SPACE_PCI 0x00000000 | |
| 306 | #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) | |
| 307 | #define CFG_PCI1_IO_SPACE_PCI 0x00000000 | |
| 308 | ||
| 309 | /* | |
| 310 | * NS16550 Configuration | |
| 311 | */ | |
| 312 | #define CFG_NS16550 | |
| 313 | ||
| 314 | #define CFG_NS16550_REG_SIZE -4 | |
| 315 | ||
| 316 | #define CFG_NS16550_CLK 3686400 | |
| 317 | ||
| 318 | #define CFG_NS16550_COM1 (CFG_DUART_IO + 0) | |
| 319 | #define CFG_NS16550_COM2 (CFG_DUART_IO + 0x20) | |
| 320 | ||
| 321 | /*---------------------------------------------------------------------- | |
| 322 | * Initial BAT mappings | |
| 323 | */ | |
| 324 | ||
| 325 | /* NOTES: | |
| 326 | * 1) GUARDED and WRITE_THRU not allowed in IBATS | |
| 327 | * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT | |
| 328 | */ | |
| 329 | ||
| 330 | /* SDRAM */ | |
| 331 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 332 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 333 | #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 334 | #define CFG_DBAT0U CFG_IBAT0U | |
| 335 | ||
| 336 | /* init ram */ | |
| 337 | #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 338 | #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 339 | #define CFG_DBAT1L CFG_IBAT1L | |
| 340 | #define CFG_DBAT1U CFG_IBAT1U | |
| 341 | ||
| 342 | /* PCI0, PCI1 in one BAT */ | |
| 343 | #define CFG_IBAT2L BATL_NO_ACCESS | |
| 344 | #define CFG_IBAT2U CFG_DBAT2U | |
| 345 | #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
| 346 | #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 347 | ||
| 348 | /* GT regs, bootrom, all the devices, PCI I/O */ | |
| 349 | #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) | |
| 350 | #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) | |
| 351 | #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
| 352 | #define CFG_DBAT3U CFG_IBAT3U | |
| 353 | ||
| 354 | /* I2C speed and slave address (for compatability) defaults */ | |
| 355 | #define CFG_I2C_SPEED 400000 | |
| 356 | #define CFG_I2C_SLAVE 0x7F | |
| 357 | ||
| 358 | /* I2C addresses for the two DIMM SPD chips */ | |
| 359 | #ifndef CONFIG_EVB64260_750CX | |
| 360 | #define DIMM0_I2C_ADDR 0x56 | |
| 361 | #define DIMM1_I2C_ADDR 0x54 | |
| 362 | #else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ | |
| 363 | #define DIMM0_I2C_ADDR 0x54 | |
| 364 | #define DIMM1_I2C_ADDR 0x54 | |
| 365 | #endif | |
| 366 | ||
| 367 | /* | |
| 368 | * For booting Linux, the board info and command line data | |
| 369 | * have to be in the first 8 MB of memory, since this is | |
| 370 | * the maximum mapped by the Linux kernel during initialization. | |
| 371 | */ | |
| 372 | #define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ | |
| 373 | ||
| 374 | /*----------------------------------------------------------------------- | |
| 375 | * FLASH organization | |
| 376 | */ | |
| 377 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
| 378 | #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ | |
| 379 | ||
| 380 | #define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ | |
| 381 | #define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ | |
| 382 | ||
| 383 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
| 384 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 385 | #define CFG_FLASH_CFI 1 | |
| 386 | ||
| 387 | #define CFG_ENV_IS_IN_FLASH 1 | |
| 388 | #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ | |
| 389 | #define CFG_ENV_SECT_SIZE 0x10000 | |
| 390 | #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) | |
| 391 | ||
| 392 | /*----------------------------------------------------------------------- | |
| 393 | * Cache Configuration | |
| 394 | */ | |
| 395 | #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ | |
| 396 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 397 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
| 398 | #endif | |
| 399 | ||
| 400 | /*----------------------------------------------------------------------- | |
| 401 | * L2CR setup -- make sure this is right for your board! | |
| 1d0350ed | 402 | * look in include/74xx_7xx.h for the defines used here |
| c609719b WD |
403 | */ |
| 404 | ||
| 405 | #define CFG_L2 | |
| 406 | ||
| 407 | #ifdef CONFIG_750CX | |
| 408 | #define L2_INIT 0 | |
| 409 | #else | |
| 410 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ | |
| 411 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) | |
| 412 | #endif | |
| 413 | ||
| 414 | #define L2_ENABLE (L2_INIT | L2CR_L2E) | |
| 415 | ||
| 416 | /* | |
| 417 | * Internal Definitions | |
| 418 | * | |
| 419 | * Boot Flags | |
| 420 | */ | |
| 421 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 422 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 423 | ||
| 424 | #define CFG_BOARD_ASM_INIT 1 | |
| 425 | ||
| 426 | ||
| 427 | #endif /* __CONFIG_H */ |