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d1cbe85b | 1 | /* |
c837dcb1 | 2 | * (C) Copyright 2000-2004 |
d1cbe85b WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
53677ef1 | 36 | #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ |
d1cbe85b WD |
37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
38 | #define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */ | |
39 | ||
c837dcb1 | 40 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
d1cbe85b WD |
41 | |
42 | #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ | |
43 | ||
44 | /* I2C configuration */ | |
45 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf JCPV |
46 | #define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed */ |
47 | #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ | |
d1cbe85b WD |
48 | |
49 | /* environment is in EEPROM */ | |
bb1f8b4f | 50 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
5a1aceb0 | 51 | #undef CONFIG_ENV_IS_IN_FLASH |
9314cee6 | 52 | #undef CONFIG_ENV_IS_IN_NVRAM |
d1cbe85b | 53 | |
bb1f8b4f | 54 | #ifdef CONFIG_ENV_IS_IN_EEPROM |
6d0f6bcf JCPV |
55 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 /* 1010110 */ |
56 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit internal addressing */ | |
57 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 /* ... and 1 bit in I2C address */ | |
58 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 4 bytes per page */ | |
59 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* write takes up to 40 msec */ | |
0e8d1586 JCPV |
60 | #define CONFIG_ENV_OFFSET 4 /* Offset of Environment Sector */ |
61 | #define CONFIG_ENV_SIZE 350 /* that is 350 bytes only! */ | |
d1cbe85b WD |
62 | #endif |
63 | ||
64 | #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ | |
65 | /* Explanation: | |
66 | autbooting is altogether disabled and cannot be | |
67 | enabled if CONFIG_BOOTDELAY is negative. | |
945af8d7 | 68 | If you want shorter bootdelay, then |
d1cbe85b WD |
69 | - "setenv bootdelay <delay>" to the proper value |
70 | */ | |
71 | ||
72 | #define CONFIG_BOOTCOMMAND "bootm 20400000 20800000" | |
73 | ||
74 | #define CONFIG_BOOTARGS "root=/dev/ram " \ | |
75 | "ramdisk_size=32768 " \ | |
76 | "console=ttyS0,115200 " \ | |
77 | "ram=128M debug" | |
78 | ||
79 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 80 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
d1cbe85b WD |
81 | |
82 | #define CONFIG_MII 1 /* MII PHY management */ | |
83 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
18cc7afd | 84 | #define CONFIG_NET_MULTI |
d1cbe85b | 85 | |
d1cbe85b | 86 | |
11799434 JL |
87 | /* |
88 | * BOOTP options | |
89 | */ | |
90 | #define CONFIG_BOOTP_BOOTFILESIZE | |
91 | #define CONFIG_BOOTP_BOOTPATH | |
96e21f86 | 92 | #define CONFIG_PPC4xx_EMAC |
11799434 JL |
93 | #define CONFIG_BOOTP_GATEWAY |
94 | #define CONFIG_BOOTP_HOSTNAME | |
95 | ||
96 | ||
dcaa7156 JL |
97 | /* |
98 | * Command line configuration. | |
99 | */ | |
100 | #include <config_cmd_default.h> | |
101 | ||
d1cbe85b WD |
102 | |
103 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
104 | ||
105 | /* | |
106 | * Miscellaneous configurable options | |
107 | */ | |
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
109 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
dcaa7156 | 110 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 111 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
d1cbe85b | 112 | #else |
6d0f6bcf | 113 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d1cbe85b | 114 | #endif |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
116 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
117 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
d1cbe85b | 118 | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
120 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
d1cbe85b WD |
121 | |
122 | /* UART configuration */ | |
6d0f6bcf | 123 | #define CONFIG_SYS_BASE_BAUD 691200 |
d1cbe85b WD |
124 | |
125 | /* Default baud rate */ | |
126 | #define CONFIG_BAUDRATE 115200 | |
945af8d7 | 127 | |
d1cbe85b | 128 | /* The following table includes the supported baudrates */ |
6d0f6bcf | 129 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
945af8d7 WD |
130 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
131 | 57600, 115200, 230400, 460800, 921600 } | |
d1cbe85b | 132 | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
134 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
d1cbe85b | 135 | |
6d0f6bcf | 136 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
d1cbe85b WD |
137 | |
138 | /*----------------------------------------------------------------------- | |
139 | * PCI stuff | |
140 | *----------------------------------------------------------------------- | |
141 | */ | |
142 | #undef CONFIG_PCI /* no pci support */ | |
143 | ||
144 | /*----------------------------------------------------------------------- | |
145 | * External peripheral base address | |
146 | *----------------------------------------------------------------------- | |
147 | */ | |
148 | #undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ | |
149 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
150 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ | |
151 | ||
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 |
153 | #define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 | |
154 | #define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 | |
d1cbe85b WD |
155 | |
156 | /*----------------------------------------------------------------------- | |
157 | * Start addresses for the final memory configuration | |
158 | * (Set up by the startup code) | |
6d0f6bcf | 159 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
d1cbe85b | 160 | */ |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
162 | #define CONFIG_SYS_FLASH0_BASE 0xFFF80000 | |
163 | #define CONFIG_SYS_FLASH0_SIZE 0x00080000 | |
164 | #define CONFIG_SYS_FLASH1_BASE 0x20000000 | |
165 | #define CONFIG_SYS_FLASH1_SIZE 0x02000000 | |
166 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE | |
167 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE | |
14d0a02a | 168 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ |
170 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
171 | ||
172 | #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH0_BASE | |
173 | #define CONFIG_SYS_RAMSTART | |
d1cbe85b WD |
174 | #endif |
175 | ||
176 | /* | |
177 | * For booting Linux, the board info and command line data | |
178 | * have to be in the first 8 MB of memory, since this is | |
179 | * the maximum mapped by the Linux kernel during initialization. | |
180 | */ | |
6d0f6bcf | 181 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
d1cbe85b WD |
182 | /*----------------------------------------------------------------------- |
183 | * FLASH organization | |
184 | */ | |
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_MAX_FLASH_BANKS 5 /* max number of memory banks */ |
186 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
d1cbe85b | 187 | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
189 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
d1cbe85b | 190 | |
5a1aceb0 | 191 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
192 | #define CONFIG_ENV_OFFSET 0x00060000 /* Offset of Environment Sector */ |
193 | #define CONFIG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */ | |
194 | #define CONFIG_ENV_SECT_SIZE 0x00010000 /* see README - env sector total size */ | |
d1cbe85b WD |
195 | #endif |
196 | ||
197 | /* On Chip Memory location/size */ | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
199 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
d1cbe85b WD |
200 | |
201 | /* Global info and initial stack */ | |
6d0f6bcf | 202 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */ |
553f0982 | 203 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
25ddd1fb | 204 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 205 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
d1cbe85b | 206 | |
dcaa7156 | 207 | #if defined(CONFIG_CMD_KGDB) |
d1cbe85b WD |
208 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
209 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
210 | #endif | |
211 | #endif /* __CONFIG_H */ |