[people/ms/u-boot.git] / include / configs / FADS850SAR.h

 /*
  * A collection of structures, addresses, and values associated with
  * the Motorola 860T FADS board.  Copied from the MBX stuff.
  * Magnus Damm added defines for 8xxrom and extended bd_info.
  * Helmut Buchsbaum added bitvalues for BCSRx
  *
  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
  */

/*
 * 1999-nov-26: The FADS is using the following physical memorymap:
 *
 * ff020000 -> ff02ffff : pcmcia
 * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxrom
 * ff000000 -> ff00ffff : IMAP       internal in the cpu
 * fe000000 -> ffnnnnnn : flash      connected to CS0, setup by 8xxrom
 * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC850		1
#define CONFIG_MPC850SAR	1
#define CONFIG_FADS			1

#define	CONFIG_SYS_TEXT_BASE	0xFE000000

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600

#if 0
#define MPC8XX_FACT	10				/* Multiply by 10		*/
#define MPC8XX_XIN	50000000		/* 50 MHz in	*/
#else
#define MPC8XX_FACT	12				/* Multiply by 12 */
#define MPC8XX_XIN	4000000			/* 4 MHz in */
#endif
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#if 1
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_BOOTCOMMAND	"bootm 02880000"	/* autoboot command */
#define CONFIG_BOOTARGS		" "

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


/*
 * Miscellaneous configurable options
 */
#undef	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT		":>"		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00800000	/* 0 ... 8 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR			0xFF000000
#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define	CONFIG_SYS_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
#define CONFIG_SYS_FLASH_BASE		0x02800000
#define CONFIG_SYS_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
#if 0
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 128 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
#define	CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control					11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration						11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control					11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer  *
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << 20) | \
				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR       (SCCR_TBS     | \
				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
				SCCR_DFALCD00)

 /*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER		0

/* Because of the way the 860 starts up and assigns CS0 the
* entire address space, we have to set the memory controller
* differently.  Normally, you write the option register
* first, and then enable the chip select by writing the
* base register.  For CS0, you must write the base register
* first, followed by the option register.
*/

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */
/* the other CS:s are determined by looking at parameters in BCSRx */


#define BCSR_ADDR		((uint) 0x02100000)
#define BCSR_SIZE		((uint)(64 * 1024))

#define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x00000000	/* FLASH bank #1	*/

#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */

/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

/* BCSRx - Board Control and Status Registers */
#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
#define CONFIG_SYS_BR1_PRELIM	((BCSR_ADDR) | BR_V )


/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA		97		/* start with divider for 100 MHz	*/

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

#define CONFIG_SYS_MAMR		0x13a01114

/* values according to the manual */


#define PCMCIA_MEM_ADDR		((uint)0xff020000)
#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))

#define	BCSR0			((uint) (BCSR_ADDR + 00))
#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
#define	BCSR4			((uint) (BCSR_ADDR + 0x10))

/* FADS bitvalues by Helmut Buchsbaum
 * see MPC8xxADS User's Manual for a proper description
 * of the following structures
 */

#define BCSR0_ERB       ((uint)0x80000000)
#define BCSR0_IP        ((uint)0x40000000)
#define BCSR0_BDIS      ((uint)0x10000000)
#define BCSR0_BPS_MASK  ((uint)0x0C000000)
#define BCSR0_ISB_MASK  ((uint)0x01800000)
#define BCSR0_DBGC_MASK ((uint)0x00600000)
#define BCSR0_DBPC_MASK ((uint)0x00180000)
#define BCSR0_EBDF_MASK ((uint)0x00060000)

#define BCSR1_FLASH_EN           ((uint)0x80000000)
#define BCSR1_DRAM_EN            ((uint)0x40000000)
#define BCSR1_ETHEN              ((uint)0x20000000)
#define BCSR1_IRDEN              ((uint)0x10000000)
#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
#define BCSR1_BCSR_EN            ((uint)0x02000000)
#define BCSR1_RS232EN_1          ((uint)0x01000000)
#define BCSR1_PCCEN              ((uint)0x00800000)
#define BCSR1_PCCVCC0            ((uint)0x00400000)
#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
#define BCSR1_RS232EN_2          ((uint)0x00040000)
#define BCSR1_SDRAM_EN           ((uint)0x00020000)
#define BCSR1_PCCVCC1            ((uint)0x00010000)

#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
#define BCSR2_FLASH_PD_SHIFT	 28
#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
#define BCSR2_DRAM_PD_SHIFT      23
#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)

#define BCSR3_DBID_MASK          ((ushort)0x3800)
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
#define BCSR3_BREVNR0            ((ushort)0x0080)
#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
#define BCSR3_BREVN1             ((ushort)0x0008)
#define BCSR3_BREVN2_MASK        ((ushort)0x0003)

#define BCSR4_ETHLOOP            ((uint)0x80000000)
#define BCSR4_TFPLDL             ((uint)0x40000000)
#define BCSR4_TPSQEL             ((uint)0x20000000)
#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
#ifdef CONFIG_MPC823
#define BCSR4_USB_EN             ((uint)0x08000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860SAR
#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
#endif /* CONFIG_MPC860SAR */
#ifdef CONFIG_MPC860T
#define BCSR4_FETH_EN            ((uint)0x08000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_USB_SPEED          ((uint)0x04000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG0           ((uint)0x04000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VCCO               ((uint)0x02000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHFDE            ((uint)0x02000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_ON           ((uint)0x00800000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG1           ((uint)0x00400000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_RST          ((uint)0x00200000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHRST            ((uint)0x00200000)
#endif /* CONFIG_MPC860T */
#define BCSR4_MODEM_EN           ((uint)0x00100000)
#define BCSR4_DATA_VOICE         ((uint)0x00080000)

#define CONFIG_DRAM_50MHZ		1
#define CONFIG_SDRAM_50MHZ

/* We don't use the 8259.
*/
#define NR_8259_INTS	0

#define CONFIG_DISK_SPINUP_TIME 1000000


/* PCMCIA configuration */

#define PCMCIA_MAX_SLOTS    2

#ifdef CONFIG_MPC860
#define PCMCIA_SLOT_A 1
#endif

#define CONFIG_SYS_DAUGHTERBOARD

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* A collection of structures, addresses, and values associated with
	3	* the Motorola 860T FADS board. Copied from the MBX stuff.
	4	* Magnus Damm added defines for 8xxrom and extended bd_info.
	5	* Helmut Buchsbaum added bitvalues for BCSRx
	6	*
	7	* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
	8	*/
	9
	10	/*
	11	* 1999-nov-26: The FADS is using the following physical memorymap:
	12	*
	13	* ff020000 -> ff02ffff : pcmcia
	14	* ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom
	15	* ff000000 -> ff00ffff : IMAP internal in the cpu
	16	* fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom
	17	* 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
	18	*/
	19
	20	/* ------------------------------------------------------------------------- */
	21
	22	/*
	23	* board/config.h - configuration options, board specific
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	/*
	30	* High Level Configuration Options
	31	* (easy to change)
	32	*/
0f8c9768 WD	33	#define CONFIG_MPC850 1
	34	#define CONFIG_MPC850SAR 1
	35	#define CONFIG_FADS 1
	36
2ae18241 WD	37	#define CONFIG_SYS_TEXT_BASE 0xFE000000
2ae18241 WD	38
0f8c9768 WD	39	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	40	#undef CONFIG_8xx_CONS_SMC2
	41	#undef CONFIG_8xx_CONS_NONE
	42	#define CONFIG_BAUDRATE 9600
	43
	44	#if 0
	45	#define MPC8XX_FACT 10 /* Multiply by 10 */
	46	#define MPC8XX_XIN 50000000 /* 50 MHz in */
	47	#else
	48	#define MPC8XX_FACT 12 /* Multiply by 12 */
	49	#define MPC8XX_XIN 4000000 /* 4 MHz in */
	50	#endif
	51	#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
	52
	53	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	54
	55	#if 1
	56	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	57	#else
	58	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	59	#endif
	60
	61	#define CONFIG_BOOTCOMMAND "bootm 02880000" /* autoboot command */
	62	#define CONFIG_BOOTARGS " "
	63
	64	#undef CONFIG_WATCHDOG /* watchdog disabled */
	65
60a0876b	66
11799434 JL	67	/*
	68	* BOOTP options
	69	*/
	70	#define CONFIG_BOOTP_BOOTFILESIZE
	71	#define CONFIG_BOOTP_BOOTPATH
	72	#define CONFIG_BOOTP_GATEWAY
	73	#define CONFIG_BOOTP_HOSTNAME
	74
	75
60a0876b JL	76	/*
	77	* Command line configuration.
	78	*/
	79	#include <config_cmd_default.h>
	80
0f8c9768 WD	81
	82	/*
	83	* Miscellaneous configurable options
	84	*/
6d0f6bcf JCPV	85	#undef CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	86	#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */
60a0876b	87	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	88	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0f8c9768	89	#else
6d0f6bcf	90	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0f8c9768	91	#endif
6d0f6bcf JCPV	92	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	93	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	94	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0f8c9768	95
6d0f6bcf JCPV	96	#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
6d0f6bcf JCPV	97	#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */
0f8c9768	98
6d0f6bcf	99	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
0f8c9768	100
6d0f6bcf	101	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
0f8c9768	102
0f8c9768 WD	103	/*
	104	* Low Level Configuration Settings
	105	* (address mappings, register initial values, etc.)
	106	* You should know what you are doing if you make changes here.
	107	*/
	108	/*-----------------------------------------------------------------------
	109	* Internal Memory Mapped Register
	110	*/
6d0f6bcf JCPV	111	#define CONFIG_SYS_IMMR 0xFF000000
6d0f6bcf JCPV	112	#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
0f8c9768 WD	113
	114	/*-----------------------------------------------------------------------
	115	* Definitions for initial stack pointer and data area (in DPRAM)
	116	*/
6d0f6bcf	117	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	118	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	119	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	120	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0f8c9768 WD	121
	122	/*-----------------------------------------------------------------------
	123	* Start addresses for the final memory configuration
	124	* (Set up by the startup code)
6d0f6bcf	125	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0f8c9768 WD	126	* Also NOTE that it doesn't mean SDRAM - it means MEMORY.
0f8c9768 WD	127	*/
6d0f6bcf JCPV	128	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	129	#define CONFIG_SYS_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
	130	#define CONFIG_SYS_FLASH_BASE 0x02800000
	131	#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
0f8c9768	132	#if 0
6d0f6bcf	133	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */
0f8c9768	134	#else
6d0f6bcf	135	#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
0f8c9768	136	#endif
6d0f6bcf JCPV	137	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	138	#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
0f8c9768 WD	139
	140	/*
	141	* For booting Linux, the board info and command line data
	142	* have to be in the first 8 MB of memory, since this is
	143	* the maximum mapped by the Linux kernel during initialization.
	144	*/
6d0f6bcf	145	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0f8c9768 WD	146	/*-----------------------------------------------------------------------
	147	* FLASH organization
	148	*/
6d0f6bcf JCPV	149	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	150	#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
0f8c9768	151
6d0f6bcf JCPV	152	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	153	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
0f8c9768	154
5a1aceb0	155	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	156	#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
0e8d1586 JCPV	157	#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
6d0f6bcf	158	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
0f8c9768 WD	159
	160	/*-----------------------------------------------------------------------
	161	* Cache Configuration
	162	*/
6d0f6bcf	163	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
60a0876b	164	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	165	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
0f8c9768 WD	166	#endif
	167
	168	/*-----------------------------------------------------------------------
	169	* SYPCR - System Protection Control 11-9
	170	* SYPCR can only be written once after reset!
	171	*-----------------------------------------------------------------------
	172	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	173	*/
	174	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	175	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
0f8c9768 WD	176	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
0f8c9768 WD	177	#else
6d0f6bcf	178	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
0f8c9768 WD	179	#endif
	180
	181	/*-----------------------------------------------------------------------
	182	* SIUMCR - SIU Module Configuration 11-6
	183	*-----------------------------------------------------------------------
	184	* PCMCIA config., multi-function pin tri-state
	185	*/
6d0f6bcf	186	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
0f8c9768 WD	187
	188	/*-----------------------------------------------------------------------
	189	* TBSCR - Time Base Status and Control 11-26
	190	*-----------------------------------------------------------------------
	191	* Clear Reference Interrupt Status, Timebase freezing enabled
	192	*/
6d0f6bcf	193	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
0f8c9768 WD	194
	195	/*-----------------------------------------------------------------------
	196	* PISCR - Periodic Interrupt Status and Control 11-31
	197	*-----------------------------------------------------------------------
	198	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	199	*/
6d0f6bcf	200	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
0f8c9768 WD	201
	202	/*-----------------------------------------------------------------------
	203	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	204	*-----------------------------------------------------------------------
	205	* Reset PLL lock status sticky bit, timer expired status bit and timer *
	206	* interrupt status bit - leave PLL multiplication factor unchanged !
	207	*/
6d0f6bcf	208	#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << 20) \| \
0f8c9768 WD	209	PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
	210
	211	/*-----------------------------------------------------------------------
	212	* SCCR - System Clock and reset Control Register 15-27
	213	*-----------------------------------------------------------------------
	214	* Set clock output, timebase and RTC source and divider,
	215	* power management and some other internal clocks
	216	*/
	217	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	218	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
0f8c9768 WD	219	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	220	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	221	SCCR_DFALCD00)
	222
	223	/*-----------------------------------------------------------------------
	224	*
	225	*-----------------------------------------------------------------------
	226	*
	227	*/
6d0f6bcf	228	#define CONFIG_SYS_DER 0
0f8c9768 WD	229
	230	/* Because of the way the 860 starts up and assigns CS0 the
	231	* entire address space, we have to set the memory controller
	232	* differently. Normally, you write the option register
	233	* first, and then enable the chip select by writing the
	234	* base register. For CS0, you must write the base register
	235	* first, followed by the option register.
	236	*/
	237
	238	/*
	239	* Init Memory Controller:
	240	*
	241	* BR0/1 and OR0/1 (FLASH)
	242	*/
	243	/* the other CS:s are determined by looking at parameters in BCSRx */
	244
	245
	246	#define BCSR_ADDR ((uint) 0x02100000)
	247	#define BCSR_SIZE ((uint)(64 * 1024))
	248
	249	#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
	250	#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
	251
6d0f6bcf JCPV	252	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	253	#define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
0f8c9768 WD	254
0f8c9768 WD	255	/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
6d0f6bcf	256	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV4 \| OR_BI \| OR_SCY_3_CLK \| OR_TRLX)
0f8c9768	257
6d0f6bcf JCPV	258	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	259	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
	260	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
0f8c9768 WD	261
0f8c9768 WD	262	/* BCSRx - Board Control and Status Registers */
6d0f6bcf JCPV	263	#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
	264	#define CONFIG_SYS_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
	265	#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) \| BR_V )
0f8c9768 WD	266
	267
	268	/*
	269	* Memory Periodic Timer Prescaler
	270	*/
	271
	272	/* periodic timer for refresh */
6d0f6bcf	273	#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
0f8c9768 WD	274
0f8c9768 WD	275	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
6d0f6bcf JCPV	276	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	277	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
0f8c9768 WD	278
0f8c9768 WD	279	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	280	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	281	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
0f8c9768 WD	282
	283	/*
	284	* MAMR settings for SDRAM
	285	*/
	286
	287	/* 8 column SDRAM */
6d0f6bcf	288	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
0f8c9768 WD	289	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	290	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	291	/* 9 column SDRAM */
6d0f6bcf	292	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
0f8c9768 WD	293	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	294	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	295
6d0f6bcf	296	#define CONFIG_SYS_MAMR 0x13a01114
0f8c9768 WD	297
	298	/* values according to the manual */
	299
	300
	301	#define PCMCIA_MEM_ADDR ((uint)0xff020000)
	302	#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
	303
	304	#define BCSR0 ((uint) (BCSR_ADDR + 00))
	305	#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
	306	#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
	307	#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
	308	#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
	309
	310	/* FADS bitvalues by Helmut Buchsbaum
	311	* see MPC8xxADS User's Manual for a proper description
	312	* of the following structures
	313	*/
	314
	315	#define BCSR0_ERB ((uint)0x80000000)
	316	#define BCSR0_IP ((uint)0x40000000)
	317	#define BCSR0_BDIS ((uint)0x10000000)
	318	#define BCSR0_BPS_MASK ((uint)0x0C000000)
	319	#define BCSR0_ISB_MASK ((uint)0x01800000)
	320	#define BCSR0_DBGC_MASK ((uint)0x00600000)
	321	#define BCSR0_DBPC_MASK ((uint)0x00180000)
	322	#define BCSR0_EBDF_MASK ((uint)0x00060000)
	323
	324	#define BCSR1_FLASH_EN ((uint)0x80000000)
	325	#define BCSR1_DRAM_EN ((uint)0x40000000)
	326	#define BCSR1_ETHEN ((uint)0x20000000)
	327	#define BCSR1_IRDEN ((uint)0x10000000)
	328	#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
	329	#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
	330	#define BCSR1_BCSR_EN ((uint)0x02000000)
	331	#define BCSR1_RS232EN_1 ((uint)0x01000000)
	332	#define BCSR1_PCCEN ((uint)0x00800000)
	333	#define BCSR1_PCCVCC0 ((uint)0x00400000)
	334	#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
	335	#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
	336	#define BCSR1_RS232EN_2 ((uint)0x00040000)
	337	#define BCSR1_SDRAM_EN ((uint)0x00020000)
	338	#define BCSR1_PCCVCC1 ((uint)0x00010000)
	339
	340	#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
b54d32b4	341	#define BCSR2_FLASH_PD_SHIFT 28
0f8c9768	342	#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
b54d32b4	343	#define BCSR2_DRAM_PD_SHIFT 23
0f8c9768 WD	344	#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
	345	#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
	346
	347	#define BCSR3_DBID_MASK ((ushort)0x3800)
	348	#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
	349	#define BCSR3_BREVNR0 ((ushort)0x0080)
	350	#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
	351	#define BCSR3_BREVN1 ((ushort)0x0008)
	352	#define BCSR3_BREVN2_MASK ((ushort)0x0003)
	353
	354	#define BCSR4_ETHLOOP ((uint)0x80000000)
	355	#define BCSR4_TFPLDL ((uint)0x40000000)
	356	#define BCSR4_TPSQEL ((uint)0x20000000)
	357	#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
	358	#ifdef CONFIG_MPC823
	359	#define BCSR4_USB_EN ((uint)0x08000000)
	360	#endif /* CONFIG_MPC823 */
	361	#ifdef CONFIG_MPC860SAR
	362	#define BCSR4_UTOPIA_EN ((uint)0x08000000)
	363	#endif /* CONFIG_MPC860SAR */
	364	#ifdef CONFIG_MPC860T
	365	#define BCSR4_FETH_EN ((uint)0x08000000)
	366	#endif /* CONFIG_MPC860T */
	367	#ifdef CONFIG_MPC823
	368	#define BCSR4_USB_SPEED ((uint)0x04000000)
	369	#endif /* CONFIG_MPC823 */
	370	#ifdef CONFIG_MPC860T
	371	#define BCSR4_FETHCFG0 ((uint)0x04000000)
	372	#endif /* CONFIG_MPC860T */
	373	#ifdef CONFIG_MPC823
	374	#define BCSR4_VCCO ((uint)0x02000000)
	375	#endif /* CONFIG_MPC823 */
	376	#ifdef CONFIG_MPC860T
	377	#define BCSR4_FETHFDE ((uint)0x02000000)
	378	#endif /* CONFIG_MPC860T */
	379	#ifdef CONFIG_MPC823
	380	#define BCSR4_VIDEO_ON ((uint)0x00800000)
	381	#endif /* CONFIG_MPC823 */
	382	#ifdef CONFIG_MPC823
	383	#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
	384	#endif /* CONFIG_MPC823 */
	385	#ifdef CONFIG_MPC860T
	386	#define BCSR4_FETHCFG1 ((uint)0x00400000)
	387	#endif /* CONFIG_MPC860T */
	388	#ifdef CONFIG_MPC823
	389	#define BCSR4_VIDEO_RST ((uint)0x00200000)
	390	#endif /* CONFIG_MPC823 */
	391	#ifdef CONFIG_MPC860T
	392	#define BCSR4_FETHRST ((uint)0x00200000)
	393	#endif /* CONFIG_MPC860T */
	394	#define BCSR4_MODEM_EN ((uint)0x00100000)
	395	#define BCSR4_DATA_VOICE ((uint)0x00080000)
	396
	397	#define CONFIG_DRAM_50MHZ 1
	398	#define CONFIG_SDRAM_50MHZ
	399
0f8c9768 WD	400	/* We don't use the 8259.
	401	*/
	402	#define NR_8259_INTS 0
	403
0f8c9768 WD	404	#define CONFIG_DISK_SPINUP_TIME 1000000
	405
	406
	407	/* PCMCIA configuration */
	408
	409	#define PCMCIA_MAX_SLOTS 2
	410
	411	#ifdef CONFIG_MPC860
	412	#define PCMCIA_SLOT_A 1
	413	#endif
	414
6d0f6bcf	415	#define CONFIG_SYS_DAUGHTERBOARD
180d3f74	416
0f8c9768	417	#endif /* __CONFIG_H */