[people/ms/u-boot.git] / include / configs / FPS850L.h

/*
 * (C) Copyright 2000-2008
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
#define CONFIG_FPS850L		1	/* ...on a FingerPrint Sensor	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
#define CONFIG_SYS_SMC_RXBUFLEN	128
#define CONFIG_SYS_MAXIDLE	10
#define CONFIG_BAUDRATE		115200

#define	CONFIG_BOOTCOUNT_LIMIT

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_8xx\0"					\
	"hostname=FPS850L\0"						\
	"bootfile=FPS850L/uImage\0"					\
	"fdt_addr=40040000\0"						\
	"kernel_addr=40060000\0"					\
	"ramdisk_addr=40200000\0"					\
	"u-boot=FPS850L/u-image.bin\0"					\
	"load=tftp 200000 ${u-boot}\0"					\
	"update=prot off 40000000 +${filesize};"			\
		"era 40000000 +${filesize};"				\
		"cp.b 200000 40000000 ${filesize};"			\
		"sete filesize;save\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_NISDOMAIN
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_TIMEOFFSET

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP


#define CONFIG_NETCONSOLE


/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CONFIG_SYS_HUSH_PARSER
#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */

/* use CFI flash driver */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */

/*-----------------------------------------------------------------------
 * Dynamic MTD partition support
 */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"

#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
						"128k(dtb),"		\
						"1664k(kernel),"	\
						"2m(rootfs),"		\
						"4m(data)"

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_3_CLK | OR_EHTR | OR_BI)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */

#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
#define CONFIG_SYS_MAMR_PTA	98

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1
#define CONFIG_HWCONFIG		1

#endif	/* __CONFIG_H */
Commit	Line	Data
75dc29eb	1	/*
29f8f58f	2	* (C) Copyright 2000-2008
75dc29eb WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
	37	#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */
	38
2ae18241 WD	39	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	40
75dc29eb	41	#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
3cb7a480 WD	42	#define CONFIG_SYS_SMC_RXBUFLEN 128
3cb7a480 WD	43	#define CONFIG_SYS_MAXIDLE 10
eb6da805	44	#define CONFIG_BAUDRATE 115200
75dc29eb	45
eb6da805 WD	46	#define CONFIG_BOOTCOUNT_LIMIT
	47
	48	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
75dc29eb WD	49
	50	#define CONFIG_BOARD_TYPES 1 /* support board types */
	51
32bf3d14	52	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
eb6da805 WD	53
	54	#undef CONFIG_BOOTARGS
	55
	56	#define CONFIG_EXTRA_ENV_SETTINGS \
	57	"netdev=eth0\0" \
	58	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	59	"nfsroot=${serverip}:${rootpath}\0" \
	60	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	61	"addip=setenv bootargs ${bootargs} " \
	62	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	63	":${hostname}:${netdev}:off panic=1\0" \
	64	"flash_nfs=run nfsargs addip;" \
	65	"bootm ${kernel_addr}\0" \
	66	"flash_self=run ramargs addip;" \
	67	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	68	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
	69	"rootpath=/opt/eldk/ppc_8xx\0" \
29f8f58f WD	70	"hostname=FPS850L\0" \
29f8f58f WD	71	"bootfile=FPS850L/uImage\0" \
eb6da805 WD	72	"fdt_addr=40040000\0" \
	73	"kernel_addr=40060000\0" \
	74	"ramdisk_addr=40200000\0" \
29f8f58f WD	75	"u-boot=FPS850L/u-image.bin\0" \
	76	"load=tftp 200000 ${u-boot}\0" \
	77	"update=prot off 40000000 +${filesize};" \
	78	"era 40000000 +${filesize};" \
	79	"cp.b 200000 40000000 ${filesize};" \
	80	"sete filesize;save\0" \
eb6da805 WD	81	""
eb6da805 WD	82	#define CONFIG_BOOTCOMMAND "run flash_self"
75dc29eb WD	83
75dc29eb WD	84	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	85	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
75dc29eb WD	86
	87	#undef CONFIG_WATCHDOG /* watchdog disabled */
	88
5d2ebe1b JL	89	/*
	90	* BOOTP options
	91	*/
	92	#define CONFIG_BOOTP_SUBNETMASK
	93	#define CONFIG_BOOTP_GATEWAY
	94	#define CONFIG_BOOTP_HOSTNAME
	95	#define CONFIG_BOOTP_BOOTPATH
	96	#define CONFIG_BOOTP_BOOTFILESIZE
	97	#define CONFIG_BOOTP_SUBNETMASK
	98	#define CONFIG_BOOTP_GATEWAY
	99	#define CONFIG_BOOTP_HOSTNAME
	100	#define CONFIG_BOOTP_NISDOMAIN
	101	#define CONFIG_BOOTP_BOOTPATH
	102	#define CONFIG_BOOTP_DNS
	103	#define CONFIG_BOOTP_DNS2
	104	#define CONFIG_BOOTP_SEND_HOSTNAME
	105	#define CONFIG_BOOTP_NTPSERVER
	106	#define CONFIG_BOOTP_TIMEOFFSET
75dc29eb	107
eb6da805	108	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
75dc29eb	109
60a0876b JL	110	/*
	111	* Command line configuration.
	112	*/
	113	#include <config_cmd_default.h>
	114
eb6da805 WD	115	#define CONFIG_CMD_ASKENV
	116	#define CONFIG_CMD_DATE
	117	#define CONFIG_CMD_DHCP
29f8f58f	118	#define CONFIG_CMD_JFFS2
eb6da805 WD	119	#define CONFIG_CMD_NFS
eb6da805 WD	120	#define CONFIG_CMD_SNTP
60a0876b	121
75dc29eb	122
29f8f58f WD	123	#define CONFIG_NETCONSOLE
	124
	125
75dc29eb WD	126	/*
	127	* Miscellaneous configurable options
	128	*/
6d0f6bcf JCPV	129	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	130	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
eb6da805 WD	131
eb6da805 WD	132	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
6d0f6bcf JCPV	133	#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
	134	#ifdef CONFIG_SYS_HUSH_PARSER
	135	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
eb6da805 WD	136	#endif
eb6da805 WD	137
60a0876b	138	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	139	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
75dc29eb	140	#else
6d0f6bcf	141	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
75dc29eb	142	#endif
6d0f6bcf JCPV	143	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	144	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	145	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
75dc29eb	146
6d0f6bcf JCPV	147	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	148	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
75dc29eb	149
6d0f6bcf	150	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
75dc29eb	151
6d0f6bcf	152	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
75dc29eb	153
6d0f6bcf	154	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
75dc29eb WD	155
	156	/*
	157	* Low Level Configuration Settings
	158	* (address mappings, register initial values, etc.)
	159	* You should know what you are doing if you make changes here.
	160	*/
	161	/*-----------------------------------------------------------------------
	162	* Internal Memory Mapped Register
	163	*/
6d0f6bcf	164	#define CONFIG_SYS_IMMR 0xFFF00000
75dc29eb WD	165
	166	/*-----------------------------------------------------------------------
	167	* Definitions for initial stack pointer and data area (in DPRAM)
	168	*/
6d0f6bcf	169	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	170	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
6d0f6bcf	171	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
553f0982	172	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
6d0f6bcf	173	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
75dc29eb WD	174
	175	/*-----------------------------------------------------------------------
	176	* Start addresses for the final memory configuration
	177	* (Set up by the startup code)
6d0f6bcf	178	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
75dc29eb	179	*/
6d0f6bcf JCPV	180	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	181	#define CONFIG_SYS_FLASH_BASE 0x40000000
	182	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	183	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	184	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
75dc29eb WD	185
	186	/*
	187	* For booting Linux, the board info and command line data
	188	* have to be in the first 8 MB of memory, since this is
	189	* the maximum mapped by the Linux kernel during initialization.
	190	*/
6d0f6bcf	191	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
46a414dc	192
75dc29eb WD	193	/*-----------------------------------------------------------------------
	194	* FLASH organization
	195	*/
75dc29eb	196
29f8f58f	197	/* use CFI flash driver */
6d0f6bcf	198	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	199	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	200	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
	201	#define CONFIG_SYS_FLASH_EMPTY_INFO
	202	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	203	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	204	#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
75dc29eb	205
5a1aceb0	206	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	207	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586 JCPV	208	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
75dc29eb	209
46a414dc	210	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	211	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
0e8d1586 JCPV	212	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
46a414dc	213
6d0f6bcf	214	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
29f8f58f	215
7c803be2 WD	216	#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
7c803be2 WD	217
29f8f58f WD	218	/*-----------------------------------------------------------------------
	219	* Dynamic MTD partition support
	220	*/
68d7d651	221	#define CONFIG_CMD_MTDPARTS
942556a9 SR	222	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	223	#define CONFIG_FLASH_CFI_MTD
29f8f58f WD	224	#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
	225
	226	#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
	227	"128k(dtb)," \
	228	"1664k(kernel)," \
	229	"2m(rootfs)," \
cd82919e	230	"4m(data)"
29f8f58f	231
75dc29eb WD	232	/*-----------------------------------------------------------------------
	233	* Hardware Information Block
	234	*/
6d0f6bcf JCPV	235	#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
	236	#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
	237	#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
75dc29eb WD	238
	239	/*-----------------------------------------------------------------------
	240	* Cache Configuration
	241	*/
6d0f6bcf	242	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
60a0876b	243	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	244	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
75dc29eb WD	245	#endif
	246
	247	/*-----------------------------------------------------------------------
	248	* SYPCR - System Protection Control 11-9
	249	* SYPCR can only be written once after reset!
	250	*-----------------------------------------------------------------------
	251	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	252	*/
	253	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	254	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
75dc29eb WD	255	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
75dc29eb WD	256	#else
6d0f6bcf	257	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
75dc29eb WD	258	#endif
	259
	260	/*-----------------------------------------------------------------------
	261	* SIUMCR - SIU Module Configuration 11-6
	262	*-----------------------------------------------------------------------
	263	* PCMCIA config., multi-function pin tri-state
	264	*/
6d0f6bcf	265	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
75dc29eb WD	266
	267	/*-----------------------------------------------------------------------
	268	* TBSCR - Time Base Status and Control 11-26
	269	*-----------------------------------------------------------------------
	270	* Clear Reference Interrupt Status, Timebase freezing enabled
	271	*/
6d0f6bcf	272	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
75dc29eb WD	273
	274	/*-----------------------------------------------------------------------
	275	* RTCSC - Real-Time Clock Status and Control Register 11-27
	276	*-----------------------------------------------------------------------
	277	*/
6d0f6bcf	278	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
75dc29eb WD	279
	280	/*-----------------------------------------------------------------------
	281	* PISCR - Periodic Interrupt Status and Control 11-31
	282	*-----------------------------------------------------------------------
	283	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	284	*/
6d0f6bcf	285	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
75dc29eb WD	286
	287	/*-----------------------------------------------------------------------
	288	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	289	*-----------------------------------------------------------------------
	290	* Reset PLL lock status sticky bit, timer expired status bit and timer
	291	* interrupt status bit - leave PLL multiplication factor unchanged !
	292	*/
6d0f6bcf	293	#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
75dc29eb WD	294
	295	/*-----------------------------------------------------------------------
	296	* SCCR - System Clock and reset Control Register 15-27
	297	*-----------------------------------------------------------------------
	298	* Set clock output, timebase and RTC source and divider,
	299	* power management and some other internal clocks
	300	*/
	301	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	302	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
75dc29eb WD	303	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	304	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	305	SCCR_DFALCD00)
	306
	307	/*-----------------------------------------------------------------------
	308	* PCMCIA stuff
	309	*-----------------------------------------------------------------------
	310	*
	311	*/
6d0f6bcf JCPV	312	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	313	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	314	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	315	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	316	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	317	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	318	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	319	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
75dc29eb WD	320
	321	/*-----------------------------------------------------------------------
	322	*
	323	*-----------------------------------------------------------------------
	324	*
	325	*/
6d0f6bcf	326	#define CONFIG_SYS_DER 0
75dc29eb WD	327
	328	/*
	329	* Init Memory Controller:
	330	*
	331	* BR0/1 and OR0/1 (FLASH)
	332	*/
	333
	334	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	335	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	336
	337	/* used to re-map FLASH both when starting from SRAM or FLASH:
	338	* restrict access enough to keep SRAM working (if any)
	339	* but not too much to meddle with FLASH accesses
	340	*/
6d0f6bcf JCPV	341	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	342	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
75dc29eb	343
46a414dc WD	344	/*
	345	* FLASH timing:
	346	*/
6d0f6bcf	347	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
46a414dc	348	OR_SCY_3_CLK \| OR_EHTR \| OR_BI)
75dc29eb	349
6d0f6bcf JCPV	350	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	351	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	352	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
75dc29eb	353
6d0f6bcf JCPV	354	#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
	355	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	356	#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V )
75dc29eb WD	357
	358	/*
	359	* BR2/3 and OR2/3 (SDRAM)
	360	*
	361	*/
	362	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	363	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
	364	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	365
	366	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	367	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
75dc29eb	368
6d0f6bcf JCPV	369	#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	370	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
75dc29eb	371
6d0f6bcf JCPV	372	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
6d0f6bcf JCPV	373	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
75dc29eb WD	374
	375	/*
	376	* Memory Periodic Timer Prescaler
46a414dc WD	377	*
	378	* The Divider for PTA (refresh timer) configuration is based on an
	379	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	380	* the number of chip selects (NCS) and the actually needed refresh
	381	* rate is done by setting MPTPR.
	382	*
	383	* PTA is calculated from
	384	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	385	*
	386	* gclk CPU clock (not bus clock!)
	387	* Trefresh Refresh cycle * 4 (four word bursts used)
	388	*
	389	* 4096 Rows from SDRAM example configuration
	390	* 1000 factor s -> ms
	391	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	392	* 4 Number of refresh cycles per period
	393	* 64 Refresh cycle in ms per number of rows
	394	* --------------------------------------------
	395	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	396	*
	397	* 50 MHz => 50.000.000 / Divider = 98
	398	* 66 Mhz => 66.000.000 / Divider = 129
	399	* 80 Mhz => 80.000.000 / Divider = 156
75dc29eb WD	400	*/
75dc29eb WD	401
6d0f6bcf JCPV	402	#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
6d0f6bcf JCPV	403	#define CONFIG_SYS_MAMR_PTA 98
75dc29eb	404
46a414dc WD	405	/*
	406	* For 16 MBit, refresh rates could be 31.3 us
	407	* (= 64 ms / 2K = 125 / quad bursts).
	408	* For a simpler initialization, 15.6 us is used instead.
	409	*
6d0f6bcf JCPV	410	* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
6d0f6bcf JCPV	411	* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
46a414dc	412	*/
6d0f6bcf JCPV	413	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	414	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
75dc29eb WD	415
75dc29eb WD	416	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	417	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	418	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
75dc29eb WD	419
	420	/*
	421	* MAMR settings for SDRAM
	422	*/
	423
	424	/* 8 column SDRAM */
6d0f6bcf	425	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
75dc29eb WD	426	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	427	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	428	/* 9 column SDRAM */
6d0f6bcf	429	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
75dc29eb WD	430	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	431	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	432
7026ead0 HS	433	/* pass open firmware flat tree */
	434	#define CONFIG_OF_LIBFDT 1
	435	#define CONFIG_OF_BOARD_SETUP 1
	436	#define CONFIG_HWCONFIG 1
	437
75dc29eb	438	#endif /* __CONFIG_H */