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a20b27a3 SR |
1 | /* |
2 | * (C) Copyright 2001-2004 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
98f4a3df SR |
5 | * (C) Copyright 2005 |
6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
7 | * | |
48a05a51 SR |
8 | * (C) Copyright 2006 |
9 | * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com | |
10 | * | |
a20b27a3 SR |
11 | * See file CREDITS for list of people who contributed to this |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | /* | |
31 | * board/config.h - configuration options, board specific | |
32 | */ | |
33 | ||
34 | #ifndef __CONFIG_H | |
35 | #define __CONFIG_H | |
36 | ||
37 | /* | |
38 | * High Level Configuration Options | |
39 | * (easy to change) | |
40 | */ | |
41 | ||
42 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
43 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
53677ef1 | 44 | #define CONFIG_HH405 1 /* ...on a HH405 board */ |
a20b27a3 SR |
45 | |
46 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ | |
47 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
48 | ||
49 | #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ | |
50 | ||
51 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
52 | ||
53 | #define CONFIG_BAUDRATE 9600 | |
54 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
55 | ||
56 | #undef CONFIG_BOOTARGS | |
57 | #undef CONFIG_BOOTCOMMAND | |
58 | ||
59 | #define CONFIG_PREBOOT "autoupd" | |
60 | ||
2c7b2ab5 SR |
61 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
62 | "pciconfighost=1\0" \ | |
63 | "" | |
64 | ||
6d0f6bcf | 65 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
a20b27a3 | 66 | |
96e21f86 | 67 | #define CONFIG_PPC4xx_EMAC |
48a05a51 SR |
68 | #define CONFIG_NET_MULTI 1 |
69 | #undef CONFIG_HAS_ETH1 | |
70 | ||
a20b27a3 | 71 | #define CONFIG_MII 1 /* MII PHY management */ |
48a05a51 | 72 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 73 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
48a05a51 | 74 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
a20b27a3 SR |
75 | |
76 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ | |
77 | ||
98f4a3df SR |
78 | /* |
79 | * Video console | |
80 | */ | |
2c7b2ab5 SR |
81 | #define CONFIG_VIDEO /* for sm501 video support */ |
82 | ||
83 | #ifdef CONFIG_VIDEO | |
98f4a3df SR |
84 | #define CONFIG_VIDEO_SM501 |
85 | #if 0 | |
86 | #define CONFIG_VIDEO_SM501_32BPP | |
87 | #else | |
88 | #define CONFIG_VIDEO_SM501_16BPP | |
89 | #endif | |
48a05a51 | 90 | #define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 |
98f4a3df SR |
91 | #define CONFIG_CFB_CONSOLE |
92 | #define CONFIG_VIDEO_LOGO | |
93 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
94 | #define CONFIG_CONSOLE_EXTRA_INFO | |
95 | #define CONFIG_VIDEO_SW_CURSOR | |
96 | #define CONFIG_SPLASH_SCREEN | |
6d0f6bcf | 97 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
98f4a3df SR |
98 | #define CONFIG_SPLASH_SCREEN |
99 | #define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ | |
6d0f6bcf | 100 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */ |
98f4a3df | 101 | |
2c7b2ab5 | 102 | #endif /* CONFIG_VIDEO */ |
98f4a3df | 103 | |
11799434 JL |
104 | |
105 | /* | |
106 | * BOOTP options | |
107 | */ | |
108 | #define CONFIG_BOOTP_BOOTFILESIZE | |
109 | #define CONFIG_BOOTP_BOOTPATH | |
110 | #define CONFIG_BOOTP_GATEWAY | |
111 | #define CONFIG_BOOTP_HOSTNAME | |
112 | ||
113 | ||
6c4f4da9 JL |
114 | /* |
115 | * Command line configuration. | |
116 | */ | |
117 | #include <config_cmd_default.h> | |
118 | ||
119 | #define CONFIG_CMD_DHCP | |
120 | #define CONFIG_CMD_PCI | |
121 | #define CONFIG_CMD_IRQ | |
122 | #define CONFIG_CMD_IDE | |
123 | #define CONFIG_CMD_FAT | |
124 | #define CONFIG_CMD_EXT2 | |
125 | #define CONFIG_CMD_ELF | |
126 | #define CONFIG_CMD_NAND | |
127 | #define CONFIG_CMD_I2C | |
128 | #define CONFIG_CMD_DATE | |
129 | #define CONFIG_CMD_MII | |
130 | #define CONFIG_CMD_PING | |
6c4f4da9 JL |
131 | #define CONFIG_CMD_EEPROM |
132 | ||
11799434 JL |
133 | #ifdef CONFIG_VIDEO |
134 | #define CONFIG_CMD_BMP | |
135 | #endif | |
a20b27a3 SR |
136 | |
137 | #define CONFIG_MAC_PARTITION | |
138 | #define CONFIG_DOS_PARTITION | |
139 | ||
140 | #define CONFIG_SUPPORT_VFAT | |
141 | ||
142 | #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ | |
143 | #undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ | |
144 | ||
a20b27a3 SR |
145 | #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ |
146 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
147 | ||
148 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
149 | ||
150 | /* | |
151 | * Miscellaneous configurable options | |
152 | */ | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
154 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
a20b27a3 | 155 | |
6d0f6bcf JCPV |
156 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
157 | #ifdef CONFIG_SYS_HUSH_PARSER | |
158 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
a20b27a3 SR |
159 | #endif |
160 | ||
6c4f4da9 | 161 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 162 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
a20b27a3 | 163 | #else |
6d0f6bcf | 164 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
a20b27a3 | 165 | #endif |
6d0f6bcf JCPV |
166 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
167 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
168 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
a20b27a3 | 169 | |
6d0f6bcf | 170 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
a20b27a3 | 171 | |
6d0f6bcf | 172 | #undef CONFIG_SYS_CONSOLE_INFO_QUIET /* print console @ startup */ |
a20b27a3 SR |
173 | |
174 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ | |
175 | ||
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
177 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
a20b27a3 | 178 | |
6d0f6bcf | 179 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 180 | #define CONFIG_SYS_BASE_BAUD 691200 |
a20b27a3 SR |
181 | #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ |
182 | ||
183 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 184 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
a20b27a3 SR |
185 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
186 | 57600, 115200, 230400, 460800, 921600 } | |
187 | ||
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
189 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
a20b27a3 | 190 | |
6d0f6bcf | 191 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
a20b27a3 SR |
192 | |
193 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
194 | ||
195 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
196 | ||
6d0f6bcf | 197 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
a20b27a3 | 198 | |
98f4a3df SR |
199 | /*----------------------------------------------------------------------- |
200 | * RTC stuff | |
201 | *----------------------------------------------------------------------- | |
202 | */ | |
203 | #define CONFIG_RTC_DS1338 | |
6d0f6bcf | 204 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
98f4a3df | 205 | |
a20b27a3 SR |
206 | /*----------------------------------------------------------------------- |
207 | * NAND-FLASH stuff | |
208 | *----------------------------------------------------------------------- | |
209 | */ | |
6d0f6bcf | 210 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
6d0f6bcf | 211 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
bd84ee4c MF |
212 | #define NAND_BIG_DELAY_US 25 |
213 | ||
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
215 | #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
216 | #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
217 | #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
a20b27a3 | 218 | |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
220 | #define CONFIG_SYS_NAND_QUIET 1 | |
a20b27a3 | 221 | |
170c1972 WD |
222 | #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ |
223 | ||
a20b27a3 SR |
224 | /*----------------------------------------------------------------------- |
225 | * PCI stuff | |
226 | *----------------------------------------------------------------------- | |
227 | */ | |
228 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
229 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
230 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
231 | ||
232 | #define CONFIG_PCI /* include pci support */ | |
233 | #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ | |
234 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
235 | /* resource configuration */ | |
236 | ||
237 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
238 | ||
239 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
240 | ||
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
242 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
243 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
244 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
245 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
246 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
247 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
248 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
249 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
a20b27a3 SR |
250 | |
251 | /*----------------------------------------------------------------------- | |
252 | * IDE/ATA stuff | |
253 | *----------------------------------------------------------------------- | |
254 | */ | |
255 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
256 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
257 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ | |
258 | ||
6d0f6bcf JCPV |
259 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
260 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ | |
a20b27a3 | 261 | |
6d0f6bcf JCPV |
262 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
263 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
a20b27a3 | 264 | |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
266 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
267 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
a20b27a3 SR |
268 | |
269 | /* | |
270 | * For booting Linux, the board info and command line data | |
271 | * have to be in the first 8 MB of memory, since this is | |
272 | * the maximum mapped by the Linux kernel during initialization. | |
273 | */ | |
6d0f6bcf | 274 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
a20b27a3 SR |
275 | /*----------------------------------------------------------------------- |
276 | * FLASH organization | |
277 | */ | |
278 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ | |
279 | ||
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
281 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
a20b27a3 | 282 | |
6d0f6bcf JCPV |
283 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
284 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
a20b27a3 | 285 | |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
287 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
288 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
a20b27a3 SR |
289 | /* |
290 | * The following defines are added for buggy IOP480 byte interface. | |
291 | * All other boards should use the standard values (CPCI405 etc.) | |
292 | */ | |
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
294 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
295 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
a20b27a3 | 296 | |
6d0f6bcf | 297 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
a20b27a3 SR |
298 | |
299 | #if 0 /* test-only */ | |
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ |
301 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ | |
a20b27a3 SR |
302 | #endif |
303 | ||
304 | /*----------------------------------------------------------------------- | |
305 | * Start addresses for the final memory configuration | |
306 | * (Set up by the startup code) | |
6d0f6bcf | 307 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
a20b27a3 | 308 | */ |
6d0f6bcf JCPV |
309 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
310 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 | |
311 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
312 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ | |
313 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */ | |
314 | ||
315 | #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) | |
316 | # define CONFIG_SYS_RAMBOOT 1 | |
a20b27a3 | 317 | #else |
6d0f6bcf | 318 | # undef CONFIG_SYS_RAMBOOT |
a20b27a3 SR |
319 | #endif |
320 | ||
321 | /*----------------------------------------------------------------------- | |
322 | * Environment Variable setup | |
323 | */ | |
bb1f8b4f | 324 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
325 | #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
326 | #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ | |
a20b27a3 SR |
327 | /* total size of a CAT24WC16 is 2048 bytes */ |
328 | ||
6d0f6bcf JCPV |
329 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */ |
330 | #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ | |
a20b27a3 SR |
331 | |
332 | /*----------------------------------------------------------------------- | |
333 | * I2C EEPROM (CAT24WC16) for environment | |
334 | */ | |
335 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
336 | #if 0 /* test-only */ | |
6d0f6bcf | 337 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
a20b27a3 | 338 | #else |
6d0f6bcf | 339 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
a20b27a3 | 340 | #endif |
6d0f6bcf | 341 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
a20b27a3 | 342 | |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ |
344 | #define CONFIG_SYS_EEPROM_WREN 1 | |
98f4a3df | 345 | |
a20b27a3 SR |
346 | #if 1 /* test-only */ |
347 | /* CAT24WC08/16... */ | |
6d0f6bcf | 348 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
a20b27a3 | 349 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
350 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
351 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
a20b27a3 SR |
352 | /* 16 byte page write mode using*/ |
353 | /* last 4 bits of the address */ | |
354 | #else | |
355 | /* CAT24WC32/64... */ | |
6d0f6bcf | 356 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ |
a20b27a3 | 357 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
358 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 |
359 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ | |
a20b27a3 SR |
360 | /* 32 byte page write mode using*/ |
361 | /* last 5 bits of the address */ | |
362 | #endif | |
6d0f6bcf | 363 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
a20b27a3 | 364 | |
a20b27a3 SR |
365 | /*----------------------------------------------------------------------- |
366 | * External Bus Controller (EBC) Setup | |
367 | */ | |
368 | ||
369 | #define CAN_BA 0xF0000000 /* CAN Base Address */ | |
370 | #define LCD_BA 0xF1000000 /* Epson LCD Base Address */ | |
6d0f6bcf JCPV |
371 | #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ |
372 | #define CONFIG_SYS_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */ | |
a20b27a3 SR |
373 | |
374 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
375 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
376 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
a20b27a3 SR |
377 | |
378 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */ | |
6d0f6bcf JCPV |
379 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
380 | #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ | |
a20b27a3 SR |
381 | |
382 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ | |
6d0f6bcf JCPV |
383 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
384 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
a20b27a3 SR |
385 | |
386 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ | |
6d0f6bcf JCPV |
387 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
388 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
a20b27a3 SR |
389 | |
390 | /* Memory Bank 4 (Epson LCD) initialization */ | |
6d0f6bcf JCPV |
391 | #define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ |
392 | #define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ | |
a20b27a3 SR |
393 | |
394 | /*----------------------------------------------------------------------- | |
395 | * LCD Setup | |
396 | */ | |
397 | ||
6d0f6bcf JCPV |
398 | #define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ |
399 | #define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ | |
400 | #define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ | |
401 | #define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ | |
a20b27a3 | 402 | |
a20b27a3 SR |
403 | /*----------------------------------------------------------------------- |
404 | * Universal Interrupt Controller (UIC) Setup | |
405 | */ | |
406 | ||
407 | /* | |
408 | * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high | |
409 | */ | |
6d0f6bcf | 410 | #define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6)) |
a20b27a3 SR |
411 | |
412 | /*----------------------------------------------------------------------- | |
413 | * FPGA stuff | |
414 | */ | |
415 | ||
6d0f6bcf | 416 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ |
a20b27a3 | 417 | |
a20b27a3 SR |
418 | #define LCD_CLK_OFF 0x0000 /* Off */ |
419 | #define LCD_CLK_02083 0x1000 /* 2.083 MHz */ | |
420 | #define LCD_CLK_03135 0x2000 /* 3.135 MHz */ | |
421 | #define LCD_CLK_04165 0x3000 /* 4.165 MHz */ | |
422 | #define LCD_CLK_06250 0x4000 /* 6.250 MHz */ | |
423 | #define LCD_CLK_08330 0x5000 /* 8.330 MHz */ | |
424 | #define LCD_CLK_12500 0x6000 /* 12.50 MHz */ | |
425 | #define LCD_CLK_25000 0x7000 /* 25.00 MHz */ | |
426 | ||
6d0f6bcf JCPV |
427 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
428 | #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
a20b27a3 SR |
429 | |
430 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
431 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
432 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
433 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
434 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
435 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
a20b27a3 SR |
436 | |
437 | /*----------------------------------------------------------------------- | |
438 | * Definitions for initial stack pointer and data area (in data cache) | |
439 | */ | |
440 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 441 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
a20b27a3 SR |
442 | |
443 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
444 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
445 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
446 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
447 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ | |
a20b27a3 | 448 | |
6d0f6bcf JCPV |
449 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
450 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
451 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
a20b27a3 SR |
452 | |
453 | /*----------------------------------------------------------------------- | |
454 | * Definitions for GPIO setup (PPC405EP specific) | |
455 | * | |
456 | * GPIO0[0] - External Bus Controller BLAST output | |
457 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
458 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs | |
459 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
460 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
461 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
462 | * GPIO0[28-29] - UART1 data signal input/output | |
463 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs | |
464 | */ | |
6d0f6bcf JCPV |
465 | #define CONFIG_SYS_GPIO0_OSRH 0x40000550 |
466 | #define CONFIG_SYS_GPIO0_OSRL 0x00000110 | |
467 | #define CONFIG_SYS_GPIO0_ISR1H 0x00000000 | |
468 | #define CONFIG_SYS_GPIO0_ISR1L 0x15555440 | |
469 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 | |
470 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 | |
471 | #define CONFIG_SYS_GPIO0_TCR 0xF7FE0017 | |
472 | ||
473 | #define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7) | |
474 | #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ | |
475 | #define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */ | |
476 | #define CONFIG_SYS_LCD0_RST (0x80000000 >> 30) | |
477 | #define CONFIG_SYS_LCD1_RST (0x80000000 >> 31) | |
a20b27a3 SR |
478 | |
479 | /* | |
480 | * Internal Definitions | |
481 | * | |
482 | * Boot Flags | |
483 | */ | |
484 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
485 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
486 | ||
487 | /* | |
488 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
489 | * This value will be set if iic boot eprom is disabled. | |
490 | */ | |
491 | #if 0 | |
492 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 | |
493 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
494 | #endif | |
495 | #if 0 | |
496 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 | |
497 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
498 | #endif | |
499 | #if 1 | |
500 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 | |
501 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
502 | #endif | |
503 | ||
504 | #endif /* __CONFIG_H */ |