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Commit | Line | Data |
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a20b27a3 SR |
1 | /* |
2 | * (C) Copyright 2001-2004 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
98f4a3df SR |
5 | * (C) Copyright 2005 |
6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
7 | * | |
48a05a51 SR |
8 | * (C) Copyright 2006 |
9 | * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com | |
10 | * | |
3765b3e7 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
a20b27a3 SR |
12 | */ |
13 | ||
14 | /* | |
15 | * board/config.h - configuration options, board specific | |
16 | */ | |
17 | ||
18 | #ifndef __CONFIG_H | |
19 | #define __CONFIG_H | |
20 | ||
21 | /* | |
22 | * High Level Configuration Options | |
23 | * (easy to change) | |
24 | */ | |
25 | ||
26 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
27 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
53677ef1 | 28 | #define CONFIG_HH405 1 /* ...on a HH405 board */ |
a20b27a3 | 29 | |
2ae18241 WD |
30 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
31 | ||
a20b27a3 SR |
32 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
33 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
34 | ||
35 | #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ | |
36 | ||
37 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
38 | ||
39 | #define CONFIG_BAUDRATE 9600 | |
40 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
41 | ||
42 | #undef CONFIG_BOOTARGS | |
43 | #undef CONFIG_BOOTCOMMAND | |
44 | ||
45 | #define CONFIG_PREBOOT "autoupd" | |
46 | ||
2c7b2ab5 SR |
47 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
48 | "pciconfighost=1\0" \ | |
49 | "" | |
50 | ||
6d0f6bcf | 51 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
a20b27a3 | 52 | |
96e21f86 | 53 | #define CONFIG_PPC4xx_EMAC |
48a05a51 SR |
54 | #undef CONFIG_HAS_ETH1 |
55 | ||
a20b27a3 | 56 | #define CONFIG_MII 1 /* MII PHY management */ |
48a05a51 | 57 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 58 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
48a05a51 | 59 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
a20b27a3 SR |
60 | |
61 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ | |
62 | ||
98f4a3df SR |
63 | /* |
64 | * Video console | |
65 | */ | |
2c7b2ab5 SR |
66 | #define CONFIG_VIDEO /* for sm501 video support */ |
67 | ||
68 | #ifdef CONFIG_VIDEO | |
98f4a3df SR |
69 | #define CONFIG_VIDEO_SM501 |
70 | #if 0 | |
71 | #define CONFIG_VIDEO_SM501_32BPP | |
72 | #else | |
73 | #define CONFIG_VIDEO_SM501_16BPP | |
74 | #endif | |
48a05a51 | 75 | #define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 |
98f4a3df SR |
76 | #define CONFIG_CFB_CONSOLE |
77 | #define CONFIG_VIDEO_LOGO | |
78 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
79 | #define CONFIG_CONSOLE_EXTRA_INFO | |
80 | #define CONFIG_VIDEO_SW_CURSOR | |
81 | #define CONFIG_SPLASH_SCREEN | |
6d0f6bcf | 82 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
98f4a3df SR |
83 | #define CONFIG_SPLASH_SCREEN |
84 | #define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ | |
6d0f6bcf | 85 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */ |
98f4a3df | 86 | |
2c7b2ab5 | 87 | #endif /* CONFIG_VIDEO */ |
98f4a3df | 88 | |
11799434 JL |
89 | |
90 | /* | |
91 | * BOOTP options | |
92 | */ | |
93 | #define CONFIG_BOOTP_BOOTFILESIZE | |
94 | #define CONFIG_BOOTP_BOOTPATH | |
95 | #define CONFIG_BOOTP_GATEWAY | |
96 | #define CONFIG_BOOTP_HOSTNAME | |
97 | ||
98 | ||
6c4f4da9 JL |
99 | /* |
100 | * Command line configuration. | |
101 | */ | |
102 | #include <config_cmd_default.h> | |
103 | ||
104 | #define CONFIG_CMD_DHCP | |
105 | #define CONFIG_CMD_PCI | |
106 | #define CONFIG_CMD_IRQ | |
107 | #define CONFIG_CMD_IDE | |
108 | #define CONFIG_CMD_FAT | |
109 | #define CONFIG_CMD_EXT2 | |
110 | #define CONFIG_CMD_ELF | |
111 | #define CONFIG_CMD_NAND | |
112 | #define CONFIG_CMD_I2C | |
113 | #define CONFIG_CMD_DATE | |
114 | #define CONFIG_CMD_MII | |
115 | #define CONFIG_CMD_PING | |
6c4f4da9 JL |
116 | #define CONFIG_CMD_EEPROM |
117 | ||
11799434 JL |
118 | #ifdef CONFIG_VIDEO |
119 | #define CONFIG_CMD_BMP | |
120 | #endif | |
a20b27a3 SR |
121 | |
122 | #define CONFIG_MAC_PARTITION | |
123 | #define CONFIG_DOS_PARTITION | |
124 | ||
125 | #define CONFIG_SUPPORT_VFAT | |
126 | ||
127 | #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ | |
128 | #undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ | |
129 | ||
a20b27a3 SR |
130 | #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ |
131 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
132 | ||
133 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
134 | ||
135 | /* | |
136 | * Miscellaneous configurable options | |
137 | */ | |
6d0f6bcf | 138 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
a20b27a3 | 139 | |
6d0f6bcf | 140 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
a20b27a3 | 141 | |
6c4f4da9 | 142 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 143 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
a20b27a3 | 144 | #else |
6d0f6bcf | 145 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
a20b27a3 | 146 | #endif |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
148 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
149 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
a20b27a3 | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
a20b27a3 | 152 | |
6d0f6bcf | 153 | #undef CONFIG_SYS_CONSOLE_INFO_QUIET /* print console @ startup */ |
a20b27a3 SR |
154 | |
155 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ | |
156 | ||
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
158 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
a20b27a3 | 159 | |
550650dd SR |
160 | #define CONFIG_CONS_INDEX 2 /* Use UART1 */ |
161 | #define CONFIG_SYS_NS16550 | |
162 | #define CONFIG_SYS_NS16550_SERIAL | |
163 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
164 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
165 | ||
6d0f6bcf | 166 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 167 | #define CONFIG_SYS_BASE_BAUD 691200 |
a20b27a3 SR |
168 | |
169 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 170 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
a20b27a3 SR |
171 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
172 | 57600, 115200, 230400, 460800, 921600 } | |
173 | ||
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
175 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
a20b27a3 | 176 | |
a20b27a3 SR |
177 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
178 | ||
179 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
180 | ||
6d0f6bcf | 181 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
a20b27a3 | 182 | |
98f4a3df SR |
183 | /*----------------------------------------------------------------------- |
184 | * RTC stuff | |
185 | *----------------------------------------------------------------------- | |
186 | */ | |
187 | #define CONFIG_RTC_DS1338 | |
6d0f6bcf | 188 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
98f4a3df | 189 | |
a20b27a3 SR |
190 | /*----------------------------------------------------------------------- |
191 | * NAND-FLASH stuff | |
192 | *----------------------------------------------------------------------- | |
193 | */ | |
6d0f6bcf | 194 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
6d0f6bcf | 195 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
bd84ee4c MF |
196 | #define NAND_BIG_DELAY_US 25 |
197 | ||
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
199 | #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
200 | #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
201 | #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
a20b27a3 | 202 | |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
204 | #define CONFIG_SYS_NAND_QUIET 1 | |
a20b27a3 SR |
205 | |
206 | /*----------------------------------------------------------------------- | |
207 | * PCI stuff | |
208 | *----------------------------------------------------------------------- | |
209 | */ | |
210 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
211 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
212 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
213 | ||
214 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 215 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
a20b27a3 SR |
216 | #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ |
217 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
218 | /* resource configuration */ | |
219 | ||
220 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
221 | ||
222 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
223 | ||
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
225 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
226 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
227 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
228 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
229 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
230 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
231 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
232 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
a20b27a3 SR |
233 | |
234 | /*----------------------------------------------------------------------- | |
235 | * IDE/ATA stuff | |
236 | *----------------------------------------------------------------------- | |
237 | */ | |
238 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
239 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
240 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ | |
241 | ||
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
243 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ | |
a20b27a3 | 244 | |
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
246 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
a20b27a3 | 247 | |
6d0f6bcf JCPV |
248 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
249 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
250 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
a20b27a3 SR |
251 | |
252 | /* | |
253 | * For booting Linux, the board info and command line data | |
254 | * have to be in the first 8 MB of memory, since this is | |
255 | * the maximum mapped by the Linux kernel during initialization. | |
256 | */ | |
6d0f6bcf | 257 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
a20b27a3 SR |
258 | /*----------------------------------------------------------------------- |
259 | * FLASH organization | |
260 | */ | |
261 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ | |
262 | ||
6d0f6bcf JCPV |
263 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
264 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
a20b27a3 | 265 | |
6d0f6bcf JCPV |
266 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
267 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
a20b27a3 | 268 | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
270 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
271 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
a20b27a3 SR |
272 | /* |
273 | * The following defines are added for buggy IOP480 byte interface. | |
274 | * All other boards should use the standard values (CPCI405 etc.) | |
275 | */ | |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
277 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
278 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
a20b27a3 | 279 | |
6d0f6bcf | 280 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
a20b27a3 SR |
281 | |
282 | #if 0 /* test-only */ | |
6d0f6bcf JCPV |
283 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ |
284 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ | |
a20b27a3 SR |
285 | #endif |
286 | ||
287 | /*----------------------------------------------------------------------- | |
288 | * Start addresses for the final memory configuration | |
289 | * (Set up by the startup code) | |
6d0f6bcf | 290 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
a20b27a3 | 291 | */ |
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
293 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 | |
14d0a02a | 294 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
295 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ |
296 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */ | |
297 | ||
298 | #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) | |
299 | # define CONFIG_SYS_RAMBOOT 1 | |
a20b27a3 | 300 | #else |
6d0f6bcf | 301 | # undef CONFIG_SYS_RAMBOOT |
a20b27a3 SR |
302 | #endif |
303 | ||
304 | /*----------------------------------------------------------------------- | |
305 | * Environment Variable setup | |
306 | */ | |
bb1f8b4f | 307 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
308 | #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
309 | #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ | |
a20b27a3 SR |
310 | /* total size of a CAT24WC16 is 2048 bytes */ |
311 | ||
6d0f6bcf JCPV |
312 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */ |
313 | #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ | |
a20b27a3 SR |
314 | |
315 | /*----------------------------------------------------------------------- | |
316 | * I2C EEPROM (CAT24WC16) for environment | |
317 | */ | |
880540de DE |
318 | #define CONFIG_SYS_I2C |
319 | #define CONFIG_SYS_I2C_PPC4XX | |
320 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
a20b27a3 | 321 | #if 0 /* test-only */ |
880540de | 322 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
a20b27a3 | 323 | #else |
880540de | 324 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
a20b27a3 | 325 | #endif |
880540de | 326 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
a20b27a3 | 327 | |
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ |
329 | #define CONFIG_SYS_EEPROM_WREN 1 | |
98f4a3df | 330 | |
a20b27a3 SR |
331 | #if 1 /* test-only */ |
332 | /* CAT24WC08/16... */ | |
6d0f6bcf | 333 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
a20b27a3 | 334 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
336 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
a20b27a3 SR |
337 | /* 16 byte page write mode using*/ |
338 | /* last 4 bits of the address */ | |
339 | #else | |
340 | /* CAT24WC32/64... */ | |
6d0f6bcf | 341 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ |
a20b27a3 | 342 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 |
344 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ | |
a20b27a3 SR |
345 | /* 32 byte page write mode using*/ |
346 | /* last 5 bits of the address */ | |
347 | #endif | |
6d0f6bcf | 348 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
a20b27a3 | 349 | |
a20b27a3 SR |
350 | /*----------------------------------------------------------------------- |
351 | * External Bus Controller (EBC) Setup | |
352 | */ | |
353 | ||
354 | #define CAN_BA 0xF0000000 /* CAN Base Address */ | |
355 | #define LCD_BA 0xF1000000 /* Epson LCD Base Address */ | |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ |
357 | #define CONFIG_SYS_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */ | |
a20b27a3 SR |
358 | |
359 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
360 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
361 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
a20b27a3 SR |
362 | |
363 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */ | |
6d0f6bcf JCPV |
364 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
365 | #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ | |
a20b27a3 SR |
366 | |
367 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ | |
6d0f6bcf JCPV |
368 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
369 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
a20b27a3 SR |
370 | |
371 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ | |
6d0f6bcf JCPV |
372 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
373 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
a20b27a3 SR |
374 | |
375 | /* Memory Bank 4 (Epson LCD) initialization */ | |
6d0f6bcf JCPV |
376 | #define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ |
377 | #define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ | |
a20b27a3 SR |
378 | |
379 | /*----------------------------------------------------------------------- | |
380 | * LCD Setup | |
381 | */ | |
382 | ||
6d0f6bcf JCPV |
383 | #define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ |
384 | #define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ | |
385 | #define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ | |
386 | #define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ | |
a20b27a3 | 387 | |
a20b27a3 SR |
388 | /*----------------------------------------------------------------------- |
389 | * Universal Interrupt Controller (UIC) Setup | |
390 | */ | |
391 | ||
392 | /* | |
393 | * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high | |
394 | */ | |
6d0f6bcf | 395 | #define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6)) |
a20b27a3 SR |
396 | |
397 | /*----------------------------------------------------------------------- | |
398 | * FPGA stuff | |
399 | */ | |
400 | ||
6d0f6bcf | 401 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ |
a20b27a3 | 402 | |
a20b27a3 SR |
403 | #define LCD_CLK_OFF 0x0000 /* Off */ |
404 | #define LCD_CLK_02083 0x1000 /* 2.083 MHz */ | |
405 | #define LCD_CLK_03135 0x2000 /* 3.135 MHz */ | |
406 | #define LCD_CLK_04165 0x3000 /* 4.165 MHz */ | |
407 | #define LCD_CLK_06250 0x4000 /* 6.250 MHz */ | |
408 | #define LCD_CLK_08330 0x5000 /* 8.330 MHz */ | |
409 | #define LCD_CLK_12500 0x6000 /* 12.50 MHz */ | |
410 | #define LCD_CLK_25000 0x7000 /* 25.00 MHz */ | |
411 | ||
6d0f6bcf JCPV |
412 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
413 | #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
a20b27a3 SR |
414 | |
415 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
416 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
417 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
418 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
419 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
420 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
a20b27a3 SR |
421 | |
422 | /*----------------------------------------------------------------------- | |
423 | * Definitions for initial stack pointer and data area (in data cache) | |
424 | */ | |
425 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 426 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
a20b27a3 SR |
427 | |
428 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
429 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
430 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
431 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 432 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
a20b27a3 | 433 | |
25ddd1fb | 434 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 435 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
a20b27a3 SR |
436 | |
437 | /*----------------------------------------------------------------------- | |
438 | * Definitions for GPIO setup (PPC405EP specific) | |
439 | * | |
440 | * GPIO0[0] - External Bus Controller BLAST output | |
441 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
442 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs | |
443 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
444 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
445 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
446 | * GPIO0[28-29] - UART1 data signal input/output | |
447 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs | |
448 | */ | |
afabb498 SR |
449 | #define CONFIG_SYS_GPIO0_OSRL 0x40000550 |
450 | #define CONFIG_SYS_GPIO0_OSRH 0x00000110 | |
451 | #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 | |
452 | #define CONFIG_SYS_GPIO0_ISR1H 0x15555440 | |
6d0f6bcf | 453 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 |
afabb498 | 454 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 |
6d0f6bcf JCPV |
455 | #define CONFIG_SYS_GPIO0_TCR 0xF7FE0017 |
456 | ||
457 | #define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7) | |
458 | #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ | |
459 | #define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */ | |
460 | #define CONFIG_SYS_LCD0_RST (0x80000000 >> 30) | |
461 | #define CONFIG_SYS_LCD1_RST (0x80000000 >> 31) | |
a20b27a3 | 462 | |
a20b27a3 SR |
463 | /* |
464 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
465 | * This value will be set if iic boot eprom is disabled. | |
466 | */ | |
467 | #if 0 | |
468 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 | |
469 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
470 | #endif | |
471 | #if 0 | |
472 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 | |
473 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
474 | #endif | |
475 | #if 1 | |
476 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 | |
477 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
478 | #endif | |
479 | ||
480 | #endif /* __CONFIG_H */ |