[people/ms/u-boot.git] / include / configs / HH405.h

/*
 * (C) Copyright 2001-2004
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * (C) Copyright 2005
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * (C) Copyright 2006
 * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
#define CONFIG_HH405		1	/* ...on a HH405 board	        */

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */

#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#undef	CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT	        "autoupd"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"pciconfighost=1\0"						\
	""

#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_NET_MULTI	1
#undef  CONFIG_HAS_ETH1

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */

#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/

/*
 * Video console
 */
#define CONFIG_VIDEO			/* for sm501 video support	*/

#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_SM501
#if 0
#define CONFIG_VIDEO_SM501_32BPP
#else
#define CONFIG_VIDEO_SM501_16BPP
#endif
#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CFG_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_GZIP		/* gzip compressed bmp images	*/
#define CFG_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* for decompressed img */

#endif /* CONFIG_VIDEO */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DATE
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM

#ifdef CONFIG_VIDEO
#define CONFIG_CMD_BMP
#endif

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_SUPPORT_VFAT

#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
#undef CONFIG_AUTO_UPDATE_SHOW          /* use board show routine       */

#undef  CONFIG_BZIP2	 /* include support for bzip2 compressed images */
#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */

#undef  CFG_CONSOLE_INFO_QUIET          /* print console @ startup	*/

#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
#define CFG_BASE_BAUD       691200
#define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE      \
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */

#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * RTC stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_RTC_DS1338
#define CFG_I2C_RTC_ADDR	0x68

/*-----------------------------------------------------------------------
 * NAND-FLASH stuff
 *-----------------------------------------------------------------------
 */
#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
#define NAND_MAX_CHIPS          1
#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
#define NAND_BIG_DELAY_US	25

#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */

#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
#define CFG_NAND_QUIET          1

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
					/* resource configuration       */

#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */

#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/

#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define	CFG_ATA_BASE_ADDR	0xF0100000
#define	CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */

#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */

#if 0 /* test-only */
#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
#endif

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFF80000
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
#define CFG_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc()	*/

#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
# define CFG_RAMBOOT		1
#else
# undef CFG_RAMBOOT
#endif

/*-----------------------------------------------------------------------
 * Environment Variable setup
 */
#define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
				   /* total size of a CAT24WC16 is 2048 bytes */

#define CFG_NVRAM_BASE_ADDR	0xF4080000		/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		0x8000		        /* NVRAM size		*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#if 0 /* test-only */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#else
#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
#endif
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
#define CFG_EEPROM_WREN         1

#if 1 /* test-only */
/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"    */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last	4 bits of the address	*/
#else
/* CAT24WC32/64... */
#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"    */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
					/* 32 byte page write mode using*/
					/* last	5 bits of the address	*/
#endif
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

#define CAN_BA          0xF0000000          /* CAN Base Address                 */
#define LCD_BA          0xF1000000          /* Epson LCD Base Address           */
#define CFG_NAND_BASE   0xF4000000          /* NAND FLASH Base Address          */
#define CFG_NVRAM_BASE  0xF4080000          /* NVRAM Base Address               */

/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
#define CFG_EBC_PB0AP           0x92015480
#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization              */
#define CFG_EBC_PB1AP           0x92015480
#define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */

/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */

/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 4 (Epson LCD) initialization                                     */
#define CFG_EBC_PB4AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
#define CFG_EBC_PB4CR   LCD_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */

/*-----------------------------------------------------------------------
 * LCD Setup
 */

#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
#define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
#define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */

/*-----------------------------------------------------------------------
 * Universal Interrupt Controller (UIC) Setup
 */

/*
 * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
 */
#define CFG_UIC0_POLARITY       (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))

/*-----------------------------------------------------------------------
 * FPGA stuff
 */

#define CFG_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */

/* FPGA internal regs */
#define CFG_FPGA_CTRL           0x000

/* FPGA Control Reg */
#define CFG_FPGA_CTRL_REV0      0x0001
#define CFG_FPGA_CTRL_REV1      0x0002
#define CFG_FPGA_CTRL_VGA0_BL   0x0004
#define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
#define CFG_FPGA_CTRL_CF_RESET  0x0040
#define CFG_FPGA_CTRL_PS2_PWR   0x0080
#define CFG_FPGA_CTRL_CF_PWRN   0x0100      /* low active                    */
#define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
#define CFG_FPGA_CTRL_LCD_CLK   0x7000      /* Mask for lcd clock            */
#define CFG_FPGA_CTRL_OW_ENABLE 0x8000

#define CFG_FPGA_STATUS_CF_DETECT 0x8000

#define LCD_CLK_OFF             0x0000      /* Off                           */
#define LCD_CLK_02083           0x1000      /* 2.083 MHz                     */
#define LCD_CLK_03135           0x2000      /* 3.135 MHz                     */
#define LCD_CLK_04165           0x3000      /* 4.165 MHz                     */
#define LCD_CLK_06250           0x4000      /* 6.250 MHz                     */
#define LCD_CLK_08330           0x5000      /* 8.330 MHz                     */
#define LCD_CLK_12500           0x6000      /* 12.50 MHz                     */
#define LCD_CLK_25000           0x7000      /* 25.00 MHz                     */

#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/

/* FPGA program pin configuration */
#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM        1

/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/

#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup (PPC405EP specific)
 *
 * GPIO0[0]     - External Bus Controller BLAST output
 * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 * GPIO0[24-27] - UART0 control signal inputs/outputs
 * GPIO0[28-29] - UART1 data signal input/output
 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 */
#define CFG_GPIO0_OSRH		0x40000550
#define CFG_GPIO0_OSRL		0x00000110
#define CFG_GPIO0_ISR1H		0x00000000
#define CFG_GPIO0_ISR1L		0x15555440
#define CFG_GPIO0_TSRH		0x00000000
#define CFG_GPIO0_TSRL		0x00000000
#define CFG_GPIO0_TCR		0xF7FE0017

#define CFG_LCD_ENDIAN		(0x80000000 >> 7)
#define CFG_EEPROM_WP		(0x80000000 >> 8)   /* GPIO8 */
#define CFG_TOUCH_RST		(0x80000000 >> 9)   /* GPIO9 */
#define CFG_LCD0_RST		(0x80000000 >> 30)
#define CFG_LCD1_RST		(0x80000000 >> 31)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

/*
 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 * This value will be set if iic boot eprom is disabled.
 */
#if 0
#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
#endif
#if 0
#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
#endif
#if 1
#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
a20b27a3 SR	1	/*
	2	* (C) Copyright 2001-2004
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
98f4a3df SR	5	* (C) Copyright 2005
	6	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	7	*
48a05a51 SR	8	* (C) Copyright 2006
	9	* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
	10	*
a20b27a3 SR	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	/*
	31	* board/config.h - configuration options, board specific
	32	*/
	33
	34	#ifndef __CONFIG_H
	35	#define __CONFIG_H
	36
	37	/*
	38	* High Level Configuration Options
	39	* (easy to change)
	40	*/
	41
	42	#define CONFIG_405EP 1 /* This is a PPC405 CPU */
	43	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
53677ef1	44	#define CONFIG_HH405 1 /* ...on a HH405 board */
a20b27a3 SR	45
	46	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
	47	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
	48
	49	#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
	50
	51	#define CONFIG_BOARD_TYPES 1 /* support board types */
	52
	53	#define CONFIG_BAUDRATE 9600
	54	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	55
	56	#undef CONFIG_BOOTARGS
	57	#undef CONFIG_BOOTCOMMAND
	58
	59	#define CONFIG_PREBOOT "autoupd"
	60
2c7b2ab5 SR	61	#define CONFIG_EXTRA_ENV_SETTINGS \
	62	"pciconfighost=1\0" \
	63	""
	64
a20b27a3 SR	65	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
a20b27a3 SR	66
48a05a51 SR	67	#define CONFIG_NET_MULTI 1
	68	#undef CONFIG_HAS_ETH1
	69
a20b27a3	70	#define CONFIG_MII 1 /* MII PHY management */
48a05a51	71	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	72	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
48a05a51	73	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
a20b27a3 SR	74
	75	#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
	76
98f4a3df SR	77	/*
	78	* Video console
	79	*/
2c7b2ab5 SR	80	#define CONFIG_VIDEO /* for sm501 video support */
	81
	82	#ifdef CONFIG_VIDEO
98f4a3df SR	83	#define CONFIG_VIDEO_SM501
	84	#if 0
	85	#define CONFIG_VIDEO_SM501_32BPP
	86	#else
	87	#define CONFIG_VIDEO_SM501_16BPP
	88	#endif
48a05a51	89	#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
98f4a3df SR	90	#define CONFIG_CFB_CONSOLE
	91	#define CONFIG_VIDEO_LOGO
	92	#define CONFIG_VGA_AS_SINGLE_DEVICE
	93	#define CONFIG_CONSOLE_EXTRA_INFO
	94	#define CONFIG_VIDEO_SW_CURSOR
	95	#define CONFIG_SPLASH_SCREEN
	96	#define CFG_CONSOLE_IS_IN_ENV
	97	#define CONFIG_SPLASH_SCREEN
	98	#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
c29ab9d7	99	#define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */
98f4a3df	100
2c7b2ab5	101	#endif /* CONFIG_VIDEO */
98f4a3df	102
11799434 JL	103
	104	/*
	105	* BOOTP options
	106	*/
	107	#define CONFIG_BOOTP_BOOTFILESIZE
	108	#define CONFIG_BOOTP_BOOTPATH
	109	#define CONFIG_BOOTP_GATEWAY
	110	#define CONFIG_BOOTP_HOSTNAME
	111
	112
6c4f4da9 JL	113	/*
	114	* Command line configuration.
	115	*/
	116	#include <config_cmd_default.h>
	117
	118	#define CONFIG_CMD_DHCP
	119	#define CONFIG_CMD_PCI
	120	#define CONFIG_CMD_IRQ
	121	#define CONFIG_CMD_IDE
	122	#define CONFIG_CMD_FAT
	123	#define CONFIG_CMD_EXT2
	124	#define CONFIG_CMD_ELF
	125	#define CONFIG_CMD_NAND
	126	#define CONFIG_CMD_I2C
	127	#define CONFIG_CMD_DATE
	128	#define CONFIG_CMD_MII
	129	#define CONFIG_CMD_PING
6c4f4da9 JL	130	#define CONFIG_CMD_EEPROM
6c4f4da9 JL	131
11799434 JL	132	#ifdef CONFIG_VIDEO
	133	#define CONFIG_CMD_BMP
	134	#endif
a20b27a3 SR	135
	136	#define CONFIG_MAC_PARTITION
	137	#define CONFIG_DOS_PARTITION
	138
	139	#define CONFIG_SUPPORT_VFAT
	140
	141	#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
	142	#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
	143
a20b27a3 SR	144	#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
	145	#undef CONFIG_WATCHDOG /* watchdog disabled */
	146
	147	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	148
	149	/*
	150	* Miscellaneous configurable options
	151	*/
	152	#define CFG_LONGHELP /* undef to save memory */
	153	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	154
	155	#undef CFG_HUSH_PARSER /* use "hush" command parser */
	156	#ifdef CFG_HUSH_PARSER
	157	#define CFG_PROMPT_HUSH_PS2 "> "
	158	#endif
	159
6c4f4da9	160	#if defined(CONFIG_CMD_KGDB)
a20b27a3 SR	161	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	162	#else
	163	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	164	#endif
	165	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	166	#define CFG_MAXARGS 16 /* max number of command args */
	167	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	168
	169	#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
	170
98f4a3df	171	#undef CFG_CONSOLE_INFO_QUIET /* print console @ startup */
a20b27a3 SR	172
	173	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
	174
	175	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	176	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	177
	178	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	179	#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	180	#define CFG_BASE_BAUD 691200
	181	#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
	182
	183	/* The following table includes the supported baudrates */
	184	#define CFG_BAUDRATE_TABLE \
	185	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	186	57600, 115200, 230400, 460800, 921600 }
	187
	188	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	189	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	190
	191	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	192
	193	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	194
	195	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	196
	197	#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
	198
98f4a3df SR	199	/*-----------------------------------------------------------------------
	200	* RTC stuff
	201	*-----------------------------------------------------------------------
	202	*/
	203	#define CONFIG_RTC_DS1338
	204	#define CFG_I2C_RTC_ADDR 0x68
	205
a20b27a3 SR	206	/*-----------------------------------------------------------------------
	207	* NAND-FLASH stuff
	208	*-----------------------------------------------------------------------
	209	*/
bd84ee4c MF	210	#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
	211	#define NAND_MAX_CHIPS 1
	212	#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
	213	#define NAND_BIG_DELAY_US 25
	214
	215	#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
	216	#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
	217	#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
	218	#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
a20b27a3	219
c750d2e6 MF	220	#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
c750d2e6 MF	221	#define CFG_NAND_QUIET 1
a20b27a3 SR	222
	223	/*-----------------------------------------------------------------------
	224	* PCI stuff
	225	*-----------------------------------------------------------------------
	226	*/
	227	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	228	#define PCI_HOST_FORCE 1 /* configure as pci host */
	229	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	230
	231	#define CONFIG_PCI /* include pci support */
	232	#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
	233	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	234	/* resource configuration */
	235
	236	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	237
	238	#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
	239
	240	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	241	#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	242	#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	243	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	244	#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
	245	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	246	#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	247	#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	248	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
	249
	250	/*-----------------------------------------------------------------------
	251	* IDE/ATA stuff
	252	*-----------------------------------------------------------------------
	253	*/
	254	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	255	#undef CONFIG_IDE_LED /* no led for ide supported */
	256	#define CONFIG_IDE_RESET 1 /* reset for ide supported */
	257
	258	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
	259	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 1 drives per IDE bus */
	260
	261	#define CFG_ATA_BASE_ADDR 0xF0100000
	262	#define CFG_ATA_IDE0_OFFSET 0x0000
	263
	264	#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
	265	#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
	266	#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
	267
	268	/*
	269	* For booting Linux, the board info and command line data
	270	* have to be in the first 8 MB of memory, since this is
	271	* the maximum mapped by the Linux kernel during initialization.
	272	*/
	273	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	274	/*-----------------------------------------------------------------------
	275	* FLASH organization
	276	*/
	277	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
	278
	279	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	280	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	281
	282	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	283	#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
	284
	285	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
286	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
287	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
288	/*
289	* The following defines are added for buggy IOP480 byte interface.
290	* All other boards should use the standard values (CPCI405 etc.)
291	*/
292	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
293	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
294	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
295
296	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
297
298	#if 0 /* test-only */
299	#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
300	#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
301	#endif
302
303	/*-----------------------------------------------------------------------
304	* Start addresses for the final memory configuration
305	* (Set up by the startup code)
306	* Please note that CFG_SDRAM_BASE _must_ start at 0
307	*/
308	#define CFG_SDRAM_BASE 0x00000000
309	#define CFG_FLASH_BASE 0xFFF80000
310	#define CFG_MONITOR_BASE TEXT_BASE
311	#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
c29ab9d7	312	#define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */
a20b27a3 SR	313
	314	#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
	315	# define CFG_RAMBOOT 1
	316	#else
	317	# undef CFG_RAMBOOT
	318	#endif
	319
	320	/*-----------------------------------------------------------------------
	321	* Environment Variable setup
	322	*/
bb1f8b4f	323	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
a20b27a3 SR	324	#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
	325	#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
	326	/* total size of a CAT24WC16 is 2048 bytes */
	327
	328	#define CFG_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */
	329	#define CFG_NVRAM_SIZE 0x8000 /* NVRAM size */
	330
	331	/*-----------------------------------------------------------------------
	332	* I2C EEPROM (CAT24WC16) for environment
	333	*/
	334	#define CONFIG_HARD_I2C /* I2c with hardware support */
	335	#if 0 /* test-only */
	336	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	337	#else
	338	#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
	339	#endif
	340	#define CFG_I2C_SLAVE 0x7F
	341
	342	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
98f4a3df SR	343	#define CFG_EEPROM_WREN 1
98f4a3df SR	344
a20b27a3 SR	345	#if 1 /* test-only */
	346	/* CAT24WC08/16... */
	347	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	348	/* mask of address bits that overflow into the "EEPROM chip address" */
	349	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	350	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	351	/* 16 byte page write mode using*/
	352	/* last 4 bits of the address */
	353	#else
	354	/* CAT24WC32/64... */
	355	#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
	356	/* mask of address bits that overflow into the "EEPROM chip address" */
	357	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
	358	#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
	359	/* 32 byte page write mode using*/
	360	/* last 5 bits of the address */
	361	#endif
	362	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	363	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	364
a20b27a3 SR	365	/*-----------------------------------------------------------------------
	366	* External Bus Controller (EBC) Setup
	367	*/
	368
	369	#define CAN_BA 0xF0000000 /* CAN Base Address */
	370	#define LCD_BA 0xF1000000 /* Epson LCD Base Address */
	371	#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
	372	#define CFG_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */
	373
	374	/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
	375	#define CFG_EBC_PB0AP 0x92015480
	376	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
	377
	378	/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */
	379	#define CFG_EBC_PB1AP 0x92015480
	380	#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
	381
	382	/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
	383	#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	384	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
	385
	386	/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
	387	#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	388	#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
	389
	390	/* Memory Bank 4 (Epson LCD) initialization */
	391	#define CFG_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
	392	#define CFG_EBC_PB4CR LCD_BA \| 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
	393
	394	/*-----------------------------------------------------------------------
	395	* LCD Setup
	396	*/
	397
	398	#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
	399	#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
	400	#define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
	401	#define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
	402
a20b27a3 SR	403	/*-----------------------------------------------------------------------
	404	* Universal Interrupt Controller (UIC) Setup
	405	*/
	406
	407	/*
	408	* define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
	409	*/
d1631fe1	410	#define CFG_UIC0_POLARITY (0xFFFFFF80 \| UIC_MASK(VECNUM_EIRQ6))
a20b27a3 SR	411
	412	/*-----------------------------------------------------------------------
	413	* FPGA stuff
	414	*/
	415
	416	#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
	417
	418	/* FPGA internal regs */
	419	#define CFG_FPGA_CTRL 0x000
	420
	421	/* FPGA Control Reg */
	422	#define CFG_FPGA_CTRL_REV0 0x0001
	423	#define CFG_FPGA_CTRL_REV1 0x0002
	424	#define CFG_FPGA_CTRL_VGA0_BL 0x0004
	425	#define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
	426	#define CFG_FPGA_CTRL_CF_RESET 0x0040
	427	#define CFG_FPGA_CTRL_PS2_PWR 0x0080
48a05a51	428	#define CFG_FPGA_CTRL_CF_PWRN 0x0100 /* low active */
a20b27a3 SR	429	#define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
a20b27a3 SR	430	#define CFG_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */
48a05a51 SR	431	#define CFG_FPGA_CTRL_OW_ENABLE 0x8000
	432
	433	#define CFG_FPGA_STATUS_CF_DETECT 0x8000
a20b27a3 SR	434
	435	#define LCD_CLK_OFF 0x0000 /* Off */
	436	#define LCD_CLK_02083 0x1000 /* 2.083 MHz */
	437	#define LCD_CLK_03135 0x2000 /* 3.135 MHz */
	438	#define LCD_CLK_04165 0x3000 /* 4.165 MHz */
	439	#define LCD_CLK_06250 0x4000 /* 6.250 MHz */
	440	#define LCD_CLK_08330 0x5000 /* 8.330 MHz */
	441	#define LCD_CLK_12500 0x6000 /* 12.50 MHz */
	442	#define LCD_CLK_25000 0x7000 /* 25.00 MHz */
	443
	444	#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
	445	#define CFG_FPGA_MAX_SIZE 1281024 / 128kByte is enough for XC2S50E*/
	446
	447	/* FPGA program pin configuration */
	448	#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	449	#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	450	#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	451	#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
	452	#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
	453
	454	/*-----------------------------------------------------------------------
	455	* Definitions for initial stack pointer and data area (in data cache)
	456	*/
	457	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
	458	#define CFG_TEMP_STACK_OCM 1
	459
	460	/* On Chip Memory location */
	461	#define CFG_OCM_DATA_ADDR 0xF8000000
	462	#define CFG_OCM_DATA_SIZE 0x1000
	463	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
	464	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
	465
	466	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	467	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	468	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	469
	470	/*-----------------------------------------------------------------------
	471	* Definitions for GPIO setup (PPC405EP specific)
	472	*
	473	* GPIO0[0] - External Bus Controller BLAST output
	474	* GPIO0[1-9] - Instruction trace outputs -> GPIO
	475	* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
	476	* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
	477	* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
	478	* GPIO0[24-27] - UART0 control signal inputs/outputs
	479	* GPIO0[28-29] - UART1 data signal input/output
	480	* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
	481	*/
	482	#define CFG_GPIO0_OSRH 0x40000550
	483	#define CFG_GPIO0_OSRL 0x00000110
	484	#define CFG_GPIO0_ISR1H 0x00000000
	485	#define CFG_GPIO0_ISR1L 0x15555440
	486	#define CFG_GPIO0_TSRH 0x00000000
	487	#define CFG_GPIO0_TSRL 0x00000000
	488	#define CFG_GPIO0_TCR 0xF7FE0017
	489
	490	#define CFG_LCD_ENDIAN (0x80000000 >> 7)
98f4a3df SR	491	#define CFG_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
98f4a3df SR	492	#define CFG_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */
a20b27a3 SR	493	#define CFG_LCD0_RST (0x80000000 >> 30)
	494	#define CFG_LCD1_RST (0x80000000 >> 31)
	495
	496	/*
	497	* Internal Definitions
	498	*
	499	* Boot Flags
	500	*/
	501	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	502	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	503
	504	/*
	505	* Default speed selection (cpu_plb_opb_ebc) in mhz.
	506	* This value will be set if iic boot eprom is disabled.
	507	*/
	508	#if 0
	509	#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
	510	#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
	511	#endif
	512	#if 0
	513	#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
	514	#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
	515	#endif
	516	#if 1
	517	#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
	518	#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
	519	#endif
	520
	521	#endif /* __CONFIG_H */