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a20b27a3 SR |
1 | /* |
2 | * (C) Copyright 2001-2004 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
98f4a3df SR |
5 | * (C) Copyright 2005 |
6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
7 | * | |
48a05a51 SR |
8 | * (C) Copyright 2006 |
9 | * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com | |
10 | * | |
a20b27a3 SR |
11 | * See file CREDITS for list of people who contributed to this |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | /* | |
31 | * board/config.h - configuration options, board specific | |
32 | */ | |
33 | ||
34 | #ifndef __CONFIG_H | |
35 | #define __CONFIG_H | |
36 | ||
37 | /* | |
38 | * High Level Configuration Options | |
39 | * (easy to change) | |
40 | */ | |
41 | ||
42 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
43 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
44 | #define CONFIG_HH405 1 /* ...on a HH405 board */ | |
45 | ||
46 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ | |
47 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
48 | ||
49 | #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ | |
50 | ||
51 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
52 | ||
53 | #define CONFIG_BAUDRATE 9600 | |
54 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
55 | ||
56 | #undef CONFIG_BOOTARGS | |
57 | #undef CONFIG_BOOTCOMMAND | |
58 | ||
59 | #define CONFIG_PREBOOT "autoupd" | |
60 | ||
2c7b2ab5 SR |
61 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
62 | "pciconfighost=1\0" \ | |
63 | "" | |
64 | ||
a20b27a3 SR |
65 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
66 | ||
48a05a51 SR |
67 | #define CONFIG_NET_MULTI 1 |
68 | #undef CONFIG_HAS_ETH1 | |
69 | ||
a20b27a3 | 70 | #define CONFIG_MII 1 /* MII PHY management */ |
48a05a51 | 71 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 72 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
48a05a51 | 73 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
a20b27a3 SR |
74 | |
75 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ | |
76 | ||
98f4a3df SR |
77 | /* |
78 | * Video console | |
79 | */ | |
2c7b2ab5 SR |
80 | #define CONFIG_VIDEO /* for sm501 video support */ |
81 | ||
82 | #ifdef CONFIG_VIDEO | |
98f4a3df SR |
83 | #define CONFIG_VIDEO_SM501 |
84 | #if 0 | |
85 | #define CONFIG_VIDEO_SM501_32BPP | |
86 | #else | |
87 | #define CONFIG_VIDEO_SM501_16BPP | |
88 | #endif | |
48a05a51 | 89 | #define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 |
98f4a3df SR |
90 | #define CONFIG_CFB_CONSOLE |
91 | #define CONFIG_VIDEO_LOGO | |
92 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
93 | #define CONFIG_CONSOLE_EXTRA_INFO | |
94 | #define CONFIG_VIDEO_SW_CURSOR | |
95 | #define CONFIG_SPLASH_SCREEN | |
96 | #define CFG_CONSOLE_IS_IN_ENV | |
97 | #define CONFIG_SPLASH_SCREEN | |
98 | #define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ | |
c29ab9d7 | 99 | #define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */ |
98f4a3df | 100 | |
98f4a3df SR |
101 | #define ADD_BMP_CMD CFG_CMD_BMP |
102 | #else | |
103 | #define ADD_BMP_CMD 0 | |
2c7b2ab5 | 104 | #endif /* CONFIG_VIDEO */ |
98f4a3df | 105 | |
a20b27a3 SR |
106 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
107 | CFG_CMD_DHCP | \ | |
108 | CFG_CMD_PCI | \ | |
109 | CFG_CMD_IRQ | \ | |
110 | CFG_CMD_IDE | \ | |
111 | CFG_CMD_FAT | \ | |
98f4a3df | 112 | CFG_CMD_EXT2 | \ |
a20b27a3 SR |
113 | CFG_CMD_ELF | \ |
114 | CFG_CMD_NAND | \ | |
115 | CFG_CMD_I2C | \ | |
98f4a3df | 116 | CFG_CMD_DATE | \ |
a20b27a3 SR |
117 | CFG_CMD_MII | \ |
118 | CFG_CMD_PING | \ | |
98f4a3df | 119 | ADD_BMP_CMD | \ |
a20b27a3 SR |
120 | CFG_CMD_EEPROM ) |
121 | ||
122 | #define CONFIG_MAC_PARTITION | |
123 | #define CONFIG_DOS_PARTITION | |
124 | ||
125 | #define CONFIG_SUPPORT_VFAT | |
126 | ||
127 | #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ | |
128 | #undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ | |
129 | ||
130 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
131 | #include <cmd_confdefs.h> | |
132 | ||
133 | #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ | |
134 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
135 | ||
136 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
137 | ||
138 | /* | |
139 | * Miscellaneous configurable options | |
140 | */ | |
141 | #define CFG_LONGHELP /* undef to save memory */ | |
142 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
143 | ||
144 | #undef CFG_HUSH_PARSER /* use "hush" command parser */ | |
145 | #ifdef CFG_HUSH_PARSER | |
146 | #define CFG_PROMPT_HUSH_PS2 "> " | |
147 | #endif | |
148 | ||
149 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
150 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
151 | #else | |
152 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
153 | #endif | |
154 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
155 | #define CFG_MAXARGS 16 /* max number of command args */ | |
156 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
157 | ||
158 | #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ | |
159 | ||
98f4a3df | 160 | #undef CFG_CONSOLE_INFO_QUIET /* print console @ startup */ |
a20b27a3 SR |
161 | |
162 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ | |
163 | ||
164 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
165 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
166 | ||
167 | #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ | |
168 | #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ | |
169 | #define CFG_BASE_BAUD 691200 | |
170 | #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ | |
171 | ||
172 | /* The following table includes the supported baudrates */ | |
173 | #define CFG_BAUDRATE_TABLE \ | |
174 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ | |
175 | 57600, 115200, 230400, 460800, 921600 } | |
176 | ||
177 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
178 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
179 | ||
180 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
181 | ||
182 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
183 | ||
184 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
185 | ||
186 | #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ | |
187 | ||
98f4a3df SR |
188 | /*----------------------------------------------------------------------- |
189 | * RTC stuff | |
190 | *----------------------------------------------------------------------- | |
191 | */ | |
192 | #define CONFIG_RTC_DS1338 | |
193 | #define CFG_I2C_RTC_ADDR 0x68 | |
194 | ||
a20b27a3 SR |
195 | /*----------------------------------------------------------------------- |
196 | * NAND-FLASH stuff | |
197 | *----------------------------------------------------------------------- | |
198 | */ | |
199 | #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
200 | #define SECTORSIZE 512 | |
201 | ||
202 | #define ADDR_COLUMN 1 | |
203 | #define ADDR_PAGE 2 | |
204 | #define ADDR_COLUMN_PAGE 3 | |
205 | ||
206 | #define NAND_ChipID_UNKNOWN 0x00 | |
207 | #define NAND_MAX_FLOORS 1 | |
208 | #define NAND_MAX_CHIPS 1 | |
209 | ||
210 | #define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ | |
211 | #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
212 | #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
213 | #define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
214 | ||
215 | #define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) | |
216 | #define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) | |
217 | #define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) | |
218 | #define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) | |
219 | #define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) | |
220 | #define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) | |
221 | #define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) | |
222 | ||
223 | #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) | |
224 | #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) | |
225 | #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) | |
226 | #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) | |
227 | ||
228 | #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ | |
229 | ||
230 | /*----------------------------------------------------------------------- | |
231 | * PCI stuff | |
232 | *----------------------------------------------------------------------- | |
233 | */ | |
234 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
235 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
236 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
237 | ||
238 | #define CONFIG_PCI /* include pci support */ | |
239 | #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ | |
240 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
241 | /* resource configuration */ | |
242 | ||
243 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
244 | ||
245 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
246 | ||
247 | #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ | |
248 | #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
249 | #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
250 | #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
251 | #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
252 | #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
253 | #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
254 | #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
255 | #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
256 | ||
257 | /*----------------------------------------------------------------------- | |
258 | * IDE/ATA stuff | |
259 | *----------------------------------------------------------------------- | |
260 | */ | |
261 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
262 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
263 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ | |
264 | ||
265 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ | |
266 | #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ | |
267 | ||
268 | #define CFG_ATA_BASE_ADDR 0xF0100000 | |
269 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
270 | ||
271 | #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ | |
272 | #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
273 | #define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
274 | ||
275 | /* | |
276 | * For booting Linux, the board info and command line data | |
277 | * have to be in the first 8 MB of memory, since this is | |
278 | * the maximum mapped by the Linux kernel during initialization. | |
279 | */ | |
280 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
281 | /*----------------------------------------------------------------------- | |
282 | * FLASH organization | |
283 | */ | |
284 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ | |
285 | ||
286 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
287 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
288 | ||
289 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
290 | #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
291 | ||
292 | #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ | |
293 | #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
294 | #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
295 | /* | |
296 | * The following defines are added for buggy IOP480 byte interface. | |
297 | * All other boards should use the standard values (CPCI405 etc.) | |
298 | */ | |
299 | #define CFG_FLASH_READ0 0x0000 /* 0 is standard */ | |
300 | #define CFG_FLASH_READ1 0x0001 /* 1 is standard */ | |
301 | #define CFG_FLASH_READ2 0x0002 /* 2 is standard */ | |
302 | ||
303 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
304 | ||
305 | #if 0 /* test-only */ | |
306 | #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ | |
307 | #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ | |
308 | #endif | |
309 | ||
310 | /*----------------------------------------------------------------------- | |
311 | * Start addresses for the final memory configuration | |
312 | * (Set up by the startup code) | |
313 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
314 | */ | |
315 | #define CFG_SDRAM_BASE 0x00000000 | |
316 | #define CFG_FLASH_BASE 0xFFF80000 | |
317 | #define CFG_MONITOR_BASE TEXT_BASE | |
318 | #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ | |
c29ab9d7 | 319 | #define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */ |
a20b27a3 SR |
320 | |
321 | #if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) | |
322 | # define CFG_RAMBOOT 1 | |
323 | #else | |
324 | # undef CFG_RAMBOOT | |
325 | #endif | |
326 | ||
327 | /*----------------------------------------------------------------------- | |
328 | * Environment Variable setup | |
329 | */ | |
330 | #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ | |
331 | #define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ | |
332 | #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ | |
333 | /* total size of a CAT24WC16 is 2048 bytes */ | |
334 | ||
335 | #define CFG_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */ | |
336 | #define CFG_NVRAM_SIZE 0x8000 /* NVRAM size */ | |
337 | ||
338 | /*----------------------------------------------------------------------- | |
339 | * I2C EEPROM (CAT24WC16) for environment | |
340 | */ | |
341 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
342 | #if 0 /* test-only */ | |
343 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
344 | #else | |
345 | #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ | |
346 | #endif | |
347 | #define CFG_I2C_SLAVE 0x7F | |
348 | ||
349 | #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ | |
98f4a3df SR |
350 | #define CFG_EEPROM_WREN 1 |
351 | ||
a20b27a3 SR |
352 | #if 1 /* test-only */ |
353 | /* CAT24WC08/16... */ | |
354 | #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
355 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
356 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 | |
357 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
358 | /* 16 byte page write mode using*/ | |
359 | /* last 4 bits of the address */ | |
360 | #else | |
361 | /* CAT24WC32/64... */ | |
362 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
363 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
364 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 | |
365 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ | |
366 | /* 32 byte page write mode using*/ | |
367 | /* last 5 bits of the address */ | |
368 | #endif | |
369 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
370 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
371 | ||
372 | /*----------------------------------------------------------------------- | |
373 | * Cache Configuration | |
374 | */ | |
0c8721a4 | 375 | #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ |
a20b27a3 SR |
376 | /* have only 8kB, 16kB is save here */ |
377 | #define CFG_CACHELINE_SIZE 32 /* ... */ | |
378 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
379 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
380 | #endif | |
381 | ||
382 | /*----------------------------------------------------------------------- | |
383 | * External Bus Controller (EBC) Setup | |
384 | */ | |
385 | ||
386 | #define CAN_BA 0xF0000000 /* CAN Base Address */ | |
387 | #define LCD_BA 0xF1000000 /* Epson LCD Base Address */ | |
388 | #define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ | |
389 | #define CFG_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */ | |
390 | ||
391 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
392 | #define CFG_EBC_PB0AP 0x92015480 | |
393 | #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
394 | ||
395 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */ | |
396 | #define CFG_EBC_PB1AP 0x92015480 | |
397 | #define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ | |
398 | ||
399 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ | |
400 | #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
401 | #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
402 | ||
403 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ | |
404 | #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
405 | #define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
406 | ||
407 | /* Memory Bank 4 (Epson LCD) initialization */ | |
408 | #define CFG_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ | |
409 | #define CFG_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ | |
410 | ||
411 | /*----------------------------------------------------------------------- | |
412 | * LCD Setup | |
413 | */ | |
414 | ||
415 | #define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ | |
416 | #define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ | |
417 | #define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ | |
418 | #define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ | |
419 | ||
a20b27a3 SR |
420 | /*----------------------------------------------------------------------- |
421 | * Universal Interrupt Controller (UIC) Setup | |
422 | */ | |
423 | ||
424 | /* | |
425 | * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high | |
426 | */ | |
427 | #define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_EXT6) | |
428 | ||
429 | /*----------------------------------------------------------------------- | |
430 | * FPGA stuff | |
431 | */ | |
432 | ||
433 | #define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ | |
434 | ||
435 | /* FPGA internal regs */ | |
436 | #define CFG_FPGA_CTRL 0x000 | |
437 | ||
438 | /* FPGA Control Reg */ | |
439 | #define CFG_FPGA_CTRL_REV0 0x0001 | |
440 | #define CFG_FPGA_CTRL_REV1 0x0002 | |
441 | #define CFG_FPGA_CTRL_VGA0_BL 0x0004 | |
442 | #define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008 | |
443 | #define CFG_FPGA_CTRL_CF_RESET 0x0040 | |
444 | #define CFG_FPGA_CTRL_PS2_PWR 0x0080 | |
48a05a51 | 445 | #define CFG_FPGA_CTRL_CF_PWRN 0x0100 /* low active */ |
a20b27a3 SR |
446 | #define CFG_FPGA_CTRL_CF_BUS_EN 0x0200 |
447 | #define CFG_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */ | |
48a05a51 SR |
448 | #define CFG_FPGA_CTRL_OW_ENABLE 0x8000 |
449 | ||
450 | #define CFG_FPGA_STATUS_CF_DETECT 0x8000 | |
a20b27a3 SR |
451 | |
452 | #define LCD_CLK_OFF 0x0000 /* Off */ | |
453 | #define LCD_CLK_02083 0x1000 /* 2.083 MHz */ | |
454 | #define LCD_CLK_03135 0x2000 /* 3.135 MHz */ | |
455 | #define LCD_CLK_04165 0x3000 /* 4.165 MHz */ | |
456 | #define LCD_CLK_06250 0x4000 /* 6.250 MHz */ | |
457 | #define LCD_CLK_08330 0x5000 /* 8.330 MHz */ | |
458 | #define LCD_CLK_12500 0x6000 /* 12.50 MHz */ | |
459 | #define LCD_CLK_25000 0x7000 /* 25.00 MHz */ | |
460 | ||
461 | #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ | |
462 | #define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
463 | ||
464 | /* FPGA program pin configuration */ | |
465 | #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ | |
466 | #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
467 | #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
468 | #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
469 | #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
470 | ||
471 | /*----------------------------------------------------------------------- | |
472 | * Definitions for initial stack pointer and data area (in data cache) | |
473 | */ | |
474 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
475 | #define CFG_TEMP_STACK_OCM 1 | |
476 | ||
477 | /* On Chip Memory location */ | |
478 | #define CFG_OCM_DATA_ADDR 0xF8000000 | |
479 | #define CFG_OCM_DATA_SIZE 0x1000 | |
480 | #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ | |
481 | #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ | |
482 | ||
483 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
484 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
485 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
486 | ||
487 | /*----------------------------------------------------------------------- | |
488 | * Definitions for GPIO setup (PPC405EP specific) | |
489 | * | |
490 | * GPIO0[0] - External Bus Controller BLAST output | |
491 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
492 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs | |
493 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
494 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
495 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
496 | * GPIO0[28-29] - UART1 data signal input/output | |
497 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs | |
498 | */ | |
499 | #define CFG_GPIO0_OSRH 0x40000550 | |
500 | #define CFG_GPIO0_OSRL 0x00000110 | |
501 | #define CFG_GPIO0_ISR1H 0x00000000 | |
502 | #define CFG_GPIO0_ISR1L 0x15555440 | |
503 | #define CFG_GPIO0_TSRH 0x00000000 | |
504 | #define CFG_GPIO0_TSRL 0x00000000 | |
505 | #define CFG_GPIO0_TCR 0xF7FE0017 | |
506 | ||
507 | #define CFG_LCD_ENDIAN (0x80000000 >> 7) | |
98f4a3df SR |
508 | #define CFG_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ |
509 | #define CFG_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */ | |
a20b27a3 SR |
510 | #define CFG_LCD0_RST (0x80000000 >> 30) |
511 | #define CFG_LCD1_RST (0x80000000 >> 31) | |
512 | ||
513 | /* | |
514 | * Internal Definitions | |
515 | * | |
516 | * Boot Flags | |
517 | */ | |
518 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
519 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
520 | ||
521 | /* | |
522 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
523 | * This value will be set if iic boot eprom is disabled. | |
524 | */ | |
525 | #if 0 | |
526 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 | |
527 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
528 | #endif | |
529 | #if 0 | |
530 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 | |
531 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
532 | #endif | |
533 | #if 1 | |
534 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 | |
535 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
536 | #endif | |
537 | ||
538 | #endif /* __CONFIG_H */ |