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756f586a WD |
1 | /* |
2 | * (C) Copyright 2004 | |
3 | * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com | |
4 | * | |
5 | * (C) Copyright 2001, 2002 | |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* ------------------------------------------------------------------------- */ | |
28 | ||
29 | /* | |
30 | * board/config.h - configuration options, board specific | |
31 | */ | |
32 | ||
33 | #ifndef __CONFIG_H | |
34 | #define __CONFIG_H | |
35 | ||
36 | /* | |
37 | * High Level Configuration Options | |
38 | * (easy to change) | |
39 | */ | |
40 | ||
41 | #define CONFIG_MPC824X 1 | |
42 | #define CONFIG_MPC8245 1 | |
43 | #define CONFIG_HIDDEN_DRAGON 1 | |
44 | ||
45 | #if 0 | |
46 | #define USE_DINK32 1 | |
47 | #else | |
48 | #undef USE_DINK32 | |
49 | #endif | |
50 | ||
51 | #define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ | |
52 | #define CONFIG_BAUDRATE 9600 | |
53 | #define CONFIG_DRAM_SPEED 100 /* MHz */ | |
54 | ||
756f586a | 55 | |
11799434 JL |
56 | /* |
57 | * BOOTP options | |
58 | */ | |
59 | #define CONFIG_BOOTP_BOOTFILESIZE | |
60 | #define CONFIG_BOOTP_BOOTPATH | |
61 | #define CONFIG_BOOTP_GATEWAY | |
62 | #define CONFIG_BOOTP_HOSTNAME | |
63 | ||
64 | ||
6c4f4da9 JL |
65 | /* |
66 | * Command line configuration. | |
67 | */ | |
68 | #include <config_cmd_default.h> | |
69 | ||
70 | #define CONFIG_CMD_EEPROM | |
71 | #define CONFIG_CMD_ELF | |
72 | #define CONFIG_CMD_I2C | |
73 | #define CONFIG_CMD_NET | |
74 | #define CONFIG_CMD_PCI | |
75 | #define CONFIG_CMD_PING | |
756f586a WD |
76 | |
77 | /* | |
78 | * Miscellaneous configurable options | |
79 | */ | |
6d0f6bcf JCPV |
80 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
81 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
82 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
83 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
84 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
85 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
86 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ | |
87 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
756f586a WD |
88 | |
89 | /*----------------------------------------------------------------------- | |
90 | * PCI stuff | |
91 | *----------------------------------------------------------------------- | |
92 | */ | |
93 | #define CONFIG_PCI /* include pci support */ | |
94 | #undef CONFIG_PCI_PNP | |
95 | ||
96 | #define CONFIG_NET_MULTI /* Multi ethernet cards support */ | |
97 | ||
6d0f6bcf | 98 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
756f586a WD |
99 | |
100 | #define PCI_ENET0_IOADDR 0x80000000 | |
101 | #define PCI_ENET0_MEMADDR 0x80000000 | |
102 | #define PCI_ENET1_IOADDR 0x81000000 | |
103 | #define PCI_ENET1_MEMADDR 0x81000000 | |
104 | ||
105 | #define CONFIG_RTL8139 | |
890d242f | 106 | |
756f586a WD |
107 | /* Make sure the ethaddr can be overwritten |
108 | TODO: Remove this on final product | |
109 | */ | |
110 | #define CONFIG_ENV_OVERWRITE | |
111 | ||
112 | /*----------------------------------------------------------------------- | |
113 | * Start addresses for the final memory configuration | |
114 | * (Set up by the startup code) | |
6d0f6bcf | 115 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
756f586a | 116 | */ |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
118 | #define CONFIG_SYS_MAX_RAM_SIZE 0x02000000 | |
756f586a | 119 | |
6d0f6bcf | 120 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
756f586a WD |
121 | |
122 | #if defined (USE_DINK32) | |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_MONITOR_LEN 0x00030000 |
124 | #define CONFIG_SYS_MONITOR_BASE 0x00090000 | |
125 | #define CONFIG_SYS_RAMBOOT 1 | |
126 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
127 | #define CONFIG_SYS_INIT_RAM_END 0x10000 | |
128 | #define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ | |
129 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
130 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
756f586a | 131 | #else |
6d0f6bcf JCPV |
132 | #undef CONFIG_SYS_RAMBOOT |
133 | #define CONFIG_SYS_MONITOR_LEN 0x00030000 | |
134 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
756f586a | 135 | |
6d0f6bcf | 136 | #define CONFIG_SYS_GBL_DATA_SIZE 128 |
756f586a | 137 | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
139 | #define CONFIG_SYS_INIT_RAM_END 0x1000 | |
140 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
756f586a WD |
141 | |
142 | #endif | |
143 | ||
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_FLASH_BASE 0xFFE00000 |
145 | #define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */ | |
5a1aceb0 | 146 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
147 | #define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ |
148 | #define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ | |
756f586a | 149 | |
6d0f6bcf | 150 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ |
756f586a | 151 | |
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
153 | #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ | |
756f586a | 154 | |
6d0f6bcf | 155 | #define CONFIG_SYS_EUMB_ADDR 0xFC000000 |
756f586a | 156 | |
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_ISA_MEM 0xFD000000 |
158 | #define CONFIG_SYS_ISA_IO 0xFE000000 | |
756f586a | 159 | |
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */ |
161 | #define CONFIG_SYS_FLASH_RANGE_SIZE 0x00200000 | |
756f586a WD |
162 | #define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */ |
163 | ||
164 | /* | |
165 | * select i2c support configuration | |
166 | * | |
167 | * Supported configurations are {none, software, hardware} drivers. | |
168 | * If the software driver is chosen, there are some additional | |
169 | * configuration items that the driver uses to drive the port pins. | |
170 | */ | |
171 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ | |
172 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
174 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
756f586a WD |
175 | |
176 | #ifdef CONFIG_SOFT_I2C | |
177 | #error "Soft I2C is not configured properly. Please review!" | |
178 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
179 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
180 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
181 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
182 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
183 | else iop->pdat &= ~0x00010000 | |
184 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
185 | else iop->pdat &= ~0x00020000 | |
186 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
187 | #endif /* CONFIG_SOFT_I2C */ | |
188 | ||
6d0f6bcf JCPV |
189 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ |
190 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
191 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
192 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
756f586a | 193 | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
195 | #define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM } | |
756f586a WD |
196 | |
197 | /*----------------------------------------------------------------------- | |
198 | * Definitions for initial stack pointer and data area (in DPRAM) | |
199 | */ | |
200 | ||
201 | ||
ab6878c7 | 202 | #define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */ |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ |
204 | #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ | |
205 | #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ | |
756f586a | 206 | |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
208 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ | |
756f586a WD |
209 | |
210 | /* TODO: Change this to VIA686A */ | |
211 | ||
212 | /* | |
213 | * NS87308 Configuration | |
214 | */ | |
55d6d2d3 | 215 | #define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ |
756f586a | 216 | |
6d0f6bcf | 217 | #define CONFIG_SYS_NS87308_BADDR_10 1 |
756f586a | 218 | |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ |
220 | CONFIG_SYS_NS87308_UART2 | \ | |
221 | CONFIG_SYS_NS87308_POWRMAN | \ | |
222 | CONFIG_SYS_NS87308_RTC_APC ) | |
756f586a | 223 | |
6d0f6bcf | 224 | #undef CONFIG_SYS_NS87308_PS2MOD |
756f586a | 225 | |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_NS87308_CS0_BASE 0x0076 |
227 | #define CONFIG_SYS_NS87308_CS0_CONF 0x30 | |
228 | #define CONFIG_SYS_NS87308_CS1_BASE 0x0075 | |
229 | #define CONFIG_SYS_NS87308_CS1_CONF 0x30 | |
230 | #define CONFIG_SYS_NS87308_CS2_BASE 0x0074 | |
231 | #define CONFIG_SYS_NS87308_CS2_CONF 0x30 | |
756f586a WD |
232 | |
233 | /* | |
234 | * NS16550 Configuration | |
235 | */ | |
6d0f6bcf JCPV |
236 | #define CONFIG_SYS_NS16550 |
237 | #define CONFIG_SYS_NS16550_SERIAL | |
756f586a | 238 | |
6d0f6bcf | 239 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
756f586a WD |
240 | |
241 | #if (CONFIG_CONS_INDEX > 2) | |
6d0f6bcf | 242 | #define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000 |
756f586a | 243 | #else |
6d0f6bcf | 244 | #define CONFIG_SYS_NS16550_CLK 1843200 |
756f586a WD |
245 | #endif |
246 | ||
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) |
248 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) | |
249 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500) | |
250 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600) | |
756f586a WD |
251 | |
252 | /* | |
253 | * Low Level Configuration Settings | |
254 | * (address mappings, register initial values, etc.) | |
255 | * You should know what you are doing if you make changes here. | |
256 | */ | |
257 | ||
258 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
259 | ||
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ |
261 | #define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ | |
756f586a | 262 | |
6d0f6bcf | 263 | #define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ |
756f586a WD |
264 | |
265 | /* the following are for SDRAM only*/ | |
6d0f6bcf JCPV |
266 | #define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ |
267 | #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ | |
268 | #define CONFIG_SYS_RDLAT 4 /* data latency from read command */ | |
269 | #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ | |
270 | #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ | |
271 | #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ | |
272 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ | |
273 | #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ | |
756f586a | 274 | #if 0 |
6d0f6bcf | 275 | #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ |
756f586a WD |
276 | #endif |
277 | ||
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 |
279 | #define CONFIG_SYS_EXTROM 1 | |
280 | #define CONFIG_SYS_REGDIMM 0 | |
756f586a WD |
281 | |
282 | ||
283 | /* memory bank settings*/ | |
284 | /* | |
285 | * only bits 20-29 are actually used from these vales to set the | |
286 | * start/end address the upper two bits will be 0, and the lower 20 | |
287 | * bits will be set to 0x00000 for a start address, or 0xfffff for an | |
288 | * end address | |
289 | */ | |
6d0f6bcf JCPV |
290 | #define CONFIG_SYS_BANK0_START 0x00000000 |
291 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) | |
292 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
293 | #define CONFIG_SYS_BANK1_START 0x3ff00000 | |
294 | #define CONFIG_SYS_BANK1_END 0x3fffffff | |
295 | #define CONFIG_SYS_BANK1_ENABLE 0 | |
296 | #define CONFIG_SYS_BANK2_START 0x3ff00000 | |
297 | #define CONFIG_SYS_BANK2_END 0x3fffffff | |
298 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
299 | #define CONFIG_SYS_BANK3_START 0x3ff00000 | |
300 | #define CONFIG_SYS_BANK3_END 0x3fffffff | |
301 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
302 | #define CONFIG_SYS_BANK4_START 0x00000000 | |
303 | #define CONFIG_SYS_BANK4_END 0x00000000 | |
304 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
305 | #define CONFIG_SYS_BANK5_START 0x00000000 | |
306 | #define CONFIG_SYS_BANK5_END 0x00000000 | |
307 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
308 | #define CONFIG_SYS_BANK6_START 0x00000000 | |
309 | #define CONFIG_SYS_BANK6_END 0x00000000 | |
310 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
311 | #define CONFIG_SYS_BANK7_START 0x00000000 | |
312 | #define CONFIG_SYS_BANK7_END 0x00000000 | |
313 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
756f586a WD |
314 | /* |
315 | * Memory bank enable bitmask, specifying which of the banks defined above | |
316 | are actually present. MSB is for bank #7, LSB is for bank #0. | |
317 | */ | |
6d0f6bcf | 318 | #define CONFIG_SYS_BANK_ENABLE 0x01 |
756f586a | 319 | |
6d0f6bcf | 320 | #define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ |
756f586a | 321 | /* see 8240 book for bit definitions */ |
6d0f6bcf | 322 | #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ |
756f586a WD |
323 | /* currently accessed page in memory */ |
324 | /* see 8240 book for details */ | |
325 | ||
326 | /* SDRAM 0 - 256MB */ | |
6d0f6bcf JCPV |
327 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
328 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
756f586a WD |
329 | |
330 | /* stack in DCACHE @ 1GB (no backing mem) */ | |
331 | #if defined(USE_DINK32) | |
6d0f6bcf JCPV |
332 | #define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) |
333 | #define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) | |
756f586a | 334 | #else |
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) |
336 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
756f586a WD |
337 | #endif |
338 | ||
339 | /* PCI memory */ | |
6d0f6bcf JCPV |
340 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
341 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
756f586a WD |
342 | |
343 | /* Flash, config addrs, etc */ | |
6d0f6bcf JCPV |
344 | #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
345 | #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
346 | ||
347 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
348 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
349 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
350 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
351 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
352 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
353 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
354 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
756f586a WD |
355 | |
356 | /* | |
357 | * For booting Linux, the board info and command line data | |
358 | * have to be in the first 8 MB of memory, since this is | |
359 | * the maximum mapped by the Linux kernel during initialization. | |
360 | */ | |
6d0f6bcf | 361 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
756f586a WD |
362 | /*----------------------------------------------------------------------- |
363 | * FLASH organization | |
364 | */ | |
6d0f6bcf JCPV |
365 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
366 | #define CONFIG_SYS_MAX_FLASH_SECT 36 /* max number of sectors on one chip */ | |
756f586a | 367 | |
6d0f6bcf JCPV |
368 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
369 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
756f586a WD |
370 | |
371 | /*----------------------------------------------------------------------- | |
372 | * Cache Configuration | |
373 | */ | |
6d0f6bcf | 374 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ |
6c4f4da9 | 375 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 376 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
756f586a WD |
377 | #endif |
378 | ||
379 | /* | |
380 | * Internal Definitions | |
381 | * | |
382 | * Boot Flags | |
383 | */ | |
384 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
385 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
386 | ||
387 | /* values according to the manual */ | |
388 | #define CONFIG_DRAM_50MHZ 1 | |
389 | #define CONFIG_SDRAM_50MHZ | |
390 | ||
391 | #undef NR_8259_INTS | |
392 | #define NR_8259_INTS 1 | |
393 | ||
394 | #define CONFIG_DISK_SPINUP_TIME 1000000 | |
395 | ||
396 | #endif /* __CONFIG_H */ |