[people/ms/u-boot.git] / include / configs / HIDDEN_DRAGON.h

/*
 * (C) Copyright 2004
 * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
 *
 * (C) Copyright 2001, 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_HIDDEN_DRAGON	1

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

#if 0
#define USE_DINK32		1
#else
#undef USE_DINK32
#endif

#define CONFIG_CONS_INDEX	3		/* set to '3' for on-chip DUART */
#define CONFIG_BAUDRATE		9600
#define CONFIG_DRAM_SPEED	100		/* MHz				*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI				/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#undef CONFIG_PCI_PNP


#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/

#define PCI_ENET0_IOADDR	0x80000000
#define PCI_ENET0_MEMADDR	0x80000000
#define PCI_ENET1_IOADDR	0x81000000
#define PCI_ENET1_MEMADDR	0x81000000

#define CONFIG_RTL8139

/* Make sure the ethaddr can be overwritten
   TODO: Remove this on final product
*/
#define CONFIG_ENV_OVERWRITE

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_MAX_RAM_SIZE	0x02000000

#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100

#if defined (USE_DINK32)
#define CONFIG_SYS_MONITOR_LEN		0x00030000
#define CONFIG_SYS_MONITOR_BASE	0x00090000
#define CONFIG_SYS_RAMBOOT		1
#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#else
#undef	CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN		0x00030000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE


#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#endif

#define CONFIG_SYS_FLASH_BASE		0xFFE00000
#define CONFIG_SYS_FLASH_SIZE		(2 * 1024 * 1024)	/* Unity has onboard 1MByte flash */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
#define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */

#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/

#define CONFIG_SYS_EUMB_ADDR		0xFC000000

#define CONFIG_SYS_ISA_MEM		0xFD000000
#define CONFIG_SYS_ISA_IO		0xFE000000

#define CONFIG_SYS_FLASH_RANGE_BASE	0xFFE00000	/* flash memory address range	*/
#define CONFIG_SYS_FLASH_RANGE_SIZE	0x00200000
#define FLASH_BASE0_PRELIM	0xFFE00000	/* processor board flash	*/

/*
 * select i2c support configuration
 *
 * Supported configurations are {none, software, hardware} drivers.
 * If the software driver is chosen, there are some additional
 * configuration items that the driver uses to drive the port pins.
 */
#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
#undef	CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F

#ifdef CONFIG_SYS_I2C_SOFT
#error "Soft I2C is not configured properly.  Please review!"
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
#define I2C_PORT		3		/* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
#define I2C_READ		((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
				else	iop->pdat &= ~0x00010000
#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
				else	iop->pdat &= ~0x00020000
#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
#endif /* CONFIG_SYS_I2C_SOFT */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1		/* Bytes of address		*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */

#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM }

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */


/* #define CONFIG_WINBOND_83C553	1	/ *has a winbond bridge			*/
#define CONFIG_SYS_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/

#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

/* TODO: Change this to VIA686A */

/*
 * NS87308 Configuration
 */
#define CONFIG_NS87308			/* Nat Semi super-io controller on ISA bus */

#define CONFIG_SYS_NS87308_BADDR_10	1

#define CONFIG_SYS_NS87308_DEVS	( CONFIG_SYS_NS87308_UART1   | \
				  CONFIG_SYS_NS87308_UART2   | \
				  CONFIG_SYS_NS87308_POWRMAN | \
				  CONFIG_SYS_NS87308_RTC_APC )

#undef	CONFIG_SYS_NS87308_PS2MOD

#define CONFIG_SYS_NS87308_CS0_BASE	0x0076
#define CONFIG_SYS_NS87308_CS0_CONF	0x30
#define CONFIG_SYS_NS87308_CS1_BASE	0x0075
#define CONFIG_SYS_NS87308_CS1_CONF	0x30
#define CONFIG_SYS_NS87308_CS2_BASE	0x0074
#define CONFIG_SYS_NS87308_CS2_CONF	0x30

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	1

#if (CONFIG_CONS_INDEX > 2)
#define CONFIG_SYS_NS16550_CLK		CONFIG_DRAM_SPEED*1000000
#else
#define CONFIG_SYS_NS16550_CLK		1843200
#endif

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_EUMB_ADDR + 0x4500)
#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_EUMB_ADDR + 0x4600)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */

#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
#define CONFIG_SYS_ROMFAL		11	/*rom/flash access time			*/

#define CONFIG_SYS_REFINT	430	/* no of clock cycles between CBR refresh cycles */

/* the following are for SDRAM only*/
#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
#if 0
#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
#endif

#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
#define CONFIG_SYS_EXTROM 1
#define CONFIG_SYS_REGDIMM 0


/* memory bank settings*/
/*
 * only bits 20-29 are actually used from these vales to set the
 * start/end address the upper two bits will be 0, and the lower 20
 * bits will be set to 0x00000 for a start address, or 0xfffff for an
 * end address
 */
#define CONFIG_SYS_BANK0_START		0x00000000
#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE	1
#define CONFIG_SYS_BANK1_START		0x3ff00000
#define CONFIG_SYS_BANK1_END		0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE	0
#define CONFIG_SYS_BANK2_START		0x3ff00000
#define CONFIG_SYS_BANK2_END		0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE	0
#define CONFIG_SYS_BANK3_START		0x3ff00000
#define CONFIG_SYS_BANK3_END		0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE	0
#define CONFIG_SYS_BANK4_START		0x00000000
#define CONFIG_SYS_BANK4_END		0x00000000
#define CONFIG_SYS_BANK4_ENABLE	0
#define CONFIG_SYS_BANK5_START		0x00000000
#define CONFIG_SYS_BANK5_END		0x00000000
#define CONFIG_SYS_BANK5_ENABLE	0
#define CONFIG_SYS_BANK6_START		0x00000000
#define CONFIG_SYS_BANK6_END		0x00000000
#define CONFIG_SYS_BANK6_ENABLE	0
#define CONFIG_SYS_BANK7_START		0x00000000
#define CONFIG_SYS_BANK7_END		0x00000000
#define CONFIG_SYS_BANK7_ENABLE	0
/*
 * Memory bank enable bitmask, specifying which of the banks defined above
 are actually present. MSB is for bank #7, LSB is for bank #0.
 */
#define CONFIG_SYS_BANK_ENABLE		0x01

#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
					/* see 8240 book for bit definitions	*/
#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

/* SDRAM 0 - 256MB */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in DCACHE @ 1GB (no backing mem) */
#if defined(USE_DINK32)
#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
#else
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#endif

/* PCI memory */
#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* Flash, config addrs, etc */
#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	36	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/* values according to the manual */
#define CONFIG_DRAM_50MHZ	1
#define CONFIG_SDRAM_50MHZ

#undef	NR_8259_INTS
#define NR_8259_INTS		1

#define CONFIG_DISK_SPINUP_TIME 1000000

#endif	/* __CONFIG_H */
Commit	Line	Data
756f586a WD	1	/*
	2	* (C) Copyright 2004
	3	* Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
	4	*
	5	* (C) Copyright 2001, 2002
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
756f586a WD	9	*/
	10
	11	/* ------------------------------------------------------------------------- */
	12
	13	/*
	14	* board/config.h - configuration options, board specific
	15	*/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
	20	/*
	21	* High Level Configuration Options
	22	* (easy to change)
	23	*/
	24
	25	#define CONFIG_MPC824X 1
	26	#define CONFIG_MPC8245 1
	27	#define CONFIG_HIDDEN_DRAGON 1
	28
2ae18241 WD	29	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
2ae18241 WD	30
756f586a WD	31	#if 0
	32	#define USE_DINK32 1
	33	#else
	34	#undef USE_DINK32
	35	#endif
	36
	37	#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
	38	#define CONFIG_BAUDRATE 9600
	39	#define CONFIG_DRAM_SPEED 100 /* MHz */
	40
756f586a	41
11799434 JL	42	/*
	43	* BOOTP options
	44	*/
	45	#define CONFIG_BOOTP_BOOTFILESIZE
	46	#define CONFIG_BOOTP_BOOTPATH
	47	#define CONFIG_BOOTP_GATEWAY
	48	#define CONFIG_BOOTP_HOSTNAME
	49
	50
6c4f4da9 JL	51	/*
	52	* Command line configuration.
	53	*/
	54	#include <config_cmd_default.h>
	55
	56	#define CONFIG_CMD_EEPROM
	57	#define CONFIG_CMD_ELF
	58	#define CONFIG_CMD_I2C
	59	#define CONFIG_CMD_NET
	60	#define CONFIG_CMD_PCI
	61	#define CONFIG_CMD_PING
756f586a WD	62
	63	/*
	64	* Miscellaneous configurable options
	65	*/
6d0f6bcf	66	#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
6d0f6bcf JCPV	67	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	68	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	69	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	70	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	71	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
756f586a WD	72
	73	/*-----------------------------------------------------------------------
	74	* PCI stuff
	75	*-----------------------------------------------------------------------
	76	*/
	77	#define CONFIG_PCI /* include pci support */
842033e6	78	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
756f586a WD	79	#undef CONFIG_PCI_PNP
756f586a WD	80
756f586a	81
6d0f6bcf	82	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
756f586a WD	83
	84	#define PCI_ENET0_IOADDR 0x80000000
	85	#define PCI_ENET0_MEMADDR 0x80000000
	86	#define PCI_ENET1_IOADDR 0x81000000
	87	#define PCI_ENET1_MEMADDR 0x81000000
	88
	89	#define CONFIG_RTL8139
890d242f	90
756f586a WD	91	/* Make sure the ethaddr can be overwritten
	92	TODO: Remove this on final product
	93	*/
	94	#define CONFIG_ENV_OVERWRITE
	95
	96	/*-----------------------------------------------------------------------
	97	* Start addresses for the final memory configuration
	98	* (Set up by the startup code)
6d0f6bcf	99	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
756f586a	100	*/
6d0f6bcf JCPV	101	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	102	#define CONFIG_SYS_MAX_RAM_SIZE 0x02000000
756f586a	103
6d0f6bcf	104	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
756f586a WD	105
756f586a WD	106	#if defined (USE_DINK32)
6d0f6bcf JCPV	107	#define CONFIG_SYS_MONITOR_LEN 0x00030000
	108	#define CONFIG_SYS_MONITOR_BASE 0x00090000
	109	#define CONFIG_SYS_RAMBOOT 1
	110	#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
553f0982	111	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
25ddd1fb	112	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	113	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
756f586a	114	#else
6d0f6bcf JCPV	115	#undef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	116	#define CONFIG_SYS_MONITOR_LEN 0x00030000
14d0a02a	117	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
756f586a	118
756f586a	119
6d0f6bcf	120	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982	121	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	122	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
756f586a WD	123
	124	#endif
	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_FLASH_BASE 0xFFE00000
6d0f6bcf JCPV	127	#define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */
5a1aceb0	128	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	129	#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
0e8d1586 JCPV	130	#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
756f586a	131
6d0f6bcf	132	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
756f586a	133
6d0f6bcf JCPV	134	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
6d0f6bcf JCPV	135	#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
756f586a	136
6d0f6bcf	137	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
756f586a	138
6d0f6bcf JCPV	139	#define CONFIG_SYS_ISA_MEM 0xFD000000
6d0f6bcf JCPV	140	#define CONFIG_SYS_ISA_IO 0xFE000000
756f586a	141
6d0f6bcf JCPV	142	#define CONFIG_SYS_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */
6d0f6bcf JCPV	143	#define CONFIG_SYS_FLASH_RANGE_SIZE 0x00200000
756f586a WD	144	#define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */
	145
	146	/*
	147	* select i2c support configuration
	148	*
	149	* Supported configurations are {none, software, hardware} drivers.
	150	* If the software driver is chosen, there are some additional
	151	* configuration items that the driver uses to drive the port pins.
	152	*/
	153	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
ea818dbb	154	#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
6d0f6bcf JCPV	155	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	156	#define CONFIG_SYS_I2C_SLAVE 0x7F
756f586a	157
ea818dbb	158	#ifdef CONFIG_SYS_I2C_SOFT
756f586a	159	#error "Soft I2C is not configured properly. Please review!"
ea818dbb HS	160	#define CONFIG_SYS_I2C
	161	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	162	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
756f586a WD	163	#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
	164	#define I2C_ACTIVE (iop->pdir \|= 0x00010000)
	165	#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
	166	#define I2C_READ ((iop->pdat & 0x00010000) != 0)
	167	#define I2C_SDA(bit) if(bit) iop->pdat \|= 0x00010000; \
	168	else iop->pdat &= ~0x00010000
	169	#define I2C_SCL(bit) if(bit) iop->pdat \|= 0x00020000; \
	170	else iop->pdat &= ~0x00020000
	171	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
ea818dbb	172	#endif /* CONFIG_SYS_I2C_SOFT */
756f586a	173
6d0f6bcf JCPV	174	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
	175	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	176	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	177	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
756f586a	178
6d0f6bcf	179	#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
756f586a WD	180
	181	/*-----------------------------------------------------------------------
	182	* Definitions for initial stack pointer and data area (in DPRAM)
	183	*/
	184
	185
57d6c589	186	/* #define CONFIG_WINBOND_83C553 1 / has a winbond bridge /
6d0f6bcf JCPV	187	#define CONFIG_SYS_USE_WINBOND_IDE 0 /use winbond 83c553 internal IDE ctrlr /
	188	#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /pci-isa bridge config addr /
	189	#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /ide config addr /
756f586a	190
6d0f6bcf JCPV	191	#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
6d0f6bcf JCPV	192	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS2) / max. 2 drives per IDE bus */
756f586a WD	193
	194	/* TODO: Change this to VIA686A */
	195
	196	/*
	197	* NS87308 Configuration
	198	*/
55d6d2d3	199	#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
756f586a	200
6d0f6bcf	201	#define CONFIG_SYS_NS87308_BADDR_10 1
756f586a	202
6d0f6bcf JCPV	203	#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 \| \
	204	CONFIG_SYS_NS87308_UART2 \| \
	205	CONFIG_SYS_NS87308_POWRMAN \| \
	206	CONFIG_SYS_NS87308_RTC_APC )
756f586a	207
6d0f6bcf	208	#undef CONFIG_SYS_NS87308_PS2MOD
756f586a	209
6d0f6bcf JCPV	210	#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
	211	#define CONFIG_SYS_NS87308_CS0_CONF 0x30
	212	#define CONFIG_SYS_NS87308_CS1_BASE 0x0075
	213	#define CONFIG_SYS_NS87308_CS1_CONF 0x30
	214	#define CONFIG_SYS_NS87308_CS2_BASE 0x0074
	215	#define CONFIG_SYS_NS87308_CS2_CONF 0x30
756f586a WD	216
	217	/*
	218	* NS16550 Configuration
	219	*/
6d0f6bcf JCPV	220	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	221	#define CONFIG_SYS_NS16550_SERIAL
756f586a	222
6d0f6bcf	223	#define CONFIG_SYS_NS16550_REG_SIZE 1
756f586a WD	224
756f586a WD	225	#if (CONFIG_CONS_INDEX > 2)
6d0f6bcf	226	#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000
756f586a	227	#else
6d0f6bcf	228	#define CONFIG_SYS_NS16550_CLK 1843200
756f586a WD	229	#endif
756f586a WD	230
6d0f6bcf JCPV	231	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
	232	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
	233	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
	234	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
756f586a WD	235
	236	/*
	237	* Low Level Configuration Settings
	238	* (address mappings, register initial values, etc.)
	239	* You should know what you are doing if you make changes here.
	240	*/
	241
	242	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	243
6d0f6bcf JCPV	244	#define CONFIG_SYS_ROMNAL 7 /rom/flash next access time /
6d0f6bcf JCPV	245	#define CONFIG_SYS_ROMFAL 11 /rom/flash access time /
756f586a	246
6d0f6bcf	247	#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
756f586a WD	248
756f586a WD	249	/* the following are for SDRAM only*/
6d0f6bcf JCPV	250	#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
	251	#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
	252	#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
	253	#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
	254	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
	255	#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
	256	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
	257	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
756f586a	258	#if 0
6d0f6bcf	259	#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
756f586a WD	260	#endif
756f586a WD	261
6d0f6bcf JCPV	262	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
	263	#define CONFIG_SYS_EXTROM 1
	264	#define CONFIG_SYS_REGDIMM 0
756f586a WD	265
	266
	267	/* memory bank settings*/
	268	/*
	269	* only bits 20-29 are actually used from these vales to set the
	270	* start/end address the upper two bits will be 0, and the lower 20
	271	* bits will be set to 0x00000 for a start address, or 0xfffff for an
	272	* end address
	273	*/
6d0f6bcf JCPV	274	#define CONFIG_SYS_BANK0_START 0x00000000
	275	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	276	#define CONFIG_SYS_BANK0_ENABLE 1
	277	#define CONFIG_SYS_BANK1_START 0x3ff00000
	278	#define CONFIG_SYS_BANK1_END 0x3fffffff
	279	#define CONFIG_SYS_BANK1_ENABLE 0
	280	#define CONFIG_SYS_BANK2_START 0x3ff00000
	281	#define CONFIG_SYS_BANK2_END 0x3fffffff
	282	#define CONFIG_SYS_BANK2_ENABLE 0
	283	#define CONFIG_SYS_BANK3_START 0x3ff00000
	284	#define CONFIG_SYS_BANK3_END 0x3fffffff
	285	#define CONFIG_SYS_BANK3_ENABLE 0
	286	#define CONFIG_SYS_BANK4_START 0x00000000
	287	#define CONFIG_SYS_BANK4_END 0x00000000
	288	#define CONFIG_SYS_BANK4_ENABLE 0
	289	#define CONFIG_SYS_BANK5_START 0x00000000
	290	#define CONFIG_SYS_BANK5_END 0x00000000
	291	#define CONFIG_SYS_BANK5_ENABLE 0
	292	#define CONFIG_SYS_BANK6_START 0x00000000
	293	#define CONFIG_SYS_BANK6_END 0x00000000
	294	#define CONFIG_SYS_BANK6_ENABLE 0
	295	#define CONFIG_SYS_BANK7_START 0x00000000
	296	#define CONFIG_SYS_BANK7_END 0x00000000
	297	#define CONFIG_SYS_BANK7_ENABLE 0
756f586a WD	298	/*
	299	* Memory bank enable bitmask, specifying which of the banks defined above
	300	are actually present. MSB is for bank #7, LSB is for bank #0.
	301	*/
6d0f6bcf	302	#define CONFIG_SYS_BANK_ENABLE 0x01
756f586a	303
6d0f6bcf	304	#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
756f586a	305	/* see 8240 book for bit definitions */
6d0f6bcf	306	#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
756f586a WD	307	/* currently accessed page in memory */
	308	/* see 8240 book for details */
	309
	310	/* SDRAM 0 - 256MB */
6d0f6bcf JCPV	311	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	312	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
756f586a WD	313
	314	/* stack in DCACHE @ 1GB (no backing mem) */
	315	#if defined(USE_DINK32)
6d0f6bcf JCPV	316	#define CONFIG_SYS_IBAT1L (0x40000000 \| BATL_PP_00 )
6d0f6bcf JCPV	317	#define CONFIG_SYS_IBAT1U (0x40000000 \| BATU_BL_128K )
756f586a	318	#else
6d0f6bcf JCPV	319	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	320	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
756f586a WD	321	#endif
	322
	323	/* PCI memory */
6d0f6bcf JCPV	324	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	325	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
756f586a WD	326
756f586a WD	327	/* Flash, config addrs, etc */
6d0f6bcf JCPV	328	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	329	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	330
	331	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	332	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	333	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	334	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	335	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	336	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	337	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	338	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
756f586a WD	339
	340	/*
	341	* For booting Linux, the board info and command line data
	342	* have to be in the first 8 MB of memory, since this is
	343	* the maximum mapped by the Linux kernel during initialization.
	344	*/
6d0f6bcf	345	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
756f586a WD	346	/*-----------------------------------------------------------------------
	347	* FLASH organization
	348	*/
6d0f6bcf JCPV	349	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	350	#define CONFIG_SYS_MAX_FLASH_SECT 36 /* max number of sectors on one chip */
756f586a	351
6d0f6bcf JCPV	352	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	353	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
756f586a WD	354
	355	/*-----------------------------------------------------------------------
	356	* Cache Configuration
	357	*/
6d0f6bcf	358	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
6c4f4da9	359	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	360	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
756f586a WD	361	#endif
756f586a WD	362
756f586a WD	363	/* values according to the manual */
	364	#define CONFIG_DRAM_50MHZ 1
	365	#define CONFIG_SDRAM_50MHZ
	366
	367	#undef NR_8259_INTS
	368	#define NR_8259_INTS 1
	369
	370	#define CONFIG_DISK_SPINUP_TIME 1000000
	371
	372	#endif /* __CONFIG_H */