[people/ms/u-boot.git] / include / configs / HMI10.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_HMI10
#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
#define CONFIG_TQM823L		1	/* ...on a TQM8xxL module	*/

#define CONFIG_LCD
#define CONFIG_NEC_NL6448BC33_54	/* NEC NL6448BC33_54 display	*/

#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
#define CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
#endif

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
#define CONFIG_PS2SERIAL	2	/* .. on COM3			*/
#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/

#define CONFIG_BOOTCOUNT_LIMIT

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_8xx\0"					\
	"bootfile=/tftpboot/HMI10/uImage\0"				\
	"kernel_addr=40040000\0"					\
	"ramdisk_addr=40100000\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define	CONFIG_BOARD_EARLY_INIT_R 1
#define CONFIG_MISC_INIT_R	  1

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

/* enable I2C and select the hardware/software driver */
#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/

#define CFG_I2C_SPEED		40000	/* 40 kHz is supposed to work	*/
#define CFG_I2C_SLAVE		0xFE

/* Software (bit-bang) I2C driver configuration */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#define CONFIG_CAN_DRIVER	1	/* CAN Driver support enabled	*/

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
#define CFG_I2C_RTC_ADDR 0x68		/* at address 0x68		*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP

#ifdef	CONFIG_SPLASH_SCREEN
    #define CONFIG_CMD_BMP
#endif


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/

#if 0
#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
#endif
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x40000000
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef CONFIG_CAN_DRIVER
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0100000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4100000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8100000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC100000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
#define PCMCIA_MEM_WIN_NO	5
#define NSCU_OE_INV		1		/* PCMCIA_GCRX_CXOE is inverted */

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
#ifndef CONFIG_STATUS_LED		/* Status and IDE LED's are mutually exclusive */
#define CONFIG_IDE_LED		1	/* LED   for ide supported	*/
#endif

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_3_CLK | OR_EHTR | OR_BI)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CFG_OR1_REMAP	CFG_OR0_REMAP
#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	0x00000A00

#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#ifndef CONFIG_CAN_DRIVER
#define CFG_OR3_PRELIM	CFG_OR2_PRELIM
#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
					BR_PS_8 | BR_MS_UPMB | BR_V )
#endif	/* CONFIG_CAN_DRIVER */

/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096	 Rows from SDRAM example configuration
 * 1000	 factor s -> ms
 *   32	 PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4	 Number of refresh cycles per period
 *   64	 Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */

#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
#define CFG_MAMR_PTA	98

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
a522fa0e	1	/*
414eec35	2	* (C) Copyright 2000-2005
a522fa0e WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
1c43771b	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
a522fa0e WD	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
c40b2956	36	#define CONFIG_HMI10
a522fa0e WD	37	#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
	38	#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
	39
	40	#define CONFIG_LCD
	41	#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */
	42
	43	#ifdef CONFIG_LCD /* with LCD controller ? */
1c43771b	44	#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
a522fa0e WD	45	#endif
a522fa0e WD	46
1c43771b	47	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
a522fa0e WD	48	#undef CONFIG_8xx_CONS_SMC2
	49	#undef CONFIG_8xx_CONS_NONE
	50	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	51
1c43771b	52	#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
c837dcb1	53	#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
1c43771b	54	#define CONFIG_PS2SERIAL 2 /* .. on COM3 */
c837dcb1	55	#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
1c43771b WD	56
1c43771b WD	57	#define CONFIG_BOOTCOUNT_LIMIT
a522fa0e WD	58
	59	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	60
	61	#define CONFIG_BOARD_TYPES 1 /* support board types */
	62
	63	#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
	64
	65	#undef CONFIG_BOOTARGS
	66
1c43771b	67	#define CONFIG_EXTRA_ENV_SETTINGS \
a522fa0e WD	68	"netdev=eth0\0" \
a522fa0e WD	69	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	70	"nfsroot=${serverip}:${rootpath}\0" \
a522fa0e	71	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	72	"addip=setenv bootargs ${bootargs} " \
	73	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	74	":${hostname}:${netdev}:off panic=1\0" \
a522fa0e	75	"flash_nfs=run nfsargs addip;" \
fe126d8b	76	"bootm ${kernel_addr}\0" \
a522fa0e	77	"flash_self=run ramargs addip;" \
fe126d8b WD	78	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	79	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
a522fa0e	80	"rootpath=/opt/eldk/ppc_8xx\0" \
c40b2956	81	"bootfile=/tftpboot/HMI10/uImage\0" \
a522fa0e WD	82	"kernel_addr=40040000\0" \
	83	"ramdisk_addr=40100000\0" \
	84	""
	85	#define CONFIG_BOOTCOMMAND "run flash_self"
	86
c837dcb1 WD	87	#define CONFIG_BOARD_EARLY_INIT_R 1
c837dcb1 WD	88	#define CONFIG_MISC_INIT_R 1
1c43771b	89
a522fa0e WD	90	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	91	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	92
	93	/* enable I2C and select the hardware/software driver */
	94	#undef CONFIG_HARD_I2C /* I2C with hardware support */
	95	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
	96
	97	#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */
	98	#define CFG_I2C_SLAVE 0xFE
	99
	100	/* Software (bit-bang) I2C driver configuration */
	101	#define PB_SCL 0x00000020 /* PB 26 */
	102	#define PB_SDA 0x00000010 /* PB 27 */
	103
	104	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	105	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	106	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	107	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	108	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
1c43771b	109	else immr->im_cpm.cp_pbdat &= ~PB_SDA
a522fa0e	110	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
1c43771b	111	else immr->im_cpm.cp_pbdat &= ~PB_SCL
a522fa0e WD	112	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	113
	114	#undef CONFIG_WATCHDOG /* watchdog disabled */
	115
	116	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	117
	118	#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
	119
	120	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE)
	121
	122	#define CONFIG_MAC_PARTITION
	123	#define CONFIG_DOS_PARTITION
	124
	125	#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
	126	#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
	127
6c4f4da9 JL	128
	129	/*
	130	* Command line configuration.
	131	*/
	132	#include <config_cmd_default.h>
	133
	134	#define CONFIG_CMD_ASKENV
	135	#define CONFIG_CMD_DATE
	136	#define CONFIG_CMD_DHCP
	137	#define CONFIG_CMD_FAT
	138	#define CONFIG_CMD_I2C
	139	#define CONFIG_CMD_IDE
	140	#define CONFIG_CMD_NFS
	141	#define CONFIG_CMD_SNTP
	142
a522fa0e	143	#ifdef CONFIG_SPLASH_SCREEN
6c4f4da9	144	#define CONFIG_CMD_BMP
a522fa0e WD	145	#endif
a522fa0e WD	146
a522fa0e WD	147
	148	/*
	149	* Miscellaneous configurable options
	150	*/
1c43771b WD	151	#define CFG_LONGHELP /* undef to save memory */
1c43771b WD	152	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
a522fa0e WD	153
a522fa0e WD	154	#if 0
1c43771b	155	#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
a522fa0e WD	156	#endif
a522fa0e WD	157	#ifdef CFG_HUSH_PARSER
1c43771b	158	#define CFG_PROMPT_HUSH_PS2 "> "
a522fa0e WD	159	#endif
a522fa0e WD	160
6c4f4da9	161	#if defined(CONFIG_CMD_KGDB)
1c43771b	162	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
a522fa0e	163	#else
1c43771b	164	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
a522fa0e	165	#endif
1c43771b WD	166	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
1c43771b WD	167	#define CFG_MAXARGS 16 /* max number of command args */
a522fa0e WD	168	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	169
	170	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	171	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	172
1c43771b	173	#define CFG_LOAD_ADDR 0x100000 /* default load address */
a522fa0e	174
1c43771b	175	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
a522fa0e WD	176
	177	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	178
	179	/*
	180	* Low Level Configuration Settings
	181	* (address mappings, register initial values, etc.)
	182	* You should know what you are doing if you make changes here.
	183	*/
	184	/*-----------------------------------------------------------------------
	185	* Internal Memory Mapped Register
	186	*/
	187	#define CFG_IMMR 0xFFF00000
	188
	189	/*-----------------------------------------------------------------------
	190	* Definitions for initial stack pointer and data area (in DPRAM)
	191	*/
	192	#define CFG_INIT_RAM_ADDR CFG_IMMR
1c43771b WD	193	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
1c43771b WD	194	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
a522fa0e	195	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
1c43771b	196	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
a522fa0e WD	197
	198	/*-----------------------------------------------------------------------
	199	* Start addresses for the final memory configuration
	200	* (Set up by the startup code)
	201	* Please note that CFG_SDRAM_BASE _must_ start at 0
	202	*/
1c43771b	203	#define CFG_SDRAM_BASE 0x00000000
a522fa0e	204	#define CFG_FLASH_BASE 0x40000000
1c43771b	205	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
a522fa0e	206	#define CFG_MONITOR_BASE CFG_FLASH_BASE
1c43771b	207	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
a522fa0e WD	208
	209	/*
	210	* For booting Linux, the board info and command line data
	211	* have to be in the first 8 MB of memory, since this is
	212	* the maximum mapped by the Linux kernel during initialization.
	213	*/
1c43771b	214	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
a522fa0e WD	215
	216	/*-----------------------------------------------------------------------
	217	* FLASH organization
	218	*/
	219	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	220	#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
	221
	222	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	223	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	224
1c43771b WD	225	#define CFG_ENV_IS_IN_FLASH 1
	226	#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
	227	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
a522fa0e WD	228
	229	/* Address and size of Redundant Environment Sector */
	230	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
	231	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	232
	233	/*-----------------------------------------------------------------------
	234	* Hardware Information Block
	235	*/
	236	#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
1c43771b	237	#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
a522fa0e WD	238	#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
	239
	240	/*-----------------------------------------------------------------------
	241	* Cache Configuration
	242	*/
	243	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
6c4f4da9	244	#if defined(CONFIG_CMD_KGDB)
a522fa0e WD	245	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	246	#endif
	247
	248	/*-----------------------------------------------------------------------
	249	* SYPCR - System Protection Control 11-9
	250	* SYPCR can only be written once after reset!
	251	*-----------------------------------------------------------------------
	252	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	253	*/
	254	#if defined(CONFIG_WATCHDOG)
	255	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	256	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	257	#else
	258	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	259	#endif
	260
	261	/*-----------------------------------------------------------------------
	262	* SIUMCR - SIU Module Configuration 11-6
	263	*-----------------------------------------------------------------------
	264	* PCMCIA config., multi-function pin tri-state
	265	*/
1c43771b	266	#ifndef CONFIG_CAN_DRIVER
a522fa0e WD	267	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	268	#else /* we must activate GPL5 in the SIUMCR for CAN */
	269	#define CFG_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	270	#endif /* CONFIG_CAN_DRIVER */
	271
	272	/*-----------------------------------------------------------------------
	273	* TBSCR - Time Base Status and Control 11-26
	274	*-----------------------------------------------------------------------
	275	* Clear Reference Interrupt Status, Timebase freezing enabled
	276	*/
	277	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	278
	279	/*-----------------------------------------------------------------------
	280	* RTCSC - Real-Time Clock Status and Control Register 11-27
	281	*-----------------------------------------------------------------------
	282	*/
	283	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
	284
	285	/*-----------------------------------------------------------------------
	286	* PISCR - Periodic Interrupt Status and Control 11-31
	287	*-----------------------------------------------------------------------
	288	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	289	*/
	290	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	291
	292	/*-----------------------------------------------------------------------
	293	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	294	*-----------------------------------------------------------------------
	295	* Reset PLL lock status sticky bit, timer expired status bit and timer
	296	* interrupt status bit
	297	*
	298	* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
	299	*/
a522fa0e	300	#define CFG_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
a522fa0e WD	301
	302	/*-----------------------------------------------------------------------
	303	* SCCR - System Clock and reset Control Register 15-27
	304	*-----------------------------------------------------------------------
	305	* Set clock output, timebase and RTC source and divider,
	306	* power management and some other internal clocks
	307	*/
	308	#define SCCR_MASK SCCR_EBDF11
c3f4d17e	309	#define CFG_SCCR (SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
a522fa0e WD	310	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
a522fa0e WD	311	SCCR_DFALCD00)
a522fa0e WD	312
	313	/*-----------------------------------------------------------------------
	314	* PCMCIA stuff
	315	*-----------------------------------------------------------------------
	316	*
	317	*/
a522fa0e WD	318	#define CFG_PCMCIA_MEM_ADDR (0xE0100000)
	319	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
	320	#define CFG_PCMCIA_DMA_ADDR (0xE4100000)
	321	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
	322	#define CFG_PCMCIA_ATTRB_ADDR (0xE8100000)
	323	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	324	#define CFG_PCMCIA_IO_ADDR (0xEC100000)
	325	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
68766094	326	#define PCMCIA_MEM_WIN_NO 5
1c43771b	327	#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */
a522fa0e WD	328
	329	/*-----------------------------------------------------------------------
	330	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	331	*-----------------------------------------------------------------------
	332	*/
	333
1c43771b	334	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
a522fa0e	335
1c43771b	336	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
a522fa0e	337	#undef CONFIG_IDE_RESET /* reset for ide not supported */
1c43771b WD	338	#ifndef CONFIG_STATUS_LED /* Status and IDE LED's are mutually exclusive */
	339	#define CONFIG_IDE_LED 1 /* LED for ide supported */
	340	#endif
a522fa0e WD	341
	342	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	343	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	344
	345	#define CFG_ATA_IDE0_OFFSET 0x0000
	346
	347	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
	348
	349	/* Offset for data I/O */
	350	#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
	351
	352	/* Offset for normal register accesses */
	353	#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
	354
	355	/* Offset for alternate registers */
	356	#define CFG_ATA_ALT_OFFSET 0x0100
	357
	358	/*-----------------------------------------------------------------------
	359	*
	360	*-----------------------------------------------------------------------
	361	*
	362	*/
1c43771b	363	#define CFG_DER 0
a522fa0e WD	364
	365	/*
	366	* Init Memory Controller:
	367	*
	368	* BR0/1 and OR0/1 (FLASH)
	369	*/
	370
	371	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	372	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	373
	374	/* used to re-map FLASH both when starting from SRAM or FLASH:
	375	* restrict access enough to keep SRAM working (if any)
	376	* but not too much to meddle with FLASH accesses
	377	*/
	378	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
	379	#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
	380
	381	/*
	382	* FLASH timing:
	383	*/
a522fa0e WD	384	#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
a522fa0e WD	385	OR_SCY_3_CLK \| OR_EHTR \| OR_BI)
a522fa0e WD	386
	387	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
	388	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
	389	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
	390
	391	#define CFG_OR1_REMAP CFG_OR0_REMAP
	392	#define CFG_OR1_PRELIM CFG_OR0_PRELIM
	393	#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V )
	394
	395	/*
	396	* BR2/3 and OR2/3 (SDRAM)
	397	*
	398	*/
	399	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	400	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
1c43771b	401	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
a522fa0e WD	402
	403	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
	404	#define CFG_OR_TIMING_SDRAM 0x00000A00
	405
	406	#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_SDRAM )
	407	#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
	408
1c43771b WD	409	#ifndef CONFIG_CAN_DRIVER
1c43771b WD	410	#define CFG_OR3_PRELIM CFG_OR2_PRELIM
a522fa0e WD	411	#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
a522fa0e WD	412	#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
1c43771b	413	#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
a522fa0e WD	414	#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	415	#define CFG_OR3_CAN (CFG_CAN_OR_AM \| OR_G5LA \| OR_BI)
	416	#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) \| \
	417	BR_PS_8 \| BR_MS_UPMB \| BR_V )
	418	#endif /* CONFIG_CAN_DRIVER */
	419
	420	/*
	421	* Memory Periodic Timer Prescaler
	422	*
	423	* The Divider for PTA (refresh timer) configuration is based on an
	424	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	425	* the number of chip selects (NCS) and the actually needed refresh
	426	* rate is done by setting MPTPR.
	427	*
	428	* PTA is calculated from
	429	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	430	*
	431	* gclk CPU clock (not bus clock!)
	432	* Trefresh Refresh cycle * 4 (four word bursts used)
	433	*
1c43771b WD	434	* 4096 Rows from SDRAM example configuration
	435	* 1000 factor s -> ms
	436	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	437	* 4 Number of refresh cycles per period
	438	* 64 Refresh cycle in ms per number of rows
a522fa0e WD	439	* --------------------------------------------
	440	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	441	*
	442	* 50 MHz => 50.000.000 / Divider = 98
	443	* 66 Mhz => 66.000.000 / Divider = 129
	444	* 80 Mhz => 80.000.000 / Divider = 156
	445	*/
c3f4d17e WD	446
	447	#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
	448	#define CFG_MAMR_PTA 98
a522fa0e WD	449
	450	/*
	451	* For 16 MBit, refresh rates could be 31.3 us
	452	* (= 64 ms / 2K = 125 / quad bursts).
	453	* For a simpler initialization, 15.6 us is used instead.
	454	*
	455	* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
	456	* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
	457	*/
	458	#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
	459	#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
	460
	461	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
	462	#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
	463	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
	464
	465	/*
	466	* MAMR settings for SDRAM
	467	*/
	468
	469	/* 8 column SDRAM */
	470	#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	471	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	472	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	473	/* 9 column SDRAM */
	474	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	475	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	476	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	477
	478
	479	/*
	480	* Internal Definitions
	481	*
	482	* Boot Flags
	483	*/
1c43771b	484	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
a522fa0e WD	485	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	486
	487	#endif /* __CONFIG_H */