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9dd41a7b WD |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Heiko Schocher, DENX Software Engineering, <hs@denx.de> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ | |
37 | #define CONFIG_MPC8272_FAMILY 1 | |
38 | #define CONFIG_IDS8247 1 | |
39 | #define CPU_ID_STR "MPC8247" | |
9c4c5ae3 | 40 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
9dd41a7b | 41 | |
2ae18241 WD |
42 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
43 | ||
9dd41a7b WD |
44 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
45 | ||
46 | #define CONFIG_BOOTCOUNT_LIMIT | |
47 | ||
32bf3d14 | 48 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
9dd41a7b WD |
49 | |
50 | #undef CONFIG_BOOTARGS | |
51 | ||
52 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
53 | "netdev=eth0\0" \ | |
54 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 55 | "nfsroot=${serverip}:${rootpath}\0" \ |
9dd41a7b WD |
56 | "ramargs=setenv bootargs root=/dev/ram rw " \ |
57 | "console=ttyS0,115200\0" \ | |
fe126d8b WD |
58 | "addip=setenv bootargs ${bootargs} " \ |
59 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
60 | ":${hostname}:${netdev}:off panic=1\0" \ | |
9dd41a7b | 61 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 62 | "bootm ${kernel_addr}\0" \ |
9dd41a7b | 63 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
64 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
65 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
9dd41a7b WD |
66 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
67 | "bootfile=/tftpboot/IDS8247/uImage\0" \ | |
68 | "kernel_addr=ff800000\0" \ | |
69 | "ramdisk_addr=ffa00000\0" \ | |
70 | "" | |
71 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
72 | ||
73 | #define CONFIG_MISC_INIT_R 1 | |
74 | ||
75 | /* enable I2C and select the hardware/software driver */ | |
76 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
77 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
6d0f6bcf JCPV |
78 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
79 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
9dd41a7b WD |
80 | |
81 | /* | |
82 | * Software (bit-bang) I2C driver configuration | |
83 | */ | |
84 | ||
85 | #define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */ | |
86 | #define I2C_ACTIVE (iop->pdir |= 0x00000080) | |
87 | #define I2C_TRISTATE (iop->pdir &= ~0x00000080) | |
88 | #define I2C_READ ((iop->pdat & 0x00000080) != 0) | |
89 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \ | |
90 | else iop->pdat &= ~0x00000080 | |
91 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \ | |
92 | else iop->pdat &= ~0x00000100 | |
93 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
94 | ||
95 | #if 0 | |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
97 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
98 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
99 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
9dd41a7b WD |
100 | |
101 | #define CONFIG_I2C_X | |
102 | #endif | |
103 | ||
104 | /* | |
105 | * select serial console configuration | |
106 | * use the extern UART for the console | |
107 | */ | |
108 | #define CONFIG_CONS_INDEX 1 | |
109 | #define CONFIG_BAUDRATE 115200 | |
110 | /* | |
111 | * NS16550 Configuration | |
112 | */ | |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_NS16550 |
114 | #define CONFIG_SYS_NS16550_SERIAL | |
9dd41a7b | 115 | |
6d0f6bcf | 116 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
9dd41a7b | 117 | |
6d0f6bcf | 118 | #define CONFIG_SYS_NS16550_CLK 14745600 |
9dd41a7b | 119 | |
6d0f6bcf JCPV |
120 | #define CONFIG_SYS_UART_BASE 0xE0000000 |
121 | #define CONFIG_SYS_UART_SIZE 0x10000 | |
9dd41a7b | 122 | |
6d0f6bcf | 123 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000) |
9dd41a7b | 124 | |
6abd82e1 SS |
125 | |
126 | /* pass open firmware flat tree */ | |
127 | #define CONFIG_OF_LIBFDT 1 | |
128 | #define CONFIG_OF_BOARD_SETUP 1 | |
129 | ||
6abd82e1 SS |
130 | #define OF_TBCLK (bd->bi_busfreq / 4) |
131 | #define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" | |
132 | ||
133 | ||
9dd41a7b WD |
134 | /* |
135 | * select ethernet configuration | |
136 | * | |
137 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
138 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
139 | * for FCC) | |
140 | * | |
141 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 142 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
9dd41a7b WD |
143 | */ |
144 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
145 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
146 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
6abd82e1 SS |
147 | #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ |
148 | #define CONFIG_ETHER_ON_FCC1 | |
149 | #define FCC_ENET | |
9dd41a7b WD |
150 | |
151 | /* | |
6abd82e1 SS |
152 | * - Rx-CLK is CLK10 |
153 | * - Tx-CLK is CLK9 | |
9dd41a7b WD |
154 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
155 | * - Enable Full Duplex in FSMR | |
156 | */ | |
6d0f6bcf JCPV |
157 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) |
158 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9) | |
159 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
160 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
9dd41a7b WD |
161 | |
162 | ||
163 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
164 | #define CONFIG_8260_CLKIN 66666666 /* in Hz */ | |
165 | ||
166 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 167 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
9dd41a7b WD |
168 | |
169 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
170 | ||
171 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
172 | ||
7be044e4 JL |
173 | /* |
174 | * BOOTP options | |
175 | */ | |
176 | #define CONFIG_BOOTP_SUBNETMASK | |
177 | #define CONFIG_BOOTP_GATEWAY | |
178 | #define CONFIG_BOOTP_HOSTNAME | |
179 | #define CONFIG_BOOTP_BOOTPATH | |
180 | #define CONFIG_BOOTP_BOOTFILESIZE | |
9dd41a7b | 181 | |
6abd82e1 | 182 | #define CONFIG_RTC_PCF8563 |
6d0f6bcf | 183 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
9dd41a7b | 184 | |
348f258f JL |
185 | /* |
186 | * Command line configuration. | |
187 | */ | |
188 | #include <config_cmd_default.h> | |
189 | ||
190 | #define CONFIG_CMD_DHCP | |
191 | #define CONFIG_CMD_NFS | |
192 | #define CONFIG_CMD_NAND | |
193 | #define CONFIG_CMD_I2C | |
194 | #define CONFIG_CMD_SNTP | |
195 | ||
9dd41a7b WD |
196 | |
197 | /* | |
198 | * Miscellaneous configurable options | |
199 | */ | |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
201 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
348f258f | 202 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 203 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
9dd41a7b | 204 | #else |
6d0f6bcf | 205 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
9dd41a7b | 206 | #endif |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
208 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
209 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
9dd41a7b | 210 | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
212 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
9dd41a7b | 213 | |
6d0f6bcf | 214 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
9dd41a7b | 215 | |
6d0f6bcf | 216 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
9dd41a7b | 217 | |
6d0f6bcf | 218 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
9dd41a7b | 219 | |
6d0f6bcf | 220 | #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ |
9dd41a7b WD |
221 | |
222 | /* | |
223 | * For booting Linux, the board info and command line data | |
224 | * have to be in the first 8 MB of memory, since this is | |
225 | * the maximum mapped by the Linux kernel during initialization. | |
226 | */ | |
6d0f6bcf | 227 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
9dd41a7b | 228 | |
6d0f6bcf | 229 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 230 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
6d0f6bcf | 231 | #define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 } |
ca5def3f | 232 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
9dd41a7b | 233 | /* What should the base address of the main FLASH be and how big is |
14d0a02a | 234 | * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk |
9dd41a7b WD |
235 | * The main FLASH is whichever is connected to *CS0. |
236 | */ | |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_FLASH0_BASE 0xFFF00000 |
238 | #define CONFIG_SYS_FLASH0_SIZE 8 | |
9dd41a7b WD |
239 | |
240 | /* Flash bank size (for preliminary settings) | |
241 | */ | |
6d0f6bcf | 242 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE |
9dd41a7b WD |
243 | |
244 | /*----------------------------------------------------------------------- | |
245 | * FLASH organization | |
246 | */ | |
6d0f6bcf | 247 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
9dd41a7b | 248 | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
250 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
9dd41a7b WD |
251 | |
252 | /* Environment in flash */ | |
5a1aceb0 | 253 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 254 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000) |
0e8d1586 JCPV |
255 | #define CONFIG_ENV_SIZE 0x20000 |
256 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
9dd41a7b WD |
257 | |
258 | /*----------------------------------------------------------------------- | |
259 | * NAND-FLASH stuff | |
260 | *----------------------------------------------------------------------- | |
261 | */ | |
348f258f | 262 | #if defined(CONFIG_CMD_NAND) |
9dd41a7b | 263 | |
6d0f6bcf | 264 | #define CONFIG_SYS_NAND0_BASE 0xE1000000 |
6d0f6bcf | 265 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
9dd41a7b | 266 | |
11799434 | 267 | #endif /* CONFIG_CMD_NAND */ |
9dd41a7b WD |
268 | |
269 | /*----------------------------------------------------------------------- | |
270 | * Hard Reset Configuration Words | |
271 | * | |
6d0f6bcf | 272 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
9dd41a7b | 273 | * defines for the various registers affected by the HRCW e.g. changing |
6d0f6bcf | 274 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
9dd41a7b | 275 | */ |
6d0f6bcf | 276 | #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000) |
9dd41a7b WD |
277 | |
278 | /* no slaves so just fill with zeros */ | |
6d0f6bcf JCPV |
279 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
280 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
281 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
282 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
283 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
284 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
285 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
9dd41a7b WD |
286 | |
287 | /*----------------------------------------------------------------------- | |
288 | * Internal Memory Mapped Register | |
289 | */ | |
6d0f6bcf | 290 | #define CONFIG_SYS_IMMR 0xF0000000 |
9dd41a7b WD |
291 | |
292 | /*----------------------------------------------------------------------- | |
293 | * Definitions for initial stack pointer and data area (in DPRAM) | |
294 | */ | |
6d0f6bcf | 295 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 296 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ |
25ddd1fb | 297 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 298 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
9dd41a7b WD |
299 | |
300 | /*----------------------------------------------------------------------- | |
301 | * Start addresses for the final memory configuration | |
302 | * (Set up by the startup code) | |
6d0f6bcf | 303 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
9dd41a7b | 304 | * |
6d0f6bcf | 305 | * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE |
9dd41a7b | 306 | */ |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
308 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE | |
14d0a02a | 309 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
311 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
9dd41a7b | 312 | |
9dd41a7b WD |
313 | /*----------------------------------------------------------------------- |
314 | * Cache Configuration | |
315 | */ | |
6d0f6bcf | 316 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
348f258f | 317 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 318 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
9dd41a7b WD |
319 | #endif |
320 | ||
321 | /*----------------------------------------------------------------------- | |
322 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
323 | *----------------------------------------------------------------------- | |
324 | * HID0 also contains cache control - initially enable both caches and | |
325 | * invalidate contents, then the final state leaves only the instruction | |
326 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
327 | * but Soft reset does not. | |
328 | * | |
329 | * HID1 has only read-only information - nothing to set. | |
330 | */ | |
331 | ||
6d0f6bcf JCPV |
332 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) |
333 | #define CONFIG_SYS_HID0_FINAL 0 | |
334 | #define CONFIG_SYS_HID2 0 | |
9dd41a7b WD |
335 | |
336 | /*----------------------------------------------------------------------- | |
337 | * RMR - Reset Mode Register 5-5 | |
338 | *----------------------------------------------------------------------- | |
339 | * turn on Checkstop Reset Enable | |
340 | */ | |
6d0f6bcf | 341 | #define CONFIG_SYS_RMR 0 |
9dd41a7b WD |
342 | |
343 | /*----------------------------------------------------------------------- | |
344 | * BCR - Bus Configuration 4-25 | |
345 | *----------------------------------------------------------------------- | |
346 | */ | |
6d0f6bcf | 347 | #define CONFIG_SYS_BCR 0 |
9dd41a7b WD |
348 | |
349 | /*----------------------------------------------------------------------- | |
350 | * SIUMCR - SIU Module Configuration 4-31 | |
351 | *----------------------------------------------------------------------- | |
352 | */ | |
6d0f6bcf | 353 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01) |
9dd41a7b WD |
354 | |
355 | /*----------------------------------------------------------------------- | |
356 | * SYPCR - System Protection Control 4-35 | |
357 | * SYPCR can only be written once after reset! | |
358 | *----------------------------------------------------------------------- | |
359 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
360 | */ | |
361 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 362 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
9dd41a7b WD |
363 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
364 | #else | |
6d0f6bcf | 365 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
9dd41a7b WD |
366 | SYPCR_SWRI|SYPCR_SWP) |
367 | #endif /* CONFIG_WATCHDOG */ | |
368 | ||
369 | /*----------------------------------------------------------------------- | |
370 | * TMCNTSC - Time Counter Status and Control 4-40 | |
371 | *----------------------------------------------------------------------- | |
372 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
373 | * and enable Time Counter | |
374 | */ | |
6d0f6bcf | 375 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
9dd41a7b WD |
376 | |
377 | /*----------------------------------------------------------------------- | |
378 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
379 | *----------------------------------------------------------------------- | |
380 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
381 | * Periodic timer | |
382 | */ | |
6d0f6bcf | 383 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
9dd41a7b WD |
384 | |
385 | /*----------------------------------------------------------------------- | |
386 | * SCCR - System Clock Control 9-8 | |
387 | *----------------------------------------------------------------------- | |
388 | * Ensure DFBRG is Divide by 16 | |
389 | */ | |
6d0f6bcf | 390 | #define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01) |
9dd41a7b WD |
391 | |
392 | /*----------------------------------------------------------------------- | |
393 | * RCCR - RISC Controller Configuration 13-7 | |
394 | *----------------------------------------------------------------------- | |
395 | */ | |
6d0f6bcf | 396 | #define CONFIG_SYS_RCCR 0 |
9dd41a7b WD |
397 | |
398 | /* | |
399 | * Init Memory Controller: | |
400 | * | |
401 | * Bank Bus Machine PortSz Device | |
402 | * ---- --- ------- ------ ------ | |
403 | * 0 60x GPCM 16 bit FLASH | |
404 | * 1 60x GPCM 8 bit NAND | |
405 | * 2 60x SDRAM 32 bit SDRAM | |
406 | * 3 60x GPCM 8 bit UART | |
407 | * | |
408 | */ | |
409 | ||
410 | #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
411 | ||
412 | /* Minimum mask to separate preliminary | |
413 | * address ranges for CS[0:2] | |
414 | */ | |
6d0f6bcf | 415 | #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */ |
9dd41a7b | 416 | |
6d0f6bcf | 417 | #define CONFIG_SYS_MPTPR 0x6600 |
9dd41a7b WD |
418 | |
419 | /*----------------------------------------------------------------------------- | |
420 | * Address for Mode Register Set (MRS) command | |
421 | *----------------------------------------------------------------------------- | |
422 | */ | |
6d0f6bcf | 423 | #define CONFIG_SYS_MRS_OFFS 0x00000110 |
9dd41a7b WD |
424 | |
425 | ||
426 | /* Bank 0 - FLASH | |
427 | */ | |
6d0f6bcf | 428 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
9dd41a7b WD |
429 | BRx_PS_8 |\ |
430 | BRx_MS_GPCM_P |\ | |
431 | BRx_V) | |
432 | ||
6d0f6bcf | 433 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
9dd41a7b WD |
434 | ORxG_SCY_6_CLK ) |
435 | ||
348f258f | 436 | #if defined(CONFIG_CMD_NAND) |
9dd41a7b WD |
437 | /* Bank 1 - NAND Flash |
438 | */ | |
6d0f6bcf JCPV |
439 | #define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE |
440 | #define CONFIG_SYS_NAND_SIZE 0x8000 | |
9dd41a7b | 441 | |
6d0f6bcf | 442 | #define CONFIG_SYS_OR_TIMING_NAND 0x000036 |
9dd41a7b | 443 | |
6d0f6bcf JCPV |
444 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) |
445 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND ) | |
9dd41a7b WD |
446 | #endif |
447 | ||
448 | /* Bank 2 - 60x bus SDRAM | |
449 | */ | |
6d0f6bcf JCPV |
450 | #define CONFIG_SYS_PSRT 0x20 |
451 | #define CONFIG_SYS_LSRT 0x20 | |
9dd41a7b | 452 | |
6d0f6bcf | 453 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ |
9dd41a7b WD |
454 | BRx_PS_32 |\ |
455 | BRx_MS_SDRAM_P |\ | |
456 | BRx_V) | |
457 | ||
6d0f6bcf | 458 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2 |
9dd41a7b WD |
459 | |
460 | ||
461 | /* SDRAM initialization values | |
462 | */ | |
6d0f6bcf | 463 | #define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
9dd41a7b | 464 | ORxS_BPD_4 |\ |
6abd82e1 | 465 | ORxS_ROWST_PBI0_A9 |\ |
9dd41a7b WD |
466 | ORxS_NUMR_12) |
467 | ||
6d0f6bcf | 468 | #define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ |
9dd41a7b | 469 | PSDMR_BSMA_A15_A17 |\ |
6abd82e1 | 470 | PSDMR_SDA10_PBI0_A10 |\ |
9dd41a7b WD |
471 | PSDMR_RFRC_5_CLK |\ |
472 | PSDMR_PRETOACT_2W |\ | |
473 | PSDMR_ACTTORW_2W |\ | |
474 | PSDMR_BL |\ | |
475 | PSDMR_LDOTOPRE_2C |\ | |
476 | PSDMR_WRC_3C |\ | |
477 | PSDMR_CL_3) | |
478 | ||
479 | /* Bank 3 - UART | |
480 | */ | |
481 | ||
6d0f6bcf JCPV |
482 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) |
483 | #define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX ) | |
9dd41a7b WD |
484 | |
485 | #endif /* __CONFIG_H */ |