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9dd41a7b WD |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Heiko Schocher, DENX Software Engineering, <hs@denx.de> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ | |
37 | #define CONFIG_MPC8272_FAMILY 1 | |
38 | #define CONFIG_IDS8247 1 | |
39 | #define CPU_ID_STR "MPC8247" | |
9c4c5ae3 | 40 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
9dd41a7b WD |
41 | |
42 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
43 | ||
44 | #define CONFIG_BOOTCOUNT_LIMIT | |
45 | ||
32bf3d14 | 46 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
9dd41a7b WD |
47 | |
48 | #undef CONFIG_BOOTARGS | |
49 | ||
50 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
51 | "netdev=eth0\0" \ | |
52 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 53 | "nfsroot=${serverip}:${rootpath}\0" \ |
9dd41a7b WD |
54 | "ramargs=setenv bootargs root=/dev/ram rw " \ |
55 | "console=ttyS0,115200\0" \ | |
fe126d8b WD |
56 | "addip=setenv bootargs ${bootargs} " \ |
57 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
58 | ":${hostname}:${netdev}:off panic=1\0" \ | |
9dd41a7b | 59 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 60 | "bootm ${kernel_addr}\0" \ |
9dd41a7b | 61 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
62 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
63 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
9dd41a7b WD |
64 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
65 | "bootfile=/tftpboot/IDS8247/uImage\0" \ | |
66 | "kernel_addr=ff800000\0" \ | |
67 | "ramdisk_addr=ffa00000\0" \ | |
68 | "" | |
69 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
70 | ||
71 | #define CONFIG_MISC_INIT_R 1 | |
72 | ||
73 | /* enable I2C and select the hardware/software driver */ | |
74 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
75 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
6d0f6bcf JCPV |
76 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
77 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
9dd41a7b WD |
78 | |
79 | /* | |
80 | * Software (bit-bang) I2C driver configuration | |
81 | */ | |
82 | ||
83 | #define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */ | |
84 | #define I2C_ACTIVE (iop->pdir |= 0x00000080) | |
85 | #define I2C_TRISTATE (iop->pdir &= ~0x00000080) | |
86 | #define I2C_READ ((iop->pdat & 0x00000080) != 0) | |
87 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \ | |
88 | else iop->pdat &= ~0x00000080 | |
89 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \ | |
90 | else iop->pdat &= ~0x00000100 | |
91 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
92 | ||
93 | #if 0 | |
6d0f6bcf JCPV |
94 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
95 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
96 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
97 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
9dd41a7b WD |
98 | |
99 | #define CONFIG_I2C_X | |
100 | #endif | |
101 | ||
102 | /* | |
103 | * select serial console configuration | |
104 | * use the extern UART for the console | |
105 | */ | |
106 | #define CONFIG_CONS_INDEX 1 | |
107 | #define CONFIG_BAUDRATE 115200 | |
108 | /* | |
109 | * NS16550 Configuration | |
110 | */ | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_NS16550 |
112 | #define CONFIG_SYS_NS16550_SERIAL | |
9dd41a7b | 113 | |
6d0f6bcf | 114 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
9dd41a7b | 115 | |
6d0f6bcf | 116 | #define CONFIG_SYS_NS16550_CLK 14745600 |
9dd41a7b | 117 | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_UART_BASE 0xE0000000 |
119 | #define CONFIG_SYS_UART_SIZE 0x10000 | |
9dd41a7b | 120 | |
6d0f6bcf | 121 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000) |
9dd41a7b | 122 | |
6abd82e1 SS |
123 | |
124 | /* pass open firmware flat tree */ | |
125 | #define CONFIG_OF_LIBFDT 1 | |
126 | #define CONFIG_OF_BOARD_SETUP 1 | |
127 | ||
6abd82e1 SS |
128 | #define OF_TBCLK (bd->bi_busfreq / 4) |
129 | #define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" | |
130 | ||
131 | ||
9dd41a7b WD |
132 | /* |
133 | * select ethernet configuration | |
134 | * | |
135 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
136 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
137 | * for FCC) | |
138 | * | |
139 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 140 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
9dd41a7b WD |
141 | */ |
142 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
143 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
144 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
6abd82e1 SS |
145 | #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ |
146 | #define CONFIG_ETHER_ON_FCC1 | |
147 | #define FCC_ENET | |
9dd41a7b WD |
148 | |
149 | /* | |
6abd82e1 SS |
150 | * - Rx-CLK is CLK10 |
151 | * - Tx-CLK is CLK9 | |
9dd41a7b WD |
152 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
153 | * - Enable Full Duplex in FSMR | |
154 | */ | |
6d0f6bcf JCPV |
155 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) |
156 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9) | |
157 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
158 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
9dd41a7b WD |
159 | |
160 | ||
161 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
162 | #define CONFIG_8260_CLKIN 66666666 /* in Hz */ | |
163 | ||
164 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 165 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
9dd41a7b WD |
166 | |
167 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
168 | ||
169 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
170 | ||
7be044e4 JL |
171 | /* |
172 | * BOOTP options | |
173 | */ | |
174 | #define CONFIG_BOOTP_SUBNETMASK | |
175 | #define CONFIG_BOOTP_GATEWAY | |
176 | #define CONFIG_BOOTP_HOSTNAME | |
177 | #define CONFIG_BOOTP_BOOTPATH | |
178 | #define CONFIG_BOOTP_BOOTFILESIZE | |
9dd41a7b | 179 | |
6abd82e1 | 180 | #define CONFIG_RTC_PCF8563 |
6d0f6bcf | 181 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
9dd41a7b | 182 | |
348f258f JL |
183 | /* |
184 | * Command line configuration. | |
185 | */ | |
186 | #include <config_cmd_default.h> | |
187 | ||
188 | #define CONFIG_CMD_DHCP | |
189 | #define CONFIG_CMD_NFS | |
190 | #define CONFIG_CMD_NAND | |
191 | #define CONFIG_CMD_I2C | |
192 | #define CONFIG_CMD_SNTP | |
193 | ||
9dd41a7b WD |
194 | |
195 | /* | |
196 | * Miscellaneous configurable options | |
197 | */ | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
199 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
348f258f | 200 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 201 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
9dd41a7b | 202 | #else |
6d0f6bcf | 203 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
9dd41a7b | 204 | #endif |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
206 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
207 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
9dd41a7b | 208 | |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
210 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
9dd41a7b | 211 | |
6d0f6bcf | 212 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
9dd41a7b | 213 | |
6d0f6bcf | 214 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
9dd41a7b | 215 | |
6d0f6bcf | 216 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
9dd41a7b | 217 | |
6d0f6bcf | 218 | #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ |
9dd41a7b WD |
219 | |
220 | /* | |
221 | * For booting Linux, the board info and command line data | |
222 | * have to be in the first 8 MB of memory, since this is | |
223 | * the maximum mapped by the Linux kernel during initialization. | |
224 | */ | |
6d0f6bcf | 225 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
9dd41a7b | 226 | |
6d0f6bcf | 227 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 228 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 } |
230 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 | |
9dd41a7b WD |
231 | /* What should the base address of the main FLASH be and how big is |
232 | * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk | |
233 | * The main FLASH is whichever is connected to *CS0. | |
234 | */ | |
6d0f6bcf JCPV |
235 | #define CONFIG_SYS_FLASH0_BASE 0xFFF00000 |
236 | #define CONFIG_SYS_FLASH0_SIZE 8 | |
9dd41a7b WD |
237 | |
238 | /* Flash bank size (for preliminary settings) | |
239 | */ | |
6d0f6bcf | 240 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE |
9dd41a7b WD |
241 | |
242 | /*----------------------------------------------------------------------- | |
243 | * FLASH organization | |
244 | */ | |
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
246 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
9dd41a7b | 247 | |
6d0f6bcf JCPV |
248 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
249 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
9dd41a7b WD |
250 | |
251 | /* Environment in flash */ | |
5a1aceb0 | 252 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 253 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000) |
0e8d1586 JCPV |
254 | #define CONFIG_ENV_SIZE 0x20000 |
255 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
9dd41a7b WD |
256 | |
257 | /*----------------------------------------------------------------------- | |
258 | * NAND-FLASH stuff | |
259 | *----------------------------------------------------------------------- | |
260 | */ | |
348f258f | 261 | #if defined(CONFIG_CMD_NAND) |
9dd41a7b | 262 | |
6d0f6bcf | 263 | #define CONFIG_SYS_NAND0_BASE 0xE1000000 |
6d0f6bcf | 264 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
9dd41a7b | 265 | |
11799434 | 266 | #endif /* CONFIG_CMD_NAND */ |
9dd41a7b WD |
267 | |
268 | /*----------------------------------------------------------------------- | |
269 | * Hard Reset Configuration Words | |
270 | * | |
6d0f6bcf | 271 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
9dd41a7b | 272 | * defines for the various registers affected by the HRCW e.g. changing |
6d0f6bcf | 273 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
9dd41a7b | 274 | */ |
6d0f6bcf | 275 | #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000) |
9dd41a7b WD |
276 | |
277 | /* no slaves so just fill with zeros */ | |
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
279 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
280 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
281 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
282 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
283 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
284 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
9dd41a7b WD |
285 | |
286 | /*----------------------------------------------------------------------- | |
287 | * Internal Memory Mapped Register | |
288 | */ | |
6d0f6bcf | 289 | #define CONFIG_SYS_IMMR 0xF0000000 |
9dd41a7b WD |
290 | |
291 | /*----------------------------------------------------------------------- | |
292 | * Definitions for initial stack pointer and data area (in DPRAM) | |
293 | */ | |
6d0f6bcf JCPV |
294 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
295 | #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ | |
296 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ | |
297 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
298 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
9dd41a7b WD |
299 | |
300 | /*----------------------------------------------------------------------- | |
301 | * Start addresses for the final memory configuration | |
302 | * (Set up by the startup code) | |
6d0f6bcf | 303 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
9dd41a7b | 304 | * |
6d0f6bcf | 305 | * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE |
9dd41a7b | 306 | */ |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
308 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE | |
309 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
310 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
311 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
9dd41a7b WD |
312 | |
313 | /* | |
314 | * Internal Definitions | |
315 | * | |
316 | * Boot Flags | |
317 | */ | |
318 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
319 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
320 | ||
321 | ||
322 | /*----------------------------------------------------------------------- | |
323 | * Cache Configuration | |
324 | */ | |
6d0f6bcf | 325 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
348f258f | 326 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 327 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
9dd41a7b WD |
328 | #endif |
329 | ||
330 | /*----------------------------------------------------------------------- | |
331 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
332 | *----------------------------------------------------------------------- | |
333 | * HID0 also contains cache control - initially enable both caches and | |
334 | * invalidate contents, then the final state leaves only the instruction | |
335 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
336 | * but Soft reset does not. | |
337 | * | |
338 | * HID1 has only read-only information - nothing to set. | |
339 | */ | |
340 | ||
6d0f6bcf JCPV |
341 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) |
342 | #define CONFIG_SYS_HID0_FINAL 0 | |
343 | #define CONFIG_SYS_HID2 0 | |
9dd41a7b WD |
344 | |
345 | /*----------------------------------------------------------------------- | |
346 | * RMR - Reset Mode Register 5-5 | |
347 | *----------------------------------------------------------------------- | |
348 | * turn on Checkstop Reset Enable | |
349 | */ | |
6d0f6bcf | 350 | #define CONFIG_SYS_RMR 0 |
9dd41a7b WD |
351 | |
352 | /*----------------------------------------------------------------------- | |
353 | * BCR - Bus Configuration 4-25 | |
354 | *----------------------------------------------------------------------- | |
355 | */ | |
6d0f6bcf | 356 | #define CONFIG_SYS_BCR 0 |
9dd41a7b WD |
357 | |
358 | /*----------------------------------------------------------------------- | |
359 | * SIUMCR - SIU Module Configuration 4-31 | |
360 | *----------------------------------------------------------------------- | |
361 | */ | |
6d0f6bcf | 362 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01) |
9dd41a7b WD |
363 | |
364 | /*----------------------------------------------------------------------- | |
365 | * SYPCR - System Protection Control 4-35 | |
366 | * SYPCR can only be written once after reset! | |
367 | *----------------------------------------------------------------------- | |
368 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
369 | */ | |
370 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 371 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
9dd41a7b WD |
372 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
373 | #else | |
6d0f6bcf | 374 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
9dd41a7b WD |
375 | SYPCR_SWRI|SYPCR_SWP) |
376 | #endif /* CONFIG_WATCHDOG */ | |
377 | ||
378 | /*----------------------------------------------------------------------- | |
379 | * TMCNTSC - Time Counter Status and Control 4-40 | |
380 | *----------------------------------------------------------------------- | |
381 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
382 | * and enable Time Counter | |
383 | */ | |
6d0f6bcf | 384 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
9dd41a7b WD |
385 | |
386 | /*----------------------------------------------------------------------- | |
387 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
388 | *----------------------------------------------------------------------- | |
389 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
390 | * Periodic timer | |
391 | */ | |
6d0f6bcf | 392 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
9dd41a7b WD |
393 | |
394 | /*----------------------------------------------------------------------- | |
395 | * SCCR - System Clock Control 9-8 | |
396 | *----------------------------------------------------------------------- | |
397 | * Ensure DFBRG is Divide by 16 | |
398 | */ | |
6d0f6bcf | 399 | #define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01) |
9dd41a7b WD |
400 | |
401 | /*----------------------------------------------------------------------- | |
402 | * RCCR - RISC Controller Configuration 13-7 | |
403 | *----------------------------------------------------------------------- | |
404 | */ | |
6d0f6bcf | 405 | #define CONFIG_SYS_RCCR 0 |
9dd41a7b WD |
406 | |
407 | /* | |
408 | * Init Memory Controller: | |
409 | * | |
410 | * Bank Bus Machine PortSz Device | |
411 | * ---- --- ------- ------ ------ | |
412 | * 0 60x GPCM 16 bit FLASH | |
413 | * 1 60x GPCM 8 bit NAND | |
414 | * 2 60x SDRAM 32 bit SDRAM | |
415 | * 3 60x GPCM 8 bit UART | |
416 | * | |
417 | */ | |
418 | ||
419 | #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
420 | ||
421 | /* Minimum mask to separate preliminary | |
422 | * address ranges for CS[0:2] | |
423 | */ | |
6d0f6bcf | 424 | #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */ |
9dd41a7b | 425 | |
6d0f6bcf | 426 | #define CONFIG_SYS_MPTPR 0x6600 |
9dd41a7b WD |
427 | |
428 | /*----------------------------------------------------------------------------- | |
429 | * Address for Mode Register Set (MRS) command | |
430 | *----------------------------------------------------------------------------- | |
431 | */ | |
6d0f6bcf | 432 | #define CONFIG_SYS_MRS_OFFS 0x00000110 |
9dd41a7b WD |
433 | |
434 | ||
435 | /* Bank 0 - FLASH | |
436 | */ | |
6d0f6bcf | 437 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
9dd41a7b WD |
438 | BRx_PS_8 |\ |
439 | BRx_MS_GPCM_P |\ | |
440 | BRx_V) | |
441 | ||
6d0f6bcf | 442 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
9dd41a7b WD |
443 | ORxG_SCY_6_CLK ) |
444 | ||
348f258f | 445 | #if defined(CONFIG_CMD_NAND) |
9dd41a7b WD |
446 | /* Bank 1 - NAND Flash |
447 | */ | |
6d0f6bcf JCPV |
448 | #define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE |
449 | #define CONFIG_SYS_NAND_SIZE 0x8000 | |
9dd41a7b | 450 | |
6d0f6bcf | 451 | #define CONFIG_SYS_OR_TIMING_NAND 0x000036 |
9dd41a7b | 452 | |
6d0f6bcf JCPV |
453 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) |
454 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND ) | |
9dd41a7b WD |
455 | #endif |
456 | ||
457 | /* Bank 2 - 60x bus SDRAM | |
458 | */ | |
6d0f6bcf JCPV |
459 | #define CONFIG_SYS_PSRT 0x20 |
460 | #define CONFIG_SYS_LSRT 0x20 | |
9dd41a7b | 461 | |
6d0f6bcf | 462 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ |
9dd41a7b WD |
463 | BRx_PS_32 |\ |
464 | BRx_MS_SDRAM_P |\ | |
465 | BRx_V) | |
466 | ||
6d0f6bcf | 467 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2 |
9dd41a7b WD |
468 | |
469 | ||
470 | /* SDRAM initialization values | |
471 | */ | |
6d0f6bcf | 472 | #define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
9dd41a7b | 473 | ORxS_BPD_4 |\ |
6abd82e1 | 474 | ORxS_ROWST_PBI0_A9 |\ |
9dd41a7b WD |
475 | ORxS_NUMR_12) |
476 | ||
6d0f6bcf | 477 | #define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ |
9dd41a7b | 478 | PSDMR_BSMA_A15_A17 |\ |
6abd82e1 | 479 | PSDMR_SDA10_PBI0_A10 |\ |
9dd41a7b WD |
480 | PSDMR_RFRC_5_CLK |\ |
481 | PSDMR_PRETOACT_2W |\ | |
482 | PSDMR_ACTTORW_2W |\ | |
483 | PSDMR_BL |\ | |
484 | PSDMR_LDOTOPRE_2C |\ | |
485 | PSDMR_WRC_3C |\ | |
486 | PSDMR_CL_3) | |
487 | ||
488 | /* Bank 3 - UART | |
489 | */ | |
490 | ||
6d0f6bcf JCPV |
491 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) |
492 | #define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX ) | |
9dd41a7b WD |
493 | |
494 | #endif /* __CONFIG_H */ |