projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 9dd41a7b WD |
1 | /* |
| 2 | * (C) Copyright 2005 | |
| 3 | * Heiko Schocher, DENX Software Engineering, <hs@denx.de> | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 31 | /* | |
| 32 | * High Level Configuration Options | |
| 33 | * (easy to change) | |
| 34 | */ | |
| 35 | ||
| 36 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ | |
| 37 | #define CONFIG_MPC8272_FAMILY 1 | |
| 38 | #define CONFIG_IDS8247 1 | |
| 39 | #define CPU_ID_STR "MPC8247" | |
| 9c4c5ae3 | 40 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
| 9dd41a7b WD |
41 | |
| 42 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 43 | ||
| 44 | #define CONFIG_BOOTCOUNT_LIMIT | |
| 45 | ||
| 32bf3d14 | 46 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
| 9dd41a7b WD |
47 | |
| 48 | #undef CONFIG_BOOTARGS | |
| 49 | ||
| 50 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 51 | "netdev=eth0\0" \ | |
| 52 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| fe126d8b | 53 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 9dd41a7b WD |
54 | "ramargs=setenv bootargs root=/dev/ram rw " \ |
| 55 | "console=ttyS0,115200\0" \ | |
| fe126d8b WD |
56 | "addip=setenv bootargs ${bootargs} " \ |
| 57 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 58 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 9dd41a7b | 59 | "flash_nfs=run nfsargs addip;" \ |
| fe126d8b | 60 | "bootm ${kernel_addr}\0" \ |
| 9dd41a7b | 61 | "flash_self=run ramargs addip;" \ |
| fe126d8b WD |
62 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 63 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
| 9dd41a7b WD |
64 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
| 65 | "bootfile=/tftpboot/IDS8247/uImage\0" \ | |
| 66 | "kernel_addr=ff800000\0" \ | |
| 67 | "ramdisk_addr=ffa00000\0" \ | |
| 68 | "" | |
| 69 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 70 | ||
| 71 | #define CONFIG_MISC_INIT_R 1 | |
| 72 | ||
| 73 | /* enable I2C and select the hardware/software driver */ | |
| 74 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 75 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
| 6d0f6bcf JCPV |
76 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 77 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 9dd41a7b WD |
78 | |
| 79 | /* | |
| 80 | * Software (bit-bang) I2C driver configuration | |
| 81 | */ | |
| 82 | ||
| 83 | #define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */ | |
| 84 | #define I2C_ACTIVE (iop->pdir |= 0x00000080) | |
| 85 | #define I2C_TRISTATE (iop->pdir &= ~0x00000080) | |
| 86 | #define I2C_READ ((iop->pdat & 0x00000080) != 0) | |
| 87 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \ | |
| 88 | else iop->pdat &= ~0x00000080 | |
| 89 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \ | |
| 90 | else iop->pdat &= ~0x00000100 | |
| 91 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
| 92 | ||
| 93 | #if 0 | |
| 6d0f6bcf JCPV |
94 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
| 95 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
| 96 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
| 97 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
| 9dd41a7b WD |
98 | |
| 99 | #define CONFIG_I2C_X | |
| 100 | #endif | |
| 101 | ||
| 102 | /* | |
| 103 | * select serial console configuration | |
| 104 | * use the extern UART for the console | |
| 105 | */ | |
| 106 | #define CONFIG_CONS_INDEX 1 | |
| 107 | #define CONFIG_BAUDRATE 115200 | |
| 108 | /* | |
| 109 | * NS16550 Configuration | |
| 110 | */ | |
| 6d0f6bcf JCPV |
111 | #define CONFIG_SYS_NS16550 |
| 112 | #define CONFIG_SYS_NS16550_SERIAL | |
| 9dd41a7b | 113 | |
| 6d0f6bcf | 114 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 9dd41a7b | 115 | |
| 6d0f6bcf | 116 | #define CONFIG_SYS_NS16550_CLK 14745600 |
| 9dd41a7b | 117 | |
| 6d0f6bcf JCPV |
118 | #define CONFIG_SYS_UART_BASE 0xE0000000 |
| 119 | #define CONFIG_SYS_UART_SIZE 0x10000 | |
| 9dd41a7b | 120 | |
| 6d0f6bcf | 121 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000) |
| 9dd41a7b | 122 | |
| 6abd82e1 SS |
123 | |
| 124 | /* pass open firmware flat tree */ | |
| 125 | #define CONFIG_OF_LIBFDT 1 | |
| 126 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 127 | ||
| 128 | #define OF_CPU "PowerPC,8247@0" | |
| 129 | #define OF_SOC "soc@f0000000" | |
| 130 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
| 131 | #define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" | |
| 132 | ||
| 133 | ||
| 9dd41a7b WD |
134 | /* |
| 135 | * select ethernet configuration | |
| 136 | * | |
| 137 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
| 138 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
| 139 | * for FCC) | |
| 140 | * | |
| 141 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
| 639221c7 | 142 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
| 9dd41a7b WD |
143 | */ |
| 144 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
| 145 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
| 146 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
| 6abd82e1 SS |
147 | #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ |
| 148 | #define CONFIG_ETHER_ON_FCC1 | |
| 149 | #define FCC_ENET | |
| 9dd41a7b WD |
150 | |
| 151 | /* | |
| 6abd82e1 SS |
152 | * - Rx-CLK is CLK10 |
| 153 | * - Tx-CLK is CLK9 | |
| 9dd41a7b WD |
154 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
| 155 | * - Enable Full Duplex in FSMR | |
| 156 | */ | |
| 6d0f6bcf JCPV |
157 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) |
| 158 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9) | |
| 159 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
| 160 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
| 9dd41a7b WD |
161 | |
| 162 | ||
| 163 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
| 164 | #define CONFIG_8260_CLKIN 66666666 /* in Hz */ | |
| 165 | ||
| 166 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 167 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
| 9dd41a7b WD |
168 | |
| 169 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 170 | ||
| 171 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
| 172 | ||
| 7be044e4 JL |
173 | /* |
| 174 | * BOOTP options | |
| 175 | */ | |
| 176 | #define CONFIG_BOOTP_SUBNETMASK | |
| 177 | #define CONFIG_BOOTP_GATEWAY | |
| 178 | #define CONFIG_BOOTP_HOSTNAME | |
| 179 | #define CONFIG_BOOTP_BOOTPATH | |
| 180 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 9dd41a7b | 181 | |
| 6abd82e1 | 182 | #define CONFIG_RTC_PCF8563 |
| 6d0f6bcf | 183 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
| 9dd41a7b | 184 | |
| 348f258f JL |
185 | /* |
| 186 | * Command line configuration. | |
| 187 | */ | |
| 188 | #include <config_cmd_default.h> | |
| 189 | ||
| 190 | #define CONFIG_CMD_DHCP | |
| 191 | #define CONFIG_CMD_NFS | |
| 192 | #define CONFIG_CMD_NAND | |
| 193 | #define CONFIG_CMD_I2C | |
| 194 | #define CONFIG_CMD_SNTP | |
| 195 | ||
| 9dd41a7b WD |
196 | |
| 197 | /* | |
| 198 | * Miscellaneous configurable options | |
| 199 | */ | |
| 6d0f6bcf JCPV |
200 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 201 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 348f258f | 202 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 203 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 9dd41a7b | 204 | #else |
| 6d0f6bcf | 205 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 9dd41a7b | 206 | #endif |
| 6d0f6bcf JCPV |
207 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 208 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 209 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 9dd41a7b | 210 | |
| 6d0f6bcf JCPV |
211 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 212 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 9dd41a7b | 213 | |
| 6d0f6bcf | 214 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 9dd41a7b | 215 | |
| 6d0f6bcf | 216 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 9dd41a7b | 217 | |
| 6d0f6bcf | 218 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 9dd41a7b | 219 | |
| 6d0f6bcf | 220 | #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ |
| 9dd41a7b WD |
221 | |
| 222 | /* | |
| 223 | * For booting Linux, the board info and command line data | |
| 224 | * have to be in the first 8 MB of memory, since this is | |
| 225 | * the maximum mapped by the Linux kernel during initialization. | |
| 226 | */ | |
| 6d0f6bcf | 227 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 9dd41a7b | 228 | |
| 6d0f6bcf | 229 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
| 00b1883a | 230 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
| 6d0f6bcf JCPV |
231 | #define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 } |
| 232 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 | |
| 9dd41a7b WD |
233 | /* What should the base address of the main FLASH be and how big is |
| 234 | * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk | |
| 235 | * The main FLASH is whichever is connected to *CS0. | |
| 236 | */ | |
| 6d0f6bcf JCPV |
237 | #define CONFIG_SYS_FLASH0_BASE 0xFFF00000 |
| 238 | #define CONFIG_SYS_FLASH0_SIZE 8 | |
| 9dd41a7b WD |
239 | |
| 240 | /* Flash bank size (for preliminary settings) | |
| 241 | */ | |
| 6d0f6bcf | 242 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE |
| 9dd41a7b WD |
243 | |
| 244 | /*----------------------------------------------------------------------- | |
| 245 | * FLASH organization | |
| 246 | */ | |
| 6d0f6bcf JCPV |
247 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
| 248 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
| 9dd41a7b | 249 | |
| 6d0f6bcf JCPV |
250 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
| 251 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
| 9dd41a7b WD |
252 | |
| 253 | /* Environment in flash */ | |
| 5a1aceb0 | 254 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 6d0f6bcf | 255 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000) |
| 0e8d1586 JCPV |
256 | #define CONFIG_ENV_SIZE 0x20000 |
| 257 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
| 9dd41a7b WD |
258 | |
| 259 | /*----------------------------------------------------------------------- | |
| 260 | * NAND-FLASH stuff | |
| 261 | *----------------------------------------------------------------------- | |
| 262 | */ | |
| 348f258f | 263 | #if defined(CONFIG_CMD_NAND) |
| 9dd41a7b | 264 | |
| cc4a0cee | 265 | #define CONFIG_NAND_LEGACY |
| 6d0f6bcf | 266 | #define CONFIG_SYS_NAND0_BASE 0xE1000000 |
| 9dd41a7b | 267 | |
| 6d0f6bcf | 268 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
| 9dd41a7b WD |
269 | #define SECTORSIZE 512 |
| 270 | #define NAND_NO_RB | |
| 271 | ||
| 272 | #define ADDR_COLUMN 1 | |
| 273 | #define ADDR_PAGE 2 | |
| 274 | #define ADDR_COLUMN_PAGE 3 | |
| 275 | ||
| 276 | #define NAND_ChipID_UNKNOWN 0x00 | |
| 277 | #define NAND_MAX_FLOORS 1 | |
| 278 | #define NAND_MAX_CHIPS 1 | |
| 279 | ||
| 280 | #define NAND_DISABLE_CE(nand) do \ | |
| 281 | { \ | |
| 282 | *(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \ | |
| 283 | } while(0) | |
| 284 | ||
| 285 | #define NAND_ENABLE_CE(nand) do \ | |
| 286 | { \ | |
| 287 | *(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \ | |
| 288 | } while(0) | |
| 289 | ||
| 290 | #define NAND_CTL_CLRALE(nandptr) do \ | |
| 291 | { \ | |
| 292 | *(((volatile __u8 *)nandptr) + 0x8) = 0; \ | |
| 293 | } while(0) | |
| 294 | ||
| 295 | #define NAND_CTL_SETALE(nandptr) do \ | |
| 296 | { \ | |
| 297 | *(((volatile __u8 *)nandptr) + 0x9) = 0; \ | |
| 298 | } while(0) | |
| 299 | ||
| 300 | #define NAND_CTL_CLRCLE(nandptr) do \ | |
| 301 | { \ | |
| 302 | *(((volatile __u8 *)nandptr) + 0x8) = 0; \ | |
| 303 | } while(0) | |
| 304 | ||
| 305 | #define NAND_CTL_SETCLE(nandptr) do \ | |
| 306 | { \ | |
| 307 | *(((volatile __u8 *)nandptr) + 0xa) = 0; \ | |
| 308 | } while(0) | |
| 309 | ||
| 310 | #ifdef NAND_NO_RB | |
| 311 | /* constant delay (see also tR in the datasheet) */ | |
| 312 | #define NAND_WAIT_READY(nand) do { \ | |
| 313 | udelay(12); \ | |
| 314 | } while (0) | |
| 315 | #else | |
| 316 | /* use the R/B pin */ | |
| 317 | #endif | |
| 318 | ||
| 319 | #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0) | |
| 320 | #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0) | |
| 321 | #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0) | |
| 322 | #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0))) | |
| 323 | ||
| 11799434 | 324 | #endif /* CONFIG_CMD_NAND */ |
| 9dd41a7b WD |
325 | |
| 326 | /*----------------------------------------------------------------------- | |
| 327 | * Hard Reset Configuration Words | |
| 328 | * | |
| 6d0f6bcf | 329 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
| 9dd41a7b | 330 | * defines for the various registers affected by the HRCW e.g. changing |
| 6d0f6bcf | 331 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
| 9dd41a7b | 332 | */ |
| 6d0f6bcf | 333 | #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000) |
| 9dd41a7b WD |
334 | |
| 335 | /* no slaves so just fill with zeros */ | |
| 6d0f6bcf JCPV |
336 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
| 337 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
| 338 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
| 339 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
| 340 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
| 341 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
| 342 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
| 9dd41a7b WD |
343 | |
| 344 | /*----------------------------------------------------------------------- | |
| 345 | * Internal Memory Mapped Register | |
| 346 | */ | |
| 6d0f6bcf | 347 | #define CONFIG_SYS_IMMR 0xF0000000 |
| 9dd41a7b WD |
348 | |
| 349 | /*----------------------------------------------------------------------- | |
| 350 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 351 | */ | |
| 6d0f6bcf JCPV |
352 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
| 353 | #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ | |
| 354 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ | |
| 355 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 356 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 9dd41a7b WD |
357 | |
| 358 | /*----------------------------------------------------------------------- | |
| 359 | * Start addresses for the final memory configuration | |
| 360 | * (Set up by the startup code) | |
| 6d0f6bcf | 361 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 9dd41a7b | 362 | * |
| 6d0f6bcf | 363 | * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE |
| 9dd41a7b | 364 | */ |
| 6d0f6bcf JCPV |
365 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 366 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE | |
| 367 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
| 368 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 369 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
| 9dd41a7b WD |
370 | |
| 371 | /* | |
| 372 | * Internal Definitions | |
| 373 | * | |
| 374 | * Boot Flags | |
| 375 | */ | |
| 376 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
| 377 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 378 | ||
| 379 | ||
| 380 | /*----------------------------------------------------------------------- | |
| 381 | * Cache Configuration | |
| 382 | */ | |
| 6d0f6bcf | 383 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
| 348f258f | 384 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 385 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 9dd41a7b WD |
386 | #endif |
| 387 | ||
| 388 | /*----------------------------------------------------------------------- | |
| 389 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
| 390 | *----------------------------------------------------------------------- | |
| 391 | * HID0 also contains cache control - initially enable both caches and | |
| 392 | * invalidate contents, then the final state leaves only the instruction | |
| 393 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
| 394 | * but Soft reset does not. | |
| 395 | * | |
| 396 | * HID1 has only read-only information - nothing to set. | |
| 397 | */ | |
| 398 | ||
| 6d0f6bcf JCPV |
399 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) |
| 400 | #define CONFIG_SYS_HID0_FINAL 0 | |
| 401 | #define CONFIG_SYS_HID2 0 | |
| 9dd41a7b WD |
402 | |
| 403 | /*----------------------------------------------------------------------- | |
| 404 | * RMR - Reset Mode Register 5-5 | |
| 405 | *----------------------------------------------------------------------- | |
| 406 | * turn on Checkstop Reset Enable | |
| 407 | */ | |
| 6d0f6bcf | 408 | #define CONFIG_SYS_RMR 0 |
| 9dd41a7b WD |
409 | |
| 410 | /*----------------------------------------------------------------------- | |
| 411 | * BCR - Bus Configuration 4-25 | |
| 412 | *----------------------------------------------------------------------- | |
| 413 | */ | |
| 6d0f6bcf | 414 | #define CONFIG_SYS_BCR 0 |
| 9dd41a7b WD |
415 | |
| 416 | /*----------------------------------------------------------------------- | |
| 417 | * SIUMCR - SIU Module Configuration 4-31 | |
| 418 | *----------------------------------------------------------------------- | |
| 419 | */ | |
| 6d0f6bcf | 420 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01) |
| 9dd41a7b WD |
421 | |
| 422 | /*----------------------------------------------------------------------- | |
| 423 | * SYPCR - System Protection Control 4-35 | |
| 424 | * SYPCR can only be written once after reset! | |
| 425 | *----------------------------------------------------------------------- | |
| 426 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
| 427 | */ | |
| 428 | #if defined(CONFIG_WATCHDOG) | |
| 6d0f6bcf | 429 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
| 9dd41a7b WD |
430 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
| 431 | #else | |
| 6d0f6bcf | 432 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
| 9dd41a7b WD |
433 | SYPCR_SWRI|SYPCR_SWP) |
| 434 | #endif /* CONFIG_WATCHDOG */ | |
| 435 | ||
| 436 | /*----------------------------------------------------------------------- | |
| 437 | * TMCNTSC - Time Counter Status and Control 4-40 | |
| 438 | *----------------------------------------------------------------------- | |
| 439 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
| 440 | * and enable Time Counter | |
| 441 | */ | |
| 6d0f6bcf | 442 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
| 9dd41a7b WD |
443 | |
| 444 | /*----------------------------------------------------------------------- | |
| 445 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
| 446 | *----------------------------------------------------------------------- | |
| 447 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
| 448 | * Periodic timer | |
| 449 | */ | |
| 6d0f6bcf | 450 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
| 9dd41a7b WD |
451 | |
| 452 | /*----------------------------------------------------------------------- | |
| 453 | * SCCR - System Clock Control 9-8 | |
| 454 | *----------------------------------------------------------------------- | |
| 455 | * Ensure DFBRG is Divide by 16 | |
| 456 | */ | |
| 6d0f6bcf | 457 | #define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01) |
| 9dd41a7b WD |
458 | |
| 459 | /*----------------------------------------------------------------------- | |
| 460 | * RCCR - RISC Controller Configuration 13-7 | |
| 461 | *----------------------------------------------------------------------- | |
| 462 | */ | |
| 6d0f6bcf | 463 | #define CONFIG_SYS_RCCR 0 |
| 9dd41a7b WD |
464 | |
| 465 | /* | |
| 466 | * Init Memory Controller: | |
| 467 | * | |
| 468 | * Bank Bus Machine PortSz Device | |
| 469 | * ---- --- ------- ------ ------ | |
| 470 | * 0 60x GPCM 16 bit FLASH | |
| 471 | * 1 60x GPCM 8 bit NAND | |
| 472 | * 2 60x SDRAM 32 bit SDRAM | |
| 473 | * 3 60x GPCM 8 bit UART | |
| 474 | * | |
| 475 | */ | |
| 476 | ||
| 477 | #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
| 478 | ||
| 479 | /* Minimum mask to separate preliminary | |
| 480 | * address ranges for CS[0:2] | |
| 481 | */ | |
| 6d0f6bcf | 482 | #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */ |
| 9dd41a7b | 483 | |
| 6d0f6bcf | 484 | #define CONFIG_SYS_MPTPR 0x6600 |
| 9dd41a7b WD |
485 | |
| 486 | /*----------------------------------------------------------------------------- | |
| 487 | * Address for Mode Register Set (MRS) command | |
| 488 | *----------------------------------------------------------------------------- | |
| 489 | */ | |
| 6d0f6bcf | 490 | #define CONFIG_SYS_MRS_OFFS 0x00000110 |
| 9dd41a7b WD |
491 | |
| 492 | ||
| 493 | /* Bank 0 - FLASH | |
| 494 | */ | |
| 6d0f6bcf | 495 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
| 9dd41a7b WD |
496 | BRx_PS_8 |\ |
| 497 | BRx_MS_GPCM_P |\ | |
| 498 | BRx_V) | |
| 499 | ||
| 6d0f6bcf | 500 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
| 9dd41a7b WD |
501 | ORxG_SCY_6_CLK ) |
| 502 | ||
| 348f258f | 503 | #if defined(CONFIG_CMD_NAND) |
| 9dd41a7b WD |
504 | /* Bank 1 - NAND Flash |
| 505 | */ | |
| 6d0f6bcf JCPV |
506 | #define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE |
| 507 | #define CONFIG_SYS_NAND_SIZE 0x8000 | |
| 9dd41a7b | 508 | |
| 6d0f6bcf | 509 | #define CONFIG_SYS_OR_TIMING_NAND 0x000036 |
| 9dd41a7b | 510 | |
| 6d0f6bcf JCPV |
511 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) |
| 512 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND ) | |
| 9dd41a7b WD |
513 | #endif |
| 514 | ||
| 515 | /* Bank 2 - 60x bus SDRAM | |
| 516 | */ | |
| 6d0f6bcf JCPV |
517 | #define CONFIG_SYS_PSRT 0x20 |
| 518 | #define CONFIG_SYS_LSRT 0x20 | |
| 9dd41a7b | 519 | |
| 6d0f6bcf | 520 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ |
| 9dd41a7b WD |
521 | BRx_PS_32 |\ |
| 522 | BRx_MS_SDRAM_P |\ | |
| 523 | BRx_V) | |
| 524 | ||
| 6d0f6bcf | 525 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2 |
| 9dd41a7b WD |
526 | |
| 527 | ||
| 528 | /* SDRAM initialization values | |
| 529 | */ | |
| 6d0f6bcf | 530 | #define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
| 9dd41a7b | 531 | ORxS_BPD_4 |\ |
| 6abd82e1 | 532 | ORxS_ROWST_PBI0_A9 |\ |
| 9dd41a7b WD |
533 | ORxS_NUMR_12) |
| 534 | ||
| 6d0f6bcf | 535 | #define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ |
| 9dd41a7b | 536 | PSDMR_BSMA_A15_A17 |\ |
| 6abd82e1 | 537 | PSDMR_SDA10_PBI0_A10 |\ |
| 9dd41a7b WD |
538 | PSDMR_RFRC_5_CLK |\ |
| 539 | PSDMR_PRETOACT_2W |\ | |
| 540 | PSDMR_ACTTORW_2W |\ | |
| 541 | PSDMR_BL |\ | |
| 542 | PSDMR_LDOTOPRE_2C |\ | |
| 543 | PSDMR_WRC_3C |\ | |
| 544 | PSDMR_CL_3) | |
| 545 | ||
| 546 | /* Bank 3 - UART | |
| 547 | */ | |
| 548 | ||
| 6d0f6bcf JCPV |
549 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) |
| 550 | #define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX ) | |
| 9dd41a7b WD |
551 | |
| 552 | #endif /* __CONFIG_H */ |