[people/ms/u-boot.git] / include / configs / IPHASE4539.h

/*
 * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
 *
 * This file is based on similar values for other boards found in
 * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

/*
 * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
#define CONFIG_IPHASE4539	1	/* ...on a Interphase 4539 PMC */

#define	CONFIG_SYS_TEXT_BASE	0xffb00000

#define CONFIG_CPM2		1	/* Has a CPM2 */

/*-----------------------------------------------------------------------
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define	CONFIG_CONS_ON_SMC		/* define if console on SMC */
#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef	CONFIG_CONS_NONE		/* define if console on something else */
#define CONFIG_CONS_INDEX	1	/* which serial channel for console */

/*-----------------------------------------------------------------------
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_INDEX	3	/* which channel for ether  */

#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)

/*-----------------------------------------------------------------------
 * - Rx-CLK is CLK14
 * - Tx-CLK is CLK16
 * - Select bus for bd/buffers (see 28-13)
 * - Half duplex
 */
# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
# define CONFIG_SYS_CPMFCR_RAMTYPE	0
# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)

#endif	/* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */

/* other options */

#define CONFIG_8260_CLKIN	66666666	/* in Hz */
#define CONFIG_BAUDRATE		19200

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * select i2c support configuration
 *
 * Supported configurations are {none, software, hardware} drivers.
 * If the software driver is chosen, there are some additional
 * configuration items that the driver uses to drive the port pins.
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	400000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
/*
 * Software (bit-bang) I2C driver configuration
 */
#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
#define I2C_READ	((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
			else    iop->pdat &= ~0x00010000
#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
			else    iop->pdat &= ~0x00020000
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* autoboot command */
#define CONFIG_BOOTARGS		"root=/dev/ram rw"

#if defined(CONFIG_CMD_KGDB)
#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
#endif

#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passed to Linux in MHz */
					/* for versions < 2.4.5-pre5	 */

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_RESET_ADDRESS	0x04400000

#define CONFIG_MISC_INIT_R	1	/* We need misc_init_r()	*/

/*-----------------------------------------------------------------------
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration (Setup by the
 * startup code). Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0.
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFF800000

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)     /* Reserve 256 kB for Monitor  */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
#define CONFIG_SYS_MAX_FLASH_SIZE	(CONFIG_SYS_MAX_FLASH_SECT * 0x10000)	/* 4 MB */

#define CONFIG_SYS_FLASH_ERASE_TOUT	2400000	/* Flash Erase Timeout (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

/* Environment in FLASH, there is little space left in Serial EEPROM */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	0x10000 /* We use one complete sector	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */


/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 */
#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM )		|\
			  ( HRCW_L2CPC10 | HRCW_ISB110 )	|\
			  ( HRCW_MMR11 | HRCW_APPC10 )		|\
			  ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )	 \
			) /* 0x14863245 */

/* no slaves */
#define CONFIG_SYS_HRCW_SLAVE1 0
#define CONFIG_SYS_HRCW_SLAVE2 0
#define CONFIG_SYS_HRCW_SLAVE3 0
#define CONFIG_SYS_HRCW_SLAVE4 0
#define CONFIG_SYS_HRCW_SLAVE5 0
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000 /* We keep original value */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32     /* For MPC8260 CPU		*/
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT	5      /* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers		2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
			 HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID0_FINAL	(HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID2	0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register					 5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CONFIG_SYS_RMR		RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration					 4-25
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_BCR		0xA01C0000

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				 4-31
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SIUMCR	0X4205C000

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				 4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined (CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control			 4-40
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control					 9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 16
 */
#define CONFIG_SYS_SCCR	0

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration				13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR	0

/*-----------------------------------------------------------------------
 * Init Memory Controller:
 *
 * Bank Bus	Machine PortSz	Device
 * ---- ---	------- ------	------
 *  0	60x	GPCM	64 bit	FLASH
 *  1	60x	SDRAM	64 bit	SDRAM
 */

#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) | 0x0801)
#define CONFIG_SYS_OR0_PRELIM	0xFF800882
#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
#define CONFIG_SYS_OR1_PRELIM	0xF8002CD0

#define CONFIG_SYS_PSDMR	0x404A241A
#define CONFIG_SYS_MPTPR	0x00007400
#define CONFIG_SYS_PSRT	0x00000007

#endif /* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
	3	*
	4	* This file is based on similar values for other boards found in
	5	* other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
e2211743 WD	8	*/
	9
	10	/*
	11	* Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
e2211743 WD	17	/*-----------------------------------------------------------------------
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21
	22	#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
	23	#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
	24
2ae18241 WD	25	#define CONFIG_SYS_TEXT_BASE 0xffb00000
2ae18241 WD	26
9c4c5ae3 JL	27	#define CONFIG_CPM2 1 /* Has a CPM2 */
9c4c5ae3 JL	28
e2211743 WD	29	/*-----------------------------------------------------------------------
	30	* select serial console configuration
	31	*
	32	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	33	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	34	* for SCC).
	35	*
	36	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	37	* defined elsewhere (for example, on the cogent platform, there are serial
	38	* ports on the motherboard which are used for the serial console - see
	39	* cogent/cma101/serial.[ch]).
	40	*/
	41	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
	42	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	43	#undef CONFIG_CONS_NONE /* define if console on something else */
	44	#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
	45
	46	/*-----------------------------------------------------------------------
	47	* select ethernet configuration
	48	*
	49	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	50	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	51	* for FCC)
	52	*
	53	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	54	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
e2211743 WD	55	*/
	56	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	57	#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
	58	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	59	#define CONFIG_ETHER_INDEX 3 /* which channel for ether */
	60
	61	#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
	62
	63	/*-----------------------------------------------------------------------
	64	* - Rx-CLK is CLK14
	65	* - Tx-CLK is CLK16
	66	* - Select bus for bd/buffers (see 28-13)
	67	* - Half duplex
	68	*/
d4590da4 MF	69	# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 \| CMXFCR_RF3CS_MSK \| CMXFCR_TF3CS_MSK)
d4590da4 MF	70	# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 \| CMXFCR_TF3CS_CLK16)
6d0f6bcf JCPV	71	# define CONFIG_SYS_CPMFCR_RAMTYPE 0
6d0f6bcf JCPV	72	# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE\|FCC_PSMR_LPB)
e2211743 WD	73
	74	#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
	75
	76	/* other options */
	77
	78	#define CONFIG_8260_CLKIN 66666666 /* in Hz */
	79	#define CONFIG_BAUDRATE 19200
	80
7be044e4 JL	81	/*
	82	* BOOTP options
	83	*/
	84	#define CONFIG_BOOTP_SUBNETMASK
	85	#define CONFIG_BOOTP_GATEWAY
	86	#define CONFIG_BOOTP_HOSTNAME
	87	#define CONFIG_BOOTP_BOOTPATH
	88	#define CONFIG_BOOTP_BOOTFILESIZE
e2211743 WD	89
	90	/*
	91	* select i2c support configuration
	92	*
	93	* Supported configurations are {none, software, hardware} drivers.
	94	* If the software driver is chosen, there are some additional
	95	* configuration items that the driver uses to drive the port pins.
	96	*/
ea818dbb HS	97	#define CONFIG_SYS_I2C
	98	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	99	#define CONFIG_SYS_I2C_SOFT_SPEED 400000
	100	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
e2211743 WD	101	/*
	102	* Software (bit-bang) I2C driver configuration
	103	*/
e2211743 WD	104	#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
	105	#define I2C_ACTIVE (iop->pdir \|= 0x00010000)
	106	#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
	107	#define I2C_READ ((iop->pdat & 0x00010000) != 0)
	108	#define I2C_SDA(bit) if(bit) iop->pdat \|= 0x00010000; \
	109	else iop->pdat &= ~0x00010000
	110	#define I2C_SCL(bit) if(bit) iop->pdat \|= 0x00020000; \
	111	else iop->pdat &= ~0x00020000
	112	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
e2211743	113
e2211743	114
348f258f JL	115	/*
	116	* Command line configuration.
	117	*/
	118	#include <config_cmd_default.h>
e2211743 WD	119
	120
	121	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	122	#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
	123	#define CONFIG_BOOTARGS "root=/dev/ram rw"
	124
348f258f	125	#if defined(CONFIG_CMD_KGDB)
e2211743 WD	126	#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	127	#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	128	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
	129	#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
	130	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
	131	#endif
	132
	133	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
	134
	135	/*-----------------------------------------------------------------------
	136	* Miscellaneous configurable options
	137	*/
6d0f6bcf JCPV	138	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	139	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
348f258f	140	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	141	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e2211743	142	#else
6d0f6bcf	143	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743	144	#endif
6d0f6bcf JCPV	145	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	146	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	147	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
e2211743	148
6d0f6bcf JCPV	149	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	150	#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */
e2211743 WD	151
	152	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */
	153	/* for versions < 2.4.5-pre5 */
	154
6d0f6bcf	155	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
e2211743	156
6d0f6bcf	157	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
e2211743	158
6d0f6bcf	159	#define CONFIG_SYS_RESET_ADDRESS 0x04400000
e2211743 WD	160
	161	#define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */
	162
	163	/*-----------------------------------------------------------------------
	164	* For booting Linux, the board info and command line data
	165	* have to be in the first 8 MB of memory, since this is
	166	* the maximum mapped by the Linux kernel during initialization.
	167	*/
6d0f6bcf	168	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743 WD	169
	170	/*-----------------------------------------------------------------------
	171	* Start addresses for the final memory configuration (Setup by the
6d0f6bcf	172	* startup code). Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0.
e2211743	173	*/
6d0f6bcf JCPV	174	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	175	#define CONFIG_SYS_FLASH_BASE 0xFF800000
e2211743	176
14d0a02a	177	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	178	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6d0f6bcf JCPV	179	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
e2211743 WD	180
	181	/*-----------------------------------------------------------------------
	182	* FLASH organization
	183	*/
6d0f6bcf JCPV	184	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	185	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
	186	#define CONFIG_SYS_MAX_FLASH_SIZE (CONFIG_SYS_MAX_FLASH_SECT * 0x10000) /* 4 MB */
e2211743	187
6d0f6bcf JCPV	188	#define CONFIG_SYS_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
e2211743 WD	190
e2211743 WD	191	/* Environment in FLASH, there is little space left in Serial EEPROM */
5a1aceb0	192	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	193	#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
6d0f6bcf	194	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */
e2211743 WD	195
	196
	197	/*-----------------------------------------------------------------------
	198	* Hard Reset Configuration Words
	199	*
6d0f6bcf	200	* if you change bits in the HRCW, you must also change the CONFIG_SYS_*
e2211743	201	* defines for the various registers affected by the HRCW e.g. changing
6d0f6bcf	202	* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
e2211743	203	*/
6d0f6bcf	204	#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS01 \| HRCW_EBM ) \|\
e2211743 WD	205	( HRCW_L2CPC10 \| HRCW_ISB110 ) \|\
	206	( HRCW_MMR11 \| HRCW_APPC10 ) \|\
	207	( HRCW_CS10PC01 \| HRCW_MODCK_H0101 ) \
	208	) /* 0x14863245 */
	209
	210	/* no slaves */
6d0f6bcf JCPV	211	#define CONFIG_SYS_HRCW_SLAVE1 0
	212	#define CONFIG_SYS_HRCW_SLAVE2 0
	213	#define CONFIG_SYS_HRCW_SLAVE3 0
	214	#define CONFIG_SYS_HRCW_SLAVE4 0
	215	#define CONFIG_SYS_HRCW_SLAVE5 0
	216	#define CONFIG_SYS_HRCW_SLAVE6 0
	217	#define CONFIG_SYS_HRCW_SLAVE7 0
e2211743 WD	218
	219	/*-----------------------------------------------------------------------
	220	* Internal Memory Mapped Register
	221	*/
6d0f6bcf	222	#define CONFIG_SYS_IMMR 0xFF000000 /* We keep original value */
e2211743 WD	223
	224	/*-----------------------------------------------------------------------
	225	* Definitions for initial stack pointer and data area (in DPRAM)
	226	*/
6d0f6bcf	227	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	228	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
25ddd1fb	229	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	230	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e2211743	231
e2211743 WD	232	/*-----------------------------------------------------------------------
	233	* Cache Configuration
	234	*/
6d0f6bcf	235	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
348f258f	236	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	237	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
e2211743 WD	238	#endif
	239
	240	/*-----------------------------------------------------------------------
	241	* HIDx - Hardware Implementation-dependent Registers 2-11
	242	*-----------------------------------------------------------------------
	243	* HID0 also contains cache control.
	244	*
	245	* HID1 has only read-only information - nothing to set.
	246	*/
6d0f6bcf	247	#define CONFIG_SYS_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|HID0_DCI\|\
53677ef1	248	HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	249	#define CONFIG_SYS_HID0_FINAL (HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	250	#define CONFIG_SYS_HID2 0
e2211743 WD	251
	252	/*-----------------------------------------------------------------------
	253	* RMR - Reset Mode Register 5-5
	254	*-----------------------------------------------------------------------
	255	* turn on Checkstop Reset Enable
	256	*/
6d0f6bcf	257	#define CONFIG_SYS_RMR RMR_CSRE
e2211743 WD	258
	259	/*-----------------------------------------------------------------------
	260	* BCR - Bus Configuration 4-25
	261	*-----------------------------------------------------------------------
	262	*/
6d0f6bcf	263	#define CONFIG_SYS_BCR 0xA01C0000
e2211743 WD	264
	265	/*-----------------------------------------------------------------------
	266	* SIUMCR - SIU Module Configuration 4-31
	267	*-----------------------------------------------------------------------
	268	*/
6d0f6bcf	269	#define CONFIG_SYS_SIUMCR 0X4205C000
e2211743 WD	270
	271	/*-----------------------------------------------------------------------
	272	* SYPCR - System Protection Control 4-35
	273	* SYPCR can only be written once after reset!
	274	*-----------------------------------------------------------------------
	275	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	276	*/
	277	#if defined (CONFIG_WATCHDOG)
6d0f6bcf	278	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
e2211743 WD	279	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
e2211743 WD	280	#else
6d0f6bcf	281	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
e2211743 WD	282	SYPCR_SWRI\|SYPCR_SWP)
	283	#endif /* CONFIG_WATCHDOG */
	284
	285	/*-----------------------------------------------------------------------
	286	* TMCNTSC - Time Counter Status and Control 4-40
	287	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	288	* and enable Time Counter
	289	*-----------------------------------------------------------------------
	290	*/
6d0f6bcf	291	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
e2211743 WD	292
	293	/*-----------------------------------------------------------------------
	294	* PISCR - Periodic Interrupt Status and Control 4-42
	295	*-----------------------------------------------------------------------
	296	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	297	* Periodic timer
	298	*/
6d0f6bcf	299	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
e2211743 WD	300
	301	/*-----------------------------------------------------------------------
	302	* SCCR - System Clock Control 9-8
	303	*-----------------------------------------------------------------------
	304	* Ensure DFBRG is Divide by 16
	305	*/
6d0f6bcf	306	#define CONFIG_SYS_SCCR 0
e2211743 WD	307
	308	/*-----------------------------------------------------------------------
	309	* RCCR - RISC Controller Configuration 13-7
	310	*-----------------------------------------------------------------------
	311	*/
6d0f6bcf	312	#define CONFIG_SYS_RCCR 0
e2211743 WD	313
	314	/*-----------------------------------------------------------------------
	315	* Init Memory Controller:
	316	*
	317	* Bank Bus Machine PortSz Device
	318	* ---- --- ------- ------ ------
	319	* 0 60x GPCM 64 bit FLASH
	320	* 1 60x SDRAM 64 bit SDRAM
	321	*/
	322
6d0f6bcf JCPV	323	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) \| 0x0801)
	324	#define CONFIG_SYS_OR0_PRELIM 0xFF800882
	325	#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) \| 0x0041)
	326	#define CONFIG_SYS_OR1_PRELIM 0xF8002CD0
e2211743	327
6d0f6bcf JCPV	328	#define CONFIG_SYS_PSDMR 0x404A241A
	329	#define CONFIG_SYS_MPTPR 0x00007400
	330	#define CONFIG_SYS_PSRT 0x00000007
e2211743 WD	331
e2211743 WD	332	#endif /* __CONFIG_H */